hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

drm/nouveau: kill nouveau_dev() + wrap register macros 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-08-10 04:10:22 +10:00
parent fa2bade99a
commit db2bec187d
17 changed files with 228 additions and 219 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/nouveau/dispnv04/arb.c
View File

@ -198,12 +198,12 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
int *burst, int *lwm)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nv_fifo_info fifo_data;
struct nv_sim_state sim_data;
int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
uint32_t cfg1 = nv_rd32(device, NV04_PFB_CFG1);
uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
sim_data.pclk_khz = VClk;
sim_data.mclk_khz = MClk;
@ -221,8 +221,8 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
sim_data.mem_latency = 3;
sim_data.mem_page_miss = 10;
} else {
sim_data.memory_type = nv_rd32(device, NV04_PFB_CFG0) & 0x1;
sim_data.memory_width = (nv_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1;
sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
sim_data.mem_latency = cfg1 & 0xf;
sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
}

46
drivers/gpu/drm/nouveau/dispnv04/dac.c
View File

@ -65,7 +65,7 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)
static int sample_load_twice(struct drm_device *dev, bool sense[2])
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nouveau_timer *ptimer = nouveau_timer(device);
int i;
@ -95,15 +95,15 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2])
udelay(100);
/* when level triggers, sense is _LO_ */
sense_a = nv_rd08(device, NV_PRMCIO_INP0) & 0x10;
sense_a = nvif_rd08(device, NV_PRMCIO_INP0) & 0x10;
/* take another reading until it agrees with sense_a... */
do {
udelay(100);
sense_b = nv_rd08(device, NV_PRMCIO_INP0) & 0x10;
sense_b = nvif_rd08(device, NV_PRMCIO_INP0) & 0x10;
if (sense_a != sense_b) {
sense_b_prime =
nv_rd08(device, NV_PRMCIO_INP0) & 0x10;
nvif_rd08(device, NV_PRMCIO_INP0) & 0x10;
if (sense_b == sense_b_prime) {
/* ... unless two consecutive subsequent
* samples agree; sense_a is replaced */
@ -128,7 +128,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
struct drm_connector *connector)
{
struct drm_device *dev = encoder->dev;
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nouveau_drm *drm = nouveau_drm(dev);
uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
uint8_t saved_palette0[3], saved_palette_mask;
@ -164,11 +164,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);
nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS, 0x0);
nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS, 0x0);
for (i = 0; i < 3; i++)
saved_palette0[i] = nv_rd08(device, NV_PRMDIO_PALETTE_DATA);
saved_palette_mask = nv_rd08(device, NV_PRMDIO_PIXEL_MASK);
nv_wr08(device, NV_PRMDIO_PIXEL_MASK, 0);
saved_palette0[i] = nvif_rd08(device, NV_PRMDIO_PALETTE_DATA);
saved_palette_mask = nvif_rd08(device, NV_PRMDIO_PIXEL_MASK);
nvif_wr08(device, NV_PRMDIO_PIXEL_MASK, 0);
saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL);
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL,
@ -181,11 +181,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
do {
bool sense_pair[2];
nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
nv_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);
nv_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);
nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);
nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);
/* testing blue won't find monochrome monitors. I don't care */
nv_wr08(device, NV_PRMDIO_PALETTE_DATA, blue);
nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, blue);
i = 0;
/* take sample pairs until both samples in the pair agree */
@ -208,11 +208,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
} while (++blue < 0x18 && sense);
out:
nv_wr08(device, NV_PRMDIO_PIXEL_MASK, saved_palette_mask);
nvif_wr08(device, NV_PRMDIO_PIXEL_MASK, saved_palette_mask);
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl);
nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
for (i = 0; i < 3; i++)
nv_wr08(device, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]);
nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]);
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
@ -231,7 +231,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nouveau_gpio *gpio = nouveau_gpio(device);
struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
@ -256,12 +256,12 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,
saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
saved_powerctrl_2 = nv_rd32(device, NV_PBUS_POWERCTRL_2);
saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2);
nv_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
if (regoffset == 0x68) {
saved_powerctrl_4 = nv_rd32(device, NV_PBUS_POWERCTRL_4);
nv_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4);
nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
}
if (gpio) {
@ -316,8 +316,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput);
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
if (regoffset == 0x68)
nv_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
nv_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
if (gpio) {
gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1);

6
drivers/gpu/drm/nouveau/dispnv04/dfp.c
View File

@ -281,7 +281,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *adjusted_mode)
{
struct drm_device *dev = encoder->dev;
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
@ -335,7 +335,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
else /* gpu needs to scale */
regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
if (nv_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
output_mode->clock > 165000)
@ -485,7 +485,7 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
{
#ifdef __powerpc__
struct drm_device *dev = encoder->dev;
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
/* BIOS scripts usually take care of the backlight, thanks
* Apple for your consistency.

4
drivers/gpu/drm/nouveau/dispnv04/disp.h
View File

@ -171,8 +171,8 @@ static inline void
nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
struct dcb_output *outp, int crtc)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_bios *bios = nouveau_bios(device);
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_bios *bios = nouveau_bios(drm->device);
struct nvbios_init init = {
.subdev = nv_subdev(bios),
.bios = bios,

46
drivers/gpu/drm/nouveau/dispnv04/hw.c
View File

@ -168,7 +168,7 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
struct nouveau_pll_vals *pllvals)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct nouveau_bios *bios = nouveau_bios(device);
uint32_t reg1, pll1, pll2 = 0;
struct nvbios_pll pll_lim;
@ -178,13 +178,13 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
if (ret || !(reg1 = pll_lim.reg))
return -ENOENT;
pll1 = nv_rd32(device, reg1);
pll1 = nvif_rd32(device, reg1);
if (reg1 <= 0x405c)
pll2 = nv_rd32(device, reg1 + 4);
pll2 = nvif_rd32(device, reg1 + 4);
else if (nv_two_reg_pll(dev)) {
uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
pll2 = nv_rd32(device, reg2);
pll2 = nvif_rd32(device, reg2);
}
if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
@ -255,7 +255,7 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
*/
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct nouveau_clock *clk = nouveau_clock(device);
struct nouveau_bios *bios = nouveau_bios(device);
struct nvbios_pll pll_lim;
@ -663,7 +663,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct nouveau_timer *ptimer = nouveau_timer(device);
struct nouveau_fb *pfb = nouveau_fb(device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
@ -678,15 +678,15 @@ nv_load_state_ext(struct drm_device *dev, int head,
*/
NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
nv_wr32(device, NV_PVIDEO_STOP, 1);
nv_wr32(device, NV_PVIDEO_INTR_EN, 0);
nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
nv_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1);
nv_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1);
nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1);
nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1);
nv_wr32(device, NV_PBUS_POWERCTRL_2, 0);
nvif_wr32(device, NV_PVIDEO_STOP, 1);
nvif_wr32(device, NV_PVIDEO_INTR_EN, 0);
nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
nvif_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1);
nvif_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1);
nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1);
nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1);
nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
@ -769,15 +769,15 @@ static void
nv_save_state_palette(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
int head_offset = head * NV_PRMDIO_SIZE, i;
nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
NV_PRMDIO_PIXEL_MASK_MASK);
nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
for (i = 0; i < 768; i++) {
state->crtc_reg[head].DAC[i] = nv_rd08(device,
state->crtc_reg[head].DAC[i] = nvif_rd08(device,
NV_PRMDIO_PALETTE_DATA + head_offset);
}
@ -788,15 +788,15 @@ void
nouveau_hw_load_state_palette(struct drm_device *dev, int head,
struct nv04_mode_state *state)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
int head_offset = head * NV_PRMDIO_SIZE, i;
nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
NV_PRMDIO_PIXEL_MASK_MASK);
nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
for (i = 0; i < 768; i++) {
nv_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
state->crtc_reg[head].DAC[i]);
}

68
drivers/gpu/drm/nouveau/dispnv04/hw.h
View File

@ -60,41 +60,41 @@ extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
static inline uint32_t NVReadCRTC(struct drm_device *dev,
int head, uint32_t reg)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
uint32_t val;
if (head)
reg += NV_PCRTC0_SIZE;
val = nv_rd32(device, reg);
val = nvif_rd32(device, reg);
return val;
}
static inline void NVWriteCRTC(struct drm_device *dev,
int head, uint32_t reg, uint32_t val)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
if (head)
reg += NV_PCRTC0_SIZE;
nv_wr32(device, reg, val);
nvif_wr32(device, reg, val);
}
static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
int head, uint32_t reg)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
uint32_t val;
if (head)
reg += NV_PRAMDAC0_SIZE;
val = nv_rd32(device, reg);
val = nvif_rd32(device, reg);
return val;
}
static inline void NVWriteRAMDAC(struct drm_device *dev,
int head, uint32_t reg, uint32_t val)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
if (head)
reg += NV_PRAMDAC0_SIZE;
nv_wr32(device, reg, val);
nvif_wr32(device, reg, val);
}
static inline uint8_t nv_read_tmds(struct drm_device *dev,
@ -120,18 +120,18 @@ static inline void nv_write_tmds(struct drm_device *dev,
static inline void NVWriteVgaCrtc(struct drm_device *dev,
int head, uint8_t index, uint8_t value)
{
struct nouveau_device *device = nouveau_dev(dev);
nv_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
nv_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
struct nouveau_object *device = nouveau_drm(dev)->device;
nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
}
static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
int head, uint8_t index)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
uint8_t val;
nv_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
val = nv_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
return val;
}
@ -165,7 +165,7 @@ static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_
static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
int head, uint32_t reg)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nouveau_drm *drm = nouveau_drm(dev);
uint8_t val;
@ -174,14 +174,14 @@ static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
if (head && nv_device(drm->device)->card_type == NV_40)
reg += NV_PRMVIO_SIZE;
val = nv_rd08(device, reg);
val = nvif_rd08(device, reg);
return val;
}
static inline void NVWritePRMVIO(struct drm_device *dev,
int head, uint32_t reg, uint8_t value)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nouveau_drm *drm = nouveau_drm(dev);
/* Only NV4x have two pvio ranges; other twoHeads cards MUST call
@ -189,50 +189,50 @@ static inline void NVWritePRMVIO(struct drm_device *dev,
if (head && nv_device(drm->device)->card_type == NV_40)
reg += NV_PRMVIO_SIZE;
nv_wr08(device, reg, value);
nvif_wr08(device, reg, value);
}
static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
{
struct nouveau_device *device = nouveau_dev(dev);
nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
struct nouveau_object *device = nouveau_drm(dev)->device;
nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
}
static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
{
struct nouveau_device *device = nouveau_dev(dev);
nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
return !(nv_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
struct nouveau_object *device = nouveau_drm(dev)->device;
nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
}
static inline void NVWriteVgaAttr(struct drm_device *dev,
int head, uint8_t index, uint8_t value)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
if (NVGetEnablePalette(dev, head))
index &= ~0x20;
else
index |= 0x20;
nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
nv_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
}
static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
int head, uint8_t index)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
uint8_t val;
if (NVGetEnablePalette(dev, head))
index &= ~0x20;
else
index |= 0x20;
nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
val = nv_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
val = nvif_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
return val;
}
@ -259,11 +259,11 @@ static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
static inline bool
nv_heads_tied(struct drm_device *dev)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nouveau_drm *drm = nouveau_drm(dev);
if (nv_device(drm->device)->chipset == 0x11)
return !!(nv_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4;
}

110
drivers/gpu/drm/nouveau/dispnv04/overlay.c
View File

@ -96,7 +96,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h)
{
struct nouveau_device *dev = nouveau_dev(plane->dev);
struct nouveau_object *dev = nouveau_drm(plane->dev)->device;
struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
@ -117,7 +117,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
if (format > 0xffff)
return -ERANGE;
if (dev->chipset >= 0x30) {
if (nv_device(dev)->chipset >= 0x30) {
if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1))
return -ERANGE;
} else {
@ -131,17 +131,17 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
nv_plane->cur = nv_fb->nvbo;
nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY);
nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);
nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY);
nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);
nv_wr32(dev, NV_PVIDEO_BASE(flip), 0);
nv_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset);
nv_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w);
nv_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x);
nv_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w);
nv_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h);
nv_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x);
nv_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w);
nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0);
nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset);
nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w);
nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x);
nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w);
nvif_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h);
nvif_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x);
nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w);
if (fb->pixel_format != DRM_FORMAT_UYVY)
format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8;
@ -153,14 +153,14 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY;
if (fb->pixel_format == DRM_FORMAT_NV12) {
nv_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0);
nv_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),
nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0);
nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),
nv_fb->nvbo->bo.offset + fb->offsets[1]);
}
nv_wr32(dev, NV_PVIDEO_FORMAT(flip), format);
nv_wr32(dev, NV_PVIDEO_STOP, 0);
nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format);
nvif_wr32(dev, NV_PVIDEO_STOP, 0);
/* TODO: wait for vblank? */
nv_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1);
nvif_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1);
nv_plane->flip = !flip;
if (cur)
@ -172,10 +172,10 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
static int
nv10_disable_plane(struct drm_plane *plane)
{
struct nouveau_device *dev = nouveau_dev(plane->dev);
struct nouveau_object *dev = nouveau_drm(plane->dev)->device;
struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
nv_wr32(dev, NV_PVIDEO_STOP, 1);
nvif_wr32(dev, NV_PVIDEO_STOP, 1);
if (nv_plane->cur) {
nouveau_bo_unpin(nv_plane->cur);
nv_plane->cur = NULL;
@ -195,24 +195,24 @@ nv_destroy_plane(struct drm_plane *plane)
static void
nv10_set_params(struct nouveau_plane *plane)
{
struct nouveau_device *dev = nouveau_dev(plane->base.dev);
struct nouveau_object *dev = nouveau_drm(plane->base.dev)->device;
u32 luma = (plane->brightness - 512) << 16 | plane->contrast;
u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) |
(cos_mul(plane->hue, plane->saturation) & 0xffff);
u32 format = 0;
nv_wr32(dev, NV_PVIDEO_LUMINANCE(0), luma);
nv_wr32(dev, NV_PVIDEO_LUMINANCE(1), luma);
nv_wr32(dev, NV_PVIDEO_CHROMINANCE(0), chroma);
nv_wr32(dev, NV_PVIDEO_CHROMINANCE(1), chroma);
nv_wr32(dev, NV_PVIDEO_COLOR_KEY, plane->colorkey & 0xffffff);
nvif_wr32(dev, NV_PVIDEO_LUMINANCE(0), luma);
nvif_wr32(dev, NV_PVIDEO_LUMINANCE(1), luma);
nvif_wr32(dev, NV_PVIDEO_CHROMINANCE(0), chroma);
nvif_wr32(dev, NV_PVIDEO_CHROMINANCE(1), chroma);
nvif_wr32(dev, NV_PVIDEO_COLOR_KEY, plane->colorkey & 0xffffff);
if (plane->cur) {
if (plane->iturbt_709)
format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709;
if (plane->colorkey & (1 << 24))
format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY;
nv_mask(dev, NV_PVIDEO_FORMAT(plane->flip),
nvif_mask(dev, NV_PVIDEO_FORMAT(plane->flip),
NV_PVIDEO_FORMAT_MATRIX_ITURBT709 |
NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY,
format);
@ -343,7 +343,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h)
{
struct nouveau_device *dev = nouveau_dev(plane->dev);
struct nouveau_object *dev = nouveau_drm(plane->dev)->device;
struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
struct nouveau_bo *cur = nv_plane->cur;
@ -375,43 +375,43 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
nv_plane->cur = nv_fb->nvbo;
nv_wr32(dev, NV_PVIDEO_OE_STATE, 0);
nv_wr32(dev, NV_PVIDEO_SU_STATE, 0);
nv_wr32(dev, NV_PVIDEO_RM_STATE, 0);
nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0);
nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0);
nvif_wr32(dev, NV_PVIDEO_RM_STATE, 0);
for (i = 0; i < 2; i++) {
nv_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i,
nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i,
nv_fb->nvbo->bo.offset);
nv_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch);
nv_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0);
nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch);
nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0);
}
nv_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x);
nv_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w);
nv_wr32(dev, NV_PVIDEO_STEP_SIZE,
nvif_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x);
nvif_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w);
nvif_wr32(dev, NV_PVIDEO_STEP_SIZE,
(uint32_t)(((src_h - 1) << 11) / (crtc_h - 1)) << 16 | (uint32_t)(((src_w - 1) << 11) / (crtc_w - 1)));
/* It should be possible to convert hue/contrast to this */
nv_wr32(dev, NV_PVIDEO_RED_CSC_OFFSET, 0x69 - brightness);
nv_wr32(dev, NV_PVIDEO_GREEN_CSC_OFFSET, 0x3e + brightness);
nv_wr32(dev, NV_PVIDEO_BLUE_CSC_OFFSET, 0x89 - brightness);
nv_wr32(dev, NV_PVIDEO_CSC_ADJUST, 0);
nvif_wr32(dev, NV_PVIDEO_RED_CSC_OFFSET, 0x69 - brightness);
nvif_wr32(dev, NV_PVIDEO_GREEN_CSC_OFFSET, 0x3e + brightness);
nvif_wr32(dev, NV_PVIDEO_BLUE_CSC_OFFSET, 0x89 - brightness);
nvif_wr32(dev, NV_PVIDEO_CSC_ADJUST, 0);
nv_wr32(dev, NV_PVIDEO_CONTROL_Y, 0x001); /* (BLUR_ON, LINE_HALF) */
nv_wr32(dev, NV_PVIDEO_CONTROL_X, 0x111); /* (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */
nvif_wr32(dev, NV_PVIDEO_CONTROL_Y, 0x001); /* (BLUR_ON, LINE_HALF) */
nvif_wr32(dev, NV_PVIDEO_CONTROL_X, 0x111); /* (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */
nv_wr32(dev, NV_PVIDEO_FIFO_BURST_LENGTH, 0x03);
nv_wr32(dev, NV_PVIDEO_FIFO_THRES_SIZE, 0x38);
nvif_wr32(dev, NV_PVIDEO_FIFO_BURST_LENGTH, 0x03);
nvif_wr32(dev, NV_PVIDEO_FIFO_THRES_SIZE, 0x38);
nv_wr32(dev, NV_PVIDEO_KEY, nv_plane->colorkey);
nvif_wr32(dev, NV_PVIDEO_KEY, nv_plane->colorkey);
if (nv_plane->colorkey & (1 << 24))
overlay |= 0x10;
if (fb->pixel_format == DRM_FORMAT_YUYV)
overlay |= 0x100;
nv_wr32(dev, NV_PVIDEO_OVERLAY, overlay);
nvif_wr32(dev, NV_PVIDEO_OVERLAY, overlay);
nv_wr32(dev, NV_PVIDEO_SU_STATE, nv_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16));
nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16));
if (cur)
nouveau_bo_unpin(cur);
@ -422,13 +422,13 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
static int
nv04_disable_plane(struct drm_plane *plane)
{
struct nouveau_device *dev = nouveau_dev(plane->dev);
struct nouveau_object *dev = nouveau_drm(plane->dev)->device;
struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
nv_mask(dev, NV_PVIDEO_OVERLAY, 1, 0);
nv_wr32(dev, NV_PVIDEO_OE_STATE, 0);
nv_wr32(dev, NV_PVIDEO_SU_STATE, 0);
nv_wr32(dev, NV_PVIDEO_RM_STATE, 0);
nvif_mask(dev, NV_PVIDEO_OVERLAY, 1, 0);
nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0);
nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0);
nvif_wr32(dev, NV_PVIDEO_RM_STATE, 0);
if (nv_plane->cur) {
nouveau_bo_unpin(nv_plane->cur);
nv_plane->cur = NULL;
@ -489,9 +489,9 @@ err:
void
nouveau_overlay_init(struct drm_device *device)
{
struct nouveau_device *dev = nouveau_dev(device);
if (dev->chipset < 0x10)
struct nouveau_object *dev = nouveau_drm(device)->device;
if (nv_device(dev)->chipset < 0x10)
nv04_overlay_init(device);
else if (dev->chipset <= 0x40)
else if (nv_device(dev)->chipset <= 0x40)
nv10_overlay_init(device);
}

8
drivers/gpu/drm/nouveau/dispnv04/tvnv17.h
View File

@ -130,14 +130,14 @@ void nv17_ctv_update_rescaler(struct drm_encoder *encoder);
static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
uint32_t val)
{
struct nouveau_device *device = nouveau_dev(dev);
nv_wr32(device, reg, val);
struct nouveau_object *device = nouveau_drm(dev)->device;
nvif_wr32(device, reg, val);
}
static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
{
struct nouveau_device *device = nouveau_dev(dev);
return nv_rd32(device, reg);
struct nouveau_object *device = nouveau_drm(dev)->device;
return nvif_rd32(device, reg);
}
static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,

14
drivers/gpu/drm/nouveau/nouveau_agp.c
View File

@ -104,7 +104,7 @@ void
nouveau_agp_reset(struct nouveau_drm *drm)
{
#if __OS_HAS_AGP
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct drm_device *dev = drm->dev;
u32 save[2];
int ret;
@ -115,7 +115,7 @@ nouveau_agp_reset(struct nouveau_drm *drm)
/* First of all, disable fast writes, otherwise if it's
* already enabled in the AGP bridge and we disable the card's
* AGP controller we might be locking ourselves out of it. */
if ((nv_rd32(device, NV04_PBUS_PCI_NV_19) |
if ((nvif_rd32(device, NV04_PBUS_PCI_NV_19) |
dev->agp->mode) & PCI_AGP_COMMAND_FW) {
struct drm_agp_info info;
struct drm_agp_mode mode;
@ -134,15 +134,15 @@ nouveau_agp_reset(struct nouveau_drm *drm)
/* clear busmaster bit, and disable AGP */
save[0] = nv_mask(device, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000);
nv_wr32(device, NV04_PBUS_PCI_NV_19, 0);
save[0] = nvif_mask(device, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000);
nvif_wr32(device, NV04_PBUS_PCI_NV_19, 0);
/* reset PGRAPH, PFIFO and PTIMER */
save[1] = nv_mask(device, 0x000200, 0x00011100, 0x00000000);
nv_mask(device, 0x000200, 0x00011100, save[1]);
save[1] = nvif_mask(device, 0x000200, 0x00011100, 0x00000000);
nvif_mask(device, 0x000200, 0x00011100, save[1]);
/* and restore bustmaster bit (gives effect of resetting AGP) */
nv_wr32(device, NV04_PBUS_PCI_NV_1, save[0]);
nvif_wr32(device, NV04_PBUS_PCI_NV_1, save[0]);
#endif
}

48
drivers/gpu/drm/nouveau/nouveau_backlight.c
View File

@ -40,8 +40,8 @@ static int
nv40_get_intensity(struct backlight_device *bd)
{
struct nouveau_drm *drm = bl_get_data(bd);
struct nouveau_device *device = nv_device(drm->device);
int val = (nv_rd32(device, NV40_PMC_BACKLIGHT) &
struct nouveau_object *device = drm->device;
int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) &
NV40_PMC_BACKLIGHT_MASK) >> 16;
return val;
@ -51,11 +51,11 @@ static int
nv40_set_intensity(struct backlight_device *bd)
{
struct nouveau_drm *drm = bl_get_data(bd);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
int val = bd->props.brightness;
int reg = nv_rd32(device, NV40_PMC_BACKLIGHT);
int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT);
nv_wr32(device, NV40_PMC_BACKLIGHT,
nvif_wr32(device, NV40_PMC_BACKLIGHT,
(val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK));
return 0;
@ -71,11 +71,11 @@ static int
nv40_backlight_init(struct drm_connector *connector)
{
struct nouveau_drm *drm = nouveau_drm(connector->dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct backlight_properties props;
struct backlight_device *bd;
if (!(nv_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK))
if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK))
return 0;
memset(&props, 0, sizeof(struct backlight_properties));
@ -97,12 +97,12 @@ nv50_get_intensity(struct backlight_device *bd)
{
struct nouveau_encoder *nv_encoder = bl_get_data(bd);
struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
int or = nv_encoder->or;
u32 div = 1025;
u32 val;
val = nv_rd32(device, NV50_PDISP_SOR_PWM_CTL(or));
val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or));
val &= NV50_PDISP_SOR_PWM_CTL_VAL;
return ((val * 100) + (div / 2)) / div;
}
@ -112,12 +112,12 @@ nv50_set_intensity(struct backlight_device *bd)
{
struct nouveau_encoder *nv_encoder = bl_get_data(bd);
struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
int or = nv_encoder->or;
u32 div = 1025;
u32 val = (bd->props.brightness * div) / 100;
nv_wr32(device, NV50_PDISP_SOR_PWM_CTL(or),
nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or),
NV50_PDISP_SOR_PWM_CTL_NEW | val);
return 0;
}
@ -133,12 +133,12 @@ nva3_get_intensity(struct backlight_device *bd)
{
struct nouveau_encoder *nv_encoder = bl_get_data(bd);
struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
int or = nv_encoder->or;
u32 div, val;
div = nv_rd32(device, NV50_PDISP_SOR_PWM_DIV(or));
val = nv_rd32(device, NV50_PDISP_SOR_PWM_CTL(or));
div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or));
val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or));
val &= NVA3_PDISP_SOR_PWM_CTL_VAL;
if (div && div >= val)
return ((val * 100) + (div / 2)) / div;
@ -151,14 +151,14 @@ nva3_set_intensity(struct backlight_device *bd)
{
struct nouveau_encoder *nv_encoder = bl_get_data(bd);
struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
int or = nv_encoder->or;
u32 div, val;
div = nv_rd32(device, NV50_PDISP_SOR_PWM_DIV(or));
div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or));
val = (bd->props.brightness * div) / 100;
if (div) {
nv_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), val |
nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), val |
NV50_PDISP_SOR_PWM_CTL_NEW |
NVA3_PDISP_SOR_PWM_CTL_UNK);
return 0;
@ -177,7 +177,7 @@ static int
nv50_backlight_init(struct drm_connector *connector)
{
struct nouveau_drm *drm = nouveau_drm(connector->dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct nouveau_encoder *nv_encoder;
struct backlight_properties props;
struct backlight_device *bd;
@ -190,12 +190,12 @@ nv50_backlight_init(struct drm_connector *connector)
return -ENODEV;
}
if (!nv_rd32(device, NV50_PDISP_SOR_PWM_CTL(nv_encoder->or)))
if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(nv_encoder->or)))
return 0;
if (device->chipset <= 0xa0 ||
device->chipset == 0xaa ||
device->chipset == 0xac)
if (nv_device(device)->chipset <= 0xa0 ||
nv_device(device)->chipset == 0xaa ||
nv_device(device)->chipset == 0xac)
ops = &nv50_bl_ops;
else
ops = &nva3_bl_ops;
@ -218,7 +218,7 @@ int
nouveau_backlight_init(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct drm_connector *connector;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
@ -226,7 +226,7 @@ nouveau_backlight_init(struct drm_device *dev)
connector->connector_type != DRM_MODE_CONNECTOR_eDP)
continue;
switch (device->card_type) {
switch (nv_device(device)->card_type) {
case NV_40:
return nv40_backlight_init(connector);
case NV_50:

26
drivers/gpu/drm/nouveau/nouveau_bios.c
View File

@ -217,7 +217,7 @@ int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head
*/
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct nvbios *bios = &drm->vbios;
uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
uint32_t sel_clk_binding, sel_clk;
@ -240,7 +240,7 @@ int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head
NV_INFO(drm, "Calling LVDS script %d:\n", script);
/* don't let script change pll->head binding */
sel_clk_binding = nv_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
if (lvds_ver < 0x30)
ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
@ -252,7 +252,7 @@ int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head
sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
/* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
nv_wr32(device, NV_PBUS_POWERCTRL_2, 0);
nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
return ret;
}
@ -320,7 +320,7 @@ static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct n
static int
get_fp_strap(struct drm_device *dev, struct nvbios *bios)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
/*
* The fp strap is normally dictated by the "User Strap" in
@ -334,10 +334,10 @@ get_fp_strap(struct drm_device *dev, struct nvbios *bios)
if (bios->major_version < 5 && bios->data[0x48] & 0x4)
return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
if (device->card_type >= NV_50)
return (nv_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
if (nv_device(device)->card_type >= NV_50)
return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
else
return (nv_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
}
static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
@ -636,7 +636,7 @@ int run_tmds_table(struct drm_device *dev, struct dcb_output *dcbent, int head,
*/
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
struct nvbios *bios = &drm->vbios;
int cv = bios->chip_version;
uint16_t clktable = 0, scriptptr;
@ -670,7 +670,7 @@ int run_tmds_table(struct drm_device *dev, struct dcb_output *dcbent, int head,
}
/* don't let script change pll->head binding */
sel_clk_binding = nv_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
@ -1908,7 +1908,7 @@ static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bio
*/
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *device = drm->device;
uint8_t bytes_to_write;
uint16_t hwsq_entry_offset;
int i;
@ -1931,15 +1931,15 @@ static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bio
hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
/* set sequencer control */
nv_wr32(device, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
nvif_wr32(device, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
bytes_to_write -= 4;
/* write ucode */
for (i = 0; i < bytes_to_write; i += 4)
nv_wr32(device, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
nvif_wr32(device, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
/* twiddle NV_PBUS_DEBUG_4 */
nv_wr32(device, NV_PBUS_DEBUG_4, nv_rd32(device, NV_PBUS_DEBUG_4) | 0x18);
nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18);
return 0;
}

2
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -1262,7 +1262,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
/* fallthrough, tiled memory */
case TTM_PL_VRAM:
mem->bus.offset = mem->start << PAGE_SHIFT;
mem->bus.base = nv_device_resource_start(nouveau_dev(dev), 1);
mem->bus.base = nv_device_resource_start(nv_device(drm->device), 1);
mem->bus.is_iomem = true;
if (nv_device(drm->device)->card_type >= NV_50) {
struct nouveau_bar *bar = nouveau_bar(drm->device);

3
drivers/gpu/drm/nouveau/nouveau_display.c
View File

@ -433,7 +433,6 @@ int
nouveau_display_create(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_display *disp;
int ret;
@ -446,7 +445,7 @@ nouveau_display_create(struct drm_device *dev)
drm_mode_create_dvi_i_properties(dev);
dev->mode_config.funcs = &nouveau_mode_config_funcs;
dev->mode_config.fb_base = nv_device_resource_start(device, 1);
dev->mode_config.fb_base = nv_device_resource_start(nv_device(drm->device), 1);
dev->mode_config.min_width = 0;
dev->mode_config.min_height = 0;

10
drivers/gpu/drm/nouveau/nouveau_drm.c
View File

@ -348,7 +348,6 @@ static int
nouveau_drm_load(struct drm_device *dev, unsigned long flags)
{
struct pci_dev *pdev = dev->pdev;
struct nouveau_device *device;
struct nouveau_drm *drm;
int ret;
@ -406,14 +405,13 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
* nosnoop capability. hopefully won't cause issues until a
* better fix is found - assuming there is one...
*/
device = nv_device(drm->device);
if (nv_device(drm->device)->chipset == 0xc1)
nv_mask(device, 0x00088080, 0x00000800, 0x00000000);
nvif_mask(drm->device, 0x00088080, 0x00000800, 0x00000000);
nouveau_vga_init(drm);
nouveau_agp_init(drm);
if (device->card_type >= NV_50) {
if (nv_device(drm->device)->card_type >= NV_50) {
ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40),
0x1000, &drm->client.vm);
if (ret)
@ -932,7 +930,7 @@ static int nouveau_pmops_runtime_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct drm_device *drm_dev = pci_get_drvdata(pdev);
struct nouveau_device *device = nouveau_dev(drm_dev);
struct nouveau_object *device = nouveau_drm(drm_dev)->device;
int ret;
if (nouveau_runtime_pm == 0)
@ -948,7 +946,7 @@ static int nouveau_pmops_runtime_resume(struct device *dev)
ret = nouveau_do_resume(drm_dev);
drm_kms_helper_poll_enable(drm_dev);
/* do magic */
nv_mask(device, 0x88488, (1 << 25), (1 << 25));
nvif_mask(device, 0x88488, (1 << 25), (1 << 25));
vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
nv_debug_level(NORMAL);

22
drivers/gpu/drm/nouveau/nouveau_drm.h
View File

@ -77,6 +77,22 @@ nouveau_cli(struct drm_file *fpriv)
return fpriv ? fpriv->driver_priv : NULL;
}
#define nvif_object(a) ({ \
struct nouveau_object *_object = (a); \
_object; \
})
#define nvif_rd08(a,b) nv_ro08(nvif_object(a), (b))
#define nvif_rd16(a,b) nv_ro16(nvif_object(a), (b))
#define nvif_rd32(a,b) nv_ro32(nvif_object(a), (b))
#define nvif_wr08(a,b,c) nv_wo08(nvif_object(a), (b), (c))
#define nvif_wr16(a,b,c) nv_wo16(nvif_object(a), (b), (c))
#define nvif_wr32(a,b,c) nv_wo32(nvif_object(a), (b), (c))
#define nvif_mask(a,b,c,d) nv_mo32(nvif_object(a), (b), (c), (d))
/*XXX*/
#include <core/object.h>
#define nvkm_object(a) nvif_object(a)
extern int nouveau_runtime_pm;
struct nouveau_drm {
@ -152,12 +168,6 @@ nouveau_drm(struct drm_device *dev)
return dev->dev_private;
}
static inline struct nouveau_device *
nouveau_dev(struct drm_device *dev)
{
return nv_device(nouveau_drm(dev)->device);
}
int nouveau_pmops_suspend(struct device *);
int nouveau_pmops_resume(struct device *);

14
drivers/gpu/drm/nouveau/nouveau_vga.c
View File

@ -12,14 +12,16 @@
static unsigned int
nouveau_vga_set_decode(void *priv, bool state)
{
struct nouveau_device *device = nouveau_dev(priv);
struct nouveau_object *device = nouveau_drm(priv)->device;
if (device->card_type == NV_40 && device->chipset >= 0x4c)
nv_wr32(device, 0x088060, state);
else if (device->chipset >= 0x40)
nv_wr32(device, 0x088054, state);
if (nv_device(device)->card_type == NV_40 &&
nv_device(device)->chipset >= 0x4c)
nvif_wr32(device, 0x088060, state);
else
nv_wr32(device, 0x001854, state);
if (nv_device(device)->chipset >= 0x40)
nvif_wr32(device, 0x088054, state);
else
nvif_wr32(device, 0x001854, state);
if (state)
return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |

12
drivers/gpu/drm/nouveau/nv50_display.c
View File

@ -317,7 +317,7 @@ evo_sync_wait(void *data)
static int
evo_sync(struct drm_device *dev)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nv50_disp *disp = nv50_disp(dev);
struct nv50_mast *mast = nv50_mast(dev);
u32 *push = evo_wait(mast, 8);
@ -329,7 +329,7 @@ evo_sync(struct drm_device *dev)
evo_data(push, 0x00000000);
evo_data(push, 0x00000000);
evo_kick(push, mast);
if (nv_wait_cb(device, evo_sync_wait, disp->sync))
if (nv_wait_cb(nv_device(device), evo_sync_wait, disp->sync))
return 0;
}
@ -364,7 +364,7 @@ nv50_display_flip_wait(void *data)
void
nv50_display_flip_stop(struct drm_crtc *crtc)
{
struct nouveau_device *device = nouveau_dev(crtc->dev);
struct nouveau_object *device = nouveau_drm(crtc->dev)->device;
struct nv50_display_flip flip = {
.disp = nv50_disp(crtc->dev),
.chan = nv50_sync(crtc),
@ -384,7 +384,7 @@ nv50_display_flip_stop(struct drm_crtc *crtc)
evo_kick(push, flip.chan);
}
nv_wait_cb(device, nv50_display_flip_wait, &flip);
nv_wait_cb(nv_device(device), nv50_display_flip_wait, &flip);
}
int
@ -2245,7 +2245,7 @@ nv50_display_destroy(struct drm_device *dev)
int
nv50_display_create(struct drm_device *dev)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_object *device = nouveau_drm(dev)->device;
struct nouveau_drm *drm = nouveau_drm(dev);
struct dcb_table *dcb = &drm->vbios.dcb;
struct drm_connector *connector, *tmp;
@ -2294,7 +2294,7 @@ nv50_display_create(struct drm_device *dev)
/* create crtc objects to represent the hw heads */
if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
crtcs = nv_rd32(device, 0x022448);
crtcs = nvif_rd32(device, 0x022448);
else
crtcs = 2;