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drm/tilcdc: fixing off by one errors found on analyzer 

When hooking up to an HDMI analyzer noticed some timings were
off by one.  Referring to the hardware technical reference manual
for the lcd controller some of the timing registers use 0 to
represent 1.  This patch addresses that issue.

Signed-off-by: Darren Etheridge <detheridge@ti.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Darren Etheridge 2013-06-21 13:52:24 -05:00 committed by Dave Airlie
parent 4e56434687
commit db2b4bd09b
1 changed files with 12 additions and 7 deletions
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19
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
View File

@ -289,17 +289,22 @@ static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
/*
* subtract one from hfp, hbp, hsw because the hardware uses
* a value of 0 as 1
*/
if (priv->rev == 2) {
reg |= (hfp & 0x300) >> 8;
reg |= (hbp & 0x300) >> 4;
reg |= (hsw & 0x3c0) << 21;
reg |= ((hfp-1) & 0x300) >> 8;
reg |= ((hbp-1) & 0x300) >> 4;
reg |= ((hsw-1) & 0x3c0) << 21;
}
tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
reg = (((mode->hdisplay >> 4) - 1) << 4) |
((hbp & 0xff) << 24) |
((hfp & 0xff) << 16) |
((hsw & 0x3f) << 10);
(((hbp-1) & 0xff) << 24) |
(((hfp-1) & 0xff) << 16) |
(((hsw-1) & 0x3f) << 10);
if (priv->rev == 2)
reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
@ -307,7 +312,7 @@ static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
reg = ((mode->vdisplay - 1) & 0x3ff) |
((vbp & 0xff) << 24) |
((vfp & 0xff) << 16) |
((vsw & 0x3f) << 10);
(((vsw-1) & 0x3f) << 10);
tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
/*