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net: phy: dp83867: perform soft reset and retain established link 

Current logic is performing hard reset and causing the programmed
registers to be wiped out.

as per datasheet: https://www.ti.com/lit/ds/symlink/dp83867cr.pdf
8.6.26 Control Register (CTRL)

do SW_RESTART to perform a reset not including the registers,
If performed when link is already present,
it will drop the link and trigger re-auto negotiation.

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Geet Modi <geet.modi@ti.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Praneeth Bajjuri 2021-06-09 19:43:42 -05:00 committed by David S. Miller
parent 232e3683b4
commit da9ef50f54
1 changed files with 1 additions and 5 deletions
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6
drivers/net/phy/dp83867.c
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@ -826,16 +826,12 @@ static int dp83867_phy_reset(struct phy_device *phydev)
{ {
int err; int err;
err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
if (err < 0) if (err < 0)
return err; return err;
usleep_range(10, 20); usleep_range(10, 20);
/* After reset FORCE_LINK_GOOD bit is set. Although the
* default value should be unset. Disable FORCE_LINK_GOOD
* for the phy to work properly.
*/
return phy_modify(phydev, MII_DP83867_PHYCTRL, return phy_modify(phydev, MII_DP83867_PHYCTRL,
DP83867_PHYCR_FORCE_LINK_GOOD, 0); DP83867_PHYCR_FORCE_LINK_GOOD, 0);
} }