[PATCH] S2io: Multi buffer mode support
Hi, This patch provides dynamic two buffer-mode and 3 buffer-mode options. Previously 2 buffer-mode was compilation option. Now with this patch applied one can load driver in 2 buffer-mode with module-load parameter ie. #insmod s2io.ko rx_ring_mode=2 This patch also provides 3 buffer-mode which provides header separation functionality. In 3 buffer-mode skb->data will have L2/L3/L4 headers and "skb_shinfo(skb)->frag_list->data" will have have L4 payload. one can load driver in 3 buffer-mode with same above module-load parameter ie. #insmod s2io.ko rx_ring_mode=3 Please review the patch. Signed-off-by: Ananda Raju <ananda.raju@neterion.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Ananda Raju
Jeff Garzik
parent
29b09fcc34
commit
da6971d8ec
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@ -2258,17 +2258,6 @@ config S2IO_NAPI
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If in doubt, say N.
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config 2BUFF_MODE
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bool "Use 2 Buffer Mode on Rx side."
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depends on S2IO
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---help---
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On enabling the 2 buffer mode, the received frame will be
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split into 2 parts before being DMA'ed to the hosts memory.
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The parts are the ethernet header and ethernet payload.
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This is useful on systems where DMA'ing to to unaligned
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physical memory loactions comes with a heavy price.
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If not sure please say N.
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endmenu
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if !UML
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File diff suppressed because it is too large
Load Diff
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@ -418,7 +418,7 @@ typedef struct list_info_hold {
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void *list_virt_addr;
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} list_info_hold_t;
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/* Rx descriptor structure */
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/* Rx descriptor structure for 1 buffer mode */
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typedef struct _RxD_t {
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u64 Host_Control; /* reserved for host */
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u64 Control_1;
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@ -439,49 +439,54 @@ typedef struct _RxD_t {
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#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
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#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
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#ifndef CONFIG_2BUFF_MODE
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#define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14)
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#define SET_BUFFER0_SIZE(val) vBIT(val,2,14)
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#else
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#define MASK_BUFFER0_SIZE vBIT(0xFF,2,14)
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#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
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#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
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#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
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#define SET_BUFFER1_SIZE(val) vBIT(val,16,16)
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#define SET_BUFFER2_SIZE(val) vBIT(val,32,16)
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#endif
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#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
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#define SET_VLAN_TAG(val) vBIT(val,48,16)
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#define SET_NUM_TAG(val) vBIT(val,16,32)
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#ifndef CONFIG_2BUFF_MODE
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#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
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#else
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#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
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>> 48)
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#define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \
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>> 32)
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#define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \
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>> 16)
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} RxD_t;
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/* Rx descriptor structure for 1 buffer mode */
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typedef struct _RxD1_t {
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struct _RxD_t h;
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#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
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#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
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#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
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(u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
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u64 Buffer0_ptr;
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} RxD1_t;
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/* Rx descriptor structure for 3 or 2 buffer mode */
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typedef struct _RxD3_t {
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struct _RxD_t h;
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#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
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#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
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#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
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#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
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#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
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#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
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#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
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(u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
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#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
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(u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
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#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
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(u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
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#define BUF0_LEN 40
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#define BUF1_LEN 1
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#endif
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u64 Buffer0_ptr;
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#ifdef CONFIG_2BUFF_MODE
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u64 Buffer1_ptr;
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u64 Buffer2_ptr;
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#endif
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} RxD_t;
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} RxD3_t;
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/* Structure that represents the Rx descriptor block which contains
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* 128 Rx descriptors.
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*/
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#ifndef CONFIG_2BUFF_MODE
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typedef struct _RxD_block {
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#define MAX_RXDS_PER_BLOCK 127
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RxD_t rxd[MAX_RXDS_PER_BLOCK];
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#define MAX_RXDS_PER_BLOCK_1 127
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RxD1_t rxd[MAX_RXDS_PER_BLOCK_1];
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u64 reserved_0;
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#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
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@ -492,18 +497,13 @@ typedef struct _RxD_block {
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* the upper 32 bits should
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* be 0 */
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} RxD_block_t;
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#else
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typedef struct _RxD_block {
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#define MAX_RXDS_PER_BLOCK 85
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RxD_t rxd[MAX_RXDS_PER_BLOCK];
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#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
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u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
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* in this blk */
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u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
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} RxD_block_t;
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#define SIZE_OF_BLOCK 4096
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#define RXD_MODE_1 0
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#define RXD_MODE_3A 1
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#define RXD_MODE_3B 2
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/* Structure to hold virtual addresses of Buf0 and Buf1 in
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* 2buf mode. */
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typedef struct bufAdd {
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@ -512,7 +512,6 @@ typedef struct bufAdd {
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void *ba_0;
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void *ba_1;
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} buffAdd_t;
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#endif
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/* Structure which stores all the MAC control parameters */
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@ -539,10 +538,17 @@ typedef struct {
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typedef tx_curr_get_info_t tx_curr_put_info_t;
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typedef struct rxd_info {
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void *virt_addr;
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dma_addr_t dma_addr;
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}rxd_info_t;
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/* Structure that holds the Phy and virt addresses of the Blocks */
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typedef struct rx_block_info {
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RxD_t *block_virt_addr;
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void *block_virt_addr;
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dma_addr_t block_dma_addr;
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rxd_info_t *rxds;
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} rx_block_info_t;
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/* pre declaration of the nic structure */
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@ -578,10 +584,8 @@ typedef struct ring_info {
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int put_pos;
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#endif
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#ifdef CONFIG_2BUFF_MODE
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/* Buffer Address store. */
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buffAdd_t **ba;
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#endif
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nic_t *nic;
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} ring_info_t;
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@ -647,8 +651,6 @@ typedef struct {
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/* Default Tunable parameters of the NIC. */
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#define DEFAULT_FIFO_LEN 4096
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#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
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#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
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#define SMALL_BLK_CNT 30
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#define LARGE_BLK_CNT 100
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@ -678,6 +680,7 @@ struct msix_info_st {
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/* Structure representing one instance of the NIC */
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struct s2io_nic {
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int rxd_mode;
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#ifdef CONFIG_S2IO_NAPI
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/*
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* Count of packets to be processed in a given iteration, it will be indicated
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