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drm/i915/bdw: WaDisableFenceDestinationToSLM 

This WA affect BDW GT3 pre-production steppings.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: Don't mention steppings ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Rodrigo Vivi 2014-09-19 20:16:27 -04:00 committed by Daniel Vetter
parent a0fcbd9535
commit da09654d77
2 changed files with 6 additions and 1 deletions
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1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -4836,6 +4836,7 @@ enum punit_power_well {
/* GEN8 chicken */
#define HDC_CHICKEN0 0x7300
#define HDC_FORCE_NON_COHERENT (1<<4)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
/* WaCatErrorRejectionIssue */
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030

6
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -740,8 +740,12 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
* workaround for for a possible hang in the unlikely event a TLB
* invalidation occurs during a PSD flush.
*/
/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
intel_ring_emit_wa(ring, HDC_CHICKEN0,
_MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
_MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT |
(IS_BDW_GT3(dev) ?
HDC_FENCE_DEST_SLM_DISABLE : 0)
));
/* Wa4x4STCOptimizationDisable:bdw */
intel_ring_emit_wa(ring, CACHE_MODE_1,