The imx device tree changes for 3.10:
* The huge diff stat is introduced by the pinctrl changes. With DTC macro support ready, we're moving those huge mount of data about pins out of pinctrl driver. * Device tree source updates for GPI, LDB, SRC, cpufreq-cpu0. * Initial imx6dl device tree support * Board level DTS changes for some imx27 and imx51 platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJRZC32AAoJEFBXWFqHsHzOozsH/RSOnAZfNanMffVYNE5m6Nia I4UjrOQktryk726/dSFuoYb9eDaLzceeJgGLzKJic4KQCnhD7aW2gWcJSN8ThLUH IWzv1TtVgy6py8DBvZNTGZdIB+bXDPr2xs6us8ev4gTMylN8gkaM+kP36UkFXsS3 GSZmd5sMgCfIj01z3ogCkcWcXQ1fE8DY3Z5UksUtfsMtMiB+vItWXi/wxYzwoaGb xYWDfR1B8dr5fgbP/LXP5NDOU5+sl0RlOCUVLRhB+W4IbDqqc08z6HUBTJhBXLEV y1eGeKaxdIux6sdsupGLIxGHp8OIKz3Fm1KpC/HBTf2s/5EiZjc/G0aJiJ04qT0= =0lru -----END PGP SIGNATURE----- Merge tag 'imx-dt-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt From Shawn Guo: The imx device tree changes for 3.10: * The huge diff stat is introduced by the pinctrl changes. With DTC macro support ready, we're moving those huge mount of data about pins out of pinctrl driver. * Device tree source updates for GPI, LDB, SRC, cpufreq-cpu0. * Initial imx6dl device tree support * Board level DTS changes for some imx27 and imx51 platforms. * tag 'imx-dt-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (605 commits) ARM: dts: imx6dl-wandboard: Add USB Host support ARM: dts: imx51 cpu node ARM: dts: Add missing imx27-phytec-phycore dtb target ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module ARM: i.MX51: Add PATA support ARM: dts: Add initial support for Wandboard Dual-Lite ARM: dts: imx: add initial imx6dl-sabreauto support ARM: dts: imx: add initial imx6dl-sabresd support ARM: dts: imx: make sabreauto and sabresd common pinctrl: add pinctrl driver for imx6sl pinctrl: add pinctrl driver for imx6dl ARM: dts: imx53: fix SD2_DATA1 pad AUDMUX_AUD4 configuration ARM: dts: MicroSys sbc6x support (i.MX6) ARM i.MX5: Add System Reset Controller (SRC) support for i.MX51 and i.MX53 ARM i.MX5: Add system reset controller (SRC) to i.MX51 and i.MX53 device tree ARM i.MX6q: Link system reset controller (SRC) to IPU in DT ARM i.MX6q: Add LDB device to device tree ARM: imx5 DT init cpufreq-cpu0 device ARM: imx27 DT init cpufreq-cpu0 device ARM i.MX53: Add LDB device to device tree ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
da0851fe3a
8
CREDITS
8
CREDITS
|
|
@ -1510,6 +1510,14 @@ D: Natsemi ethernet
|
|||
D: Cobalt Networks (x86) support
|
||||
D: This-and-That
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||||
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||||
N: Mark M. Hoffman
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||||
E: mhoffman@lightlink.com
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||||
D: asb100, lm93 and smsc47b397 hardware monitoring drivers
|
||||
D: hwmon subsystem core
|
||||
D: hwmon subsystem maintainer
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||||
D: i2c-sis96x and i2c-stub SMBus drivers
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||||
S: USA
|
||||
|
||||
N: Dirk Hohndel
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||||
E: hohndel@suse.de
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D: The XFree86[tm] Project
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||||
|
|
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|||
|
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@ -0,0 +1,117 @@
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* Clock bindings for Freescale i.MX27
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||||
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Required properties:
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- compatible: Should be "fsl,imx27-ccm"
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- reg: Address and length of the register set
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- interrupts: Should contain CCM interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX27
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clocks and IDs.
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Clock ID
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-----------------------
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dummy 0
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ckih 1
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ckil 2
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mpll 3
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spll 4
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mpll_main2 5
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ahb 6
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ipg 7
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nfc_div 8
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per1_div 9
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per2_div 10
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per3_div 11
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per4_div 12
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vpu_sel 13
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vpu_div 14
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usb_div 15
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cpu_sel 16
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clko_sel 17
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cpu_div 18
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clko_div 19
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ssi1_sel 20
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ssi2_sel 21
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ssi1_div 22
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ssi2_div 23
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clko_en 24
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ssi2_ipg_gate 25
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ssi1_ipg_gate 26
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slcdc_ipg_gate 27
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sdhc3_ipg_gate 28
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sdhc2_ipg_gate 29
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sdhc1_ipg_gate 30
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scc_ipg_gate 31
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sahara_ipg_gate 32
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rtc_ipg_gate 33
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pwm_ipg_gate 34
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owire_ipg_gate 35
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lcdc_ipg_gate 36
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kpp_ipg_gate 37
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iim_ipg_gate 38
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i2c2_ipg_gate 39
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i2c1_ipg_gate 40
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gpt6_ipg_gate 41
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gpt5_ipg_gate 42
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gpt4_ipg_gate 43
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gpt3_ipg_gate 44
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gpt2_ipg_gate 45
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gpt1_ipg_gate 46
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gpio_ipg_gate 47
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fec_ipg_gate 48
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emma_ipg_gate 49
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dma_ipg_gate 50
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cspi3_ipg_gate 51
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cspi2_ipg_gate 52
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cspi1_ipg_gate 53
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nfc_baud_gate 54
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ssi2_baud_gate 55
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ssi1_baud_gate 56
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vpu_baud_gate 57
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per4_gate 58
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per3_gate 59
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per2_gate 60
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per1_gate 61
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usb_ahb_gate 62
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slcdc_ahb_gate 63
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sahara_ahb_gate 64
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lcdc_ahb_gate 65
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vpu_ahb_gate 66
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fec_ahb_gate 67
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emma_ahb_gate 68
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emi_ahb_gate 69
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dma_ahb_gate 70
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csi_ahb_gate 71
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brom_ahb_gate 72
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ata_ahb_gate 73
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wdog_ipg_gate 74
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usb_ipg_gate 75
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uart6_ipg_gate 76
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uart5_ipg_gate 77
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uart4_ipg_gate 78
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uart3_ipg_gate 79
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uart2_ipg_gate 80
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uart1_ipg_gate 81
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ckih_div1p5 82
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fpm 83
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mpll_osc_sel 84
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mpll_sel 85
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Examples:
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clks: ccm@10027000{
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compatible = "fsl,imx27-ccm";
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reg = <0x10027000 0x1000>;
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#clock-cells = <1>;
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks 81>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -24,9 +24,9 @@ Required properties for iomux controller:
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Required properties for pin configuration node:
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- fsl,pins: two integers array, represents a group of pins mux and config
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setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
|
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pin working on a specific function, CONFIG is the pad setting value like
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pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
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pins and functions of each SoC.
|
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pin working on a specific function, which consists of a tuple of
|
||||
<mux_reg conf_reg input_reg mux_val input_val>. CONFIG is the pad setting
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value like pull-up on this pin.
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Bits used for CONFIG:
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NO_PAD_CTL(1 << 31): indicate this pin does not need config.
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|
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@ -29,956 +29,5 @@ PAD_CTL_DSE_MAX (2 << 1)
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PAD_CTL_SRE_FAST (1 << 0)
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PAD_CTL_SRE_SLOW (0 << 0)
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See below for available PIN_FUNC_ID for imx35:
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0 MX35_PAD_CAPTURE__GPT_CAPIN1
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1 MX35_PAD_CAPTURE__GPT_CMPOUT2
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2 MX35_PAD_CAPTURE__CSPI2_SS1
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3 MX35_PAD_CAPTURE__EPIT1_EPITO
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4 MX35_PAD_CAPTURE__CCM_CLK32K
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5 MX35_PAD_CAPTURE__GPIO1_4
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6 MX35_PAD_COMPARE__GPT_CMPOUT1
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7 MX35_PAD_COMPARE__GPT_CAPIN2
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8 MX35_PAD_COMPARE__GPT_CMPOUT3
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9 MX35_PAD_COMPARE__EPIT2_EPITO
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10 MX35_PAD_COMPARE__GPIO1_5
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11 MX35_PAD_COMPARE__SDMA_EXTDMA_2
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12 MX35_PAD_WDOG_RST__WDOG_WDOG_B
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13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
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14 MX35_PAD_WDOG_RST__GPIO1_6
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15 MX35_PAD_GPIO1_0__GPIO1_0
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16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
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17 MX35_PAD_GPIO1_0__OWIRE_LINE
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18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
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19 MX35_PAD_GPIO1_1__GPIO1_1
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20 MX35_PAD_GPIO1_1__PWM_PWMO
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21 MX35_PAD_GPIO1_1__CSPI1_SS2
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22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
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23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
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24 MX35_PAD_GPIO2_0__GPIO2_0
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25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
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26 MX35_PAD_GPIO3_0__GPIO3_0
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27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
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28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
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29 MX35_PAD_POR_B__CCM_POR_B
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30 MX35_PAD_CLKO__CCM_CLKO
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31 MX35_PAD_CLKO__GPIO1_8
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32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
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33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
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34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
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35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
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36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
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37 MX35_PAD_VSTBY__CCM_VSTBY
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38 MX35_PAD_VSTBY__GPIO1_7
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39 MX35_PAD_A0__EMI_EIM_DA_L_0
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40 MX35_PAD_A1__EMI_EIM_DA_L_1
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41 MX35_PAD_A2__EMI_EIM_DA_L_2
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42 MX35_PAD_A3__EMI_EIM_DA_L_3
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43 MX35_PAD_A4__EMI_EIM_DA_L_4
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44 MX35_PAD_A5__EMI_EIM_DA_L_5
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45 MX35_PAD_A6__EMI_EIM_DA_L_6
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46 MX35_PAD_A7__EMI_EIM_DA_L_7
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47 MX35_PAD_A8__EMI_EIM_DA_H_8
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48 MX35_PAD_A9__EMI_EIM_DA_H_9
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49 MX35_PAD_A10__EMI_EIM_DA_H_10
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50 MX35_PAD_MA10__EMI_MA10
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51 MX35_PAD_A11__EMI_EIM_DA_H_11
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52 MX35_PAD_A12__EMI_EIM_DA_H_12
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53 MX35_PAD_A13__EMI_EIM_DA_H_13
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54 MX35_PAD_A14__EMI_EIM_DA_H2_14
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55 MX35_PAD_A15__EMI_EIM_DA_H2_15
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56 MX35_PAD_A16__EMI_EIM_A_16
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57 MX35_PAD_A17__EMI_EIM_A_17
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58 MX35_PAD_A18__EMI_EIM_A_18
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59 MX35_PAD_A19__EMI_EIM_A_19
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60 MX35_PAD_A20__EMI_EIM_A_20
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61 MX35_PAD_A21__EMI_EIM_A_21
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62 MX35_PAD_A22__EMI_EIM_A_22
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63 MX35_PAD_A23__EMI_EIM_A_23
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64 MX35_PAD_A24__EMI_EIM_A_24
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65 MX35_PAD_A25__EMI_EIM_A_25
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66 MX35_PAD_SDBA1__EMI_EIM_SDBA1
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67 MX35_PAD_SDBA0__EMI_EIM_SDBA0
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68 MX35_PAD_SD0__EMI_DRAM_D_0
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69 MX35_PAD_SD1__EMI_DRAM_D_1
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70 MX35_PAD_SD2__EMI_DRAM_D_2
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71 MX35_PAD_SD3__EMI_DRAM_D_3
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72 MX35_PAD_SD4__EMI_DRAM_D_4
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73 MX35_PAD_SD5__EMI_DRAM_D_5
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74 MX35_PAD_SD6__EMI_DRAM_D_6
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75 MX35_PAD_SD7__EMI_DRAM_D_7
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76 MX35_PAD_SD8__EMI_DRAM_D_8
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77 MX35_PAD_SD9__EMI_DRAM_D_9
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78 MX35_PAD_SD10__EMI_DRAM_D_10
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||||
79 MX35_PAD_SD11__EMI_DRAM_D_11
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||||
80 MX35_PAD_SD12__EMI_DRAM_D_12
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||||
81 MX35_PAD_SD13__EMI_DRAM_D_13
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82 MX35_PAD_SD14__EMI_DRAM_D_14
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83 MX35_PAD_SD15__EMI_DRAM_D_15
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||||
84 MX35_PAD_SD16__EMI_DRAM_D_16
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||||
85 MX35_PAD_SD17__EMI_DRAM_D_17
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||||
86 MX35_PAD_SD18__EMI_DRAM_D_18
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||||
87 MX35_PAD_SD19__EMI_DRAM_D_19
|
||||
88 MX35_PAD_SD20__EMI_DRAM_D_20
|
||||
89 MX35_PAD_SD21__EMI_DRAM_D_21
|
||||
90 MX35_PAD_SD22__EMI_DRAM_D_22
|
||||
91 MX35_PAD_SD23__EMI_DRAM_D_23
|
||||
92 MX35_PAD_SD24__EMI_DRAM_D_24
|
||||
93 MX35_PAD_SD25__EMI_DRAM_D_25
|
||||
94 MX35_PAD_SD26__EMI_DRAM_D_26
|
||||
95 MX35_PAD_SD27__EMI_DRAM_D_27
|
||||
96 MX35_PAD_SD28__EMI_DRAM_D_28
|
||||
97 MX35_PAD_SD29__EMI_DRAM_D_29
|
||||
98 MX35_PAD_SD30__EMI_DRAM_D_30
|
||||
99 MX35_PAD_SD31__EMI_DRAM_D_31
|
||||
100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
|
||||
101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
|
||||
102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
|
||||
103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
|
||||
104 MX35_PAD_EB0__EMI_EIM_EB0_B
|
||||
105 MX35_PAD_EB1__EMI_EIM_EB1_B
|
||||
106 MX35_PAD_OE__EMI_EIM_OE
|
||||
107 MX35_PAD_CS0__EMI_EIM_CS0
|
||||
108 MX35_PAD_CS1__EMI_EIM_CS1
|
||||
109 MX35_PAD_CS1__EMI_NANDF_CE3
|
||||
110 MX35_PAD_CS2__EMI_EIM_CS2
|
||||
111 MX35_PAD_CS3__EMI_EIM_CS3
|
||||
112 MX35_PAD_CS4__EMI_EIM_CS4
|
||||
113 MX35_PAD_CS4__EMI_DTACK_B
|
||||
114 MX35_PAD_CS4__EMI_NANDF_CE1
|
||||
115 MX35_PAD_CS4__GPIO1_20
|
||||
116 MX35_PAD_CS5__EMI_EIM_CS5
|
||||
117 MX35_PAD_CS5__CSPI2_SS2
|
||||
118 MX35_PAD_CS5__CSPI1_SS2
|
||||
119 MX35_PAD_CS5__EMI_NANDF_CE2
|
||||
120 MX35_PAD_CS5__GPIO1_21
|
||||
121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
|
||||
122 MX35_PAD_NF_CE0__GPIO1_22
|
||||
123 MX35_PAD_ECB__EMI_EIM_ECB
|
||||
124 MX35_PAD_LBA__EMI_EIM_LBA
|
||||
125 MX35_PAD_BCLK__EMI_EIM_BCLK
|
||||
126 MX35_PAD_RW__EMI_EIM_RW
|
||||
127 MX35_PAD_RAS__EMI_DRAM_RAS
|
||||
128 MX35_PAD_CAS__EMI_DRAM_CAS
|
||||
129 MX35_PAD_SDWE__EMI_DRAM_SDWE
|
||||
130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
|
||||
131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
|
||||
132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
|
||||
133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
|
||||
134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
|
||||
135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
|
||||
136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
|
||||
137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
|
||||
138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
|
||||
139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
|
||||
140 MX35_PAD_NFWE_B__GPIO2_18
|
||||
141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
|
||||
142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
|
||||
143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
|
||||
144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
|
||||
145 MX35_PAD_NFRE_B__GPIO2_19
|
||||
146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
|
||||
147 MX35_PAD_NFALE__EMI_NANDF_ALE
|
||||
148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
|
||||
149 MX35_PAD_NFALE__IPU_DISPB_CS0
|
||||
150 MX35_PAD_NFALE__GPIO2_20
|
||||
151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
|
||||
152 MX35_PAD_NFCLE__EMI_NANDF_CLE
|
||||
153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
|
||||
154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
|
||||
155 MX35_PAD_NFCLE__GPIO2_21
|
||||
156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
|
||||
157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
|
||||
158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
|
||||
159 MX35_PAD_NFWP_B__IPU_DISPB_WR
|
||||
160 MX35_PAD_NFWP_B__GPIO2_22
|
||||
161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
|
||||
162 MX35_PAD_NFRB__EMI_NANDF_RB
|
||||
163 MX35_PAD_NFRB__IPU_DISPB_RD
|
||||
164 MX35_PAD_NFRB__GPIO2_23
|
||||
165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
|
||||
166 MX35_PAD_D15__EMI_EIM_D_15
|
||||
167 MX35_PAD_D14__EMI_EIM_D_14
|
||||
168 MX35_PAD_D13__EMI_EIM_D_13
|
||||
169 MX35_PAD_D12__EMI_EIM_D_12
|
||||
170 MX35_PAD_D11__EMI_EIM_D_11
|
||||
171 MX35_PAD_D10__EMI_EIM_D_10
|
||||
172 MX35_PAD_D9__EMI_EIM_D_9
|
||||
173 MX35_PAD_D8__EMI_EIM_D_8
|
||||
174 MX35_PAD_D7__EMI_EIM_D_7
|
||||
175 MX35_PAD_D6__EMI_EIM_D_6
|
||||
176 MX35_PAD_D5__EMI_EIM_D_5
|
||||
177 MX35_PAD_D4__EMI_EIM_D_4
|
||||
178 MX35_PAD_D3__EMI_EIM_D_3
|
||||
179 MX35_PAD_D2__EMI_EIM_D_2
|
||||
180 MX35_PAD_D1__EMI_EIM_D_1
|
||||
181 MX35_PAD_D0__EMI_EIM_D_0
|
||||
182 MX35_PAD_CSI_D8__IPU_CSI_D_8
|
||||
183 MX35_PAD_CSI_D8__KPP_COL_0
|
||||
184 MX35_PAD_CSI_D8__GPIO1_20
|
||||
185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
|
||||
186 MX35_PAD_CSI_D9__IPU_CSI_D_9
|
||||
187 MX35_PAD_CSI_D9__KPP_COL_1
|
||||
188 MX35_PAD_CSI_D9__GPIO1_21
|
||||
189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
|
||||
190 MX35_PAD_CSI_D10__IPU_CSI_D_10
|
||||
191 MX35_PAD_CSI_D10__KPP_COL_2
|
||||
192 MX35_PAD_CSI_D10__GPIO1_22
|
||||
193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
|
||||
194 MX35_PAD_CSI_D11__IPU_CSI_D_11
|
||||
195 MX35_PAD_CSI_D11__KPP_COL_3
|
||||
196 MX35_PAD_CSI_D11__GPIO1_23
|
||||
197 MX35_PAD_CSI_D12__IPU_CSI_D_12
|
||||
198 MX35_PAD_CSI_D12__KPP_ROW_0
|
||||
199 MX35_PAD_CSI_D12__GPIO1_24
|
||||
200 MX35_PAD_CSI_D13__IPU_CSI_D_13
|
||||
201 MX35_PAD_CSI_D13__KPP_ROW_1
|
||||
202 MX35_PAD_CSI_D13__GPIO1_25
|
||||
203 MX35_PAD_CSI_D14__IPU_CSI_D_14
|
||||
204 MX35_PAD_CSI_D14__KPP_ROW_2
|
||||
205 MX35_PAD_CSI_D14__GPIO1_26
|
||||
206 MX35_PAD_CSI_D15__IPU_CSI_D_15
|
||||
207 MX35_PAD_CSI_D15__KPP_ROW_3
|
||||
208 MX35_PAD_CSI_D15__GPIO1_27
|
||||
209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
|
||||
210 MX35_PAD_CSI_MCLK__GPIO1_28
|
||||
211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
|
||||
212 MX35_PAD_CSI_VSYNC__GPIO1_29
|
||||
213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
|
||||
214 MX35_PAD_CSI_HSYNC__GPIO1_30
|
||||
215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
|
||||
216 MX35_PAD_CSI_PIXCLK__GPIO1_31
|
||||
217 MX35_PAD_I2C1_CLK__I2C1_SCL
|
||||
218 MX35_PAD_I2C1_CLK__GPIO2_24
|
||||
219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
|
||||
220 MX35_PAD_I2C1_DAT__I2C1_SDA
|
||||
221 MX35_PAD_I2C1_DAT__GPIO2_25
|
||||
222 MX35_PAD_I2C2_CLK__I2C2_SCL
|
||||
223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
|
||||
224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
|
||||
225 MX35_PAD_I2C2_CLK__GPIO2_26
|
||||
226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
|
||||
227 MX35_PAD_I2C2_DAT__I2C2_SDA
|
||||
228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
|
||||
229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
|
||||
230 MX35_PAD_I2C2_DAT__GPIO2_27
|
||||
231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
|
||||
232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
|
||||
233 MX35_PAD_STXD4__GPIO2_28
|
||||
234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
|
||||
235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
|
||||
236 MX35_PAD_SRXD4__GPIO2_29
|
||||
237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
|
||||
238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
|
||||
239 MX35_PAD_SCK4__GPIO2_30
|
||||
240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
|
||||
241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
|
||||
242 MX35_PAD_STXFS4__GPIO2_31
|
||||
243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
|
||||
244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
|
||||
245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
|
||||
246 MX35_PAD_STXD5__CSPI2_MOSI
|
||||
247 MX35_PAD_STXD5__GPIO1_0
|
||||
248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
|
||||
249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
|
||||
250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
|
||||
251 MX35_PAD_SRXD5__CSPI2_MISO
|
||||
252 MX35_PAD_SRXD5__GPIO1_1
|
||||
253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
|
||||
254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
|
||||
255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
|
||||
256 MX35_PAD_SCK5__CSPI2_SCLK
|
||||
257 MX35_PAD_SCK5__GPIO1_2
|
||||
258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
|
||||
259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
|
||||
260 MX35_PAD_STXFS5__CSPI2_RDY
|
||||
261 MX35_PAD_STXFS5__GPIO1_3
|
||||
262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
|
||||
263 MX35_PAD_SCKR__ESAI_SCKR
|
||||
264 MX35_PAD_SCKR__GPIO1_4
|
||||
265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
|
||||
266 MX35_PAD_FSR__ESAI_FSR
|
||||
267 MX35_PAD_FSR__GPIO1_5
|
||||
268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
|
||||
269 MX35_PAD_HCKR__ESAI_HCKR
|
||||
270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
|
||||
271 MX35_PAD_HCKR__CSPI2_SS0
|
||||
272 MX35_PAD_HCKR__IPU_FLASH_STROBE
|
||||
273 MX35_PAD_HCKR__GPIO1_6
|
||||
274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
|
||||
275 MX35_PAD_SCKT__ESAI_SCKT
|
||||
276 MX35_PAD_SCKT__GPIO1_7
|
||||
277 MX35_PAD_SCKT__IPU_CSI_D_0
|
||||
278 MX35_PAD_SCKT__KPP_ROW_2
|
||||
279 MX35_PAD_FST__ESAI_FST
|
||||
280 MX35_PAD_FST__GPIO1_8
|
||||
281 MX35_PAD_FST__IPU_CSI_D_1
|
||||
282 MX35_PAD_FST__KPP_ROW_3
|
||||
283 MX35_PAD_HCKT__ESAI_HCKT
|
||||
284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
|
||||
285 MX35_PAD_HCKT__GPIO1_9
|
||||
286 MX35_PAD_HCKT__IPU_CSI_D_2
|
||||
287 MX35_PAD_HCKT__KPP_COL_3
|
||||
288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
|
||||
289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
|
||||
290 MX35_PAD_TX5_RX0__CSPI2_SS2
|
||||
291 MX35_PAD_TX5_RX0__CAN2_TXCAN
|
||||
292 MX35_PAD_TX5_RX0__UART2_DTR
|
||||
293 MX35_PAD_TX5_RX0__GPIO1_10
|
||||
294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
|
||||
295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
|
||||
296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
|
||||
297 MX35_PAD_TX4_RX1__CSPI2_SS3
|
||||
298 MX35_PAD_TX4_RX1__CAN2_RXCAN
|
||||
299 MX35_PAD_TX4_RX1__UART2_DSR
|
||||
300 MX35_PAD_TX4_RX1__GPIO1_11
|
||||
301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
|
||||
302 MX35_PAD_TX4_RX1__KPP_ROW_0
|
||||
303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
|
||||
304 MX35_PAD_TX3_RX2__I2C3_SCL
|
||||
305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
|
||||
306 MX35_PAD_TX3_RX2__GPIO1_12
|
||||
307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
|
||||
308 MX35_PAD_TX3_RX2__KPP_ROW_1
|
||||
309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
|
||||
310 MX35_PAD_TX2_RX3__I2C3_SDA
|
||||
311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
|
||||
312 MX35_PAD_TX2_RX3__GPIO1_13
|
||||
313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
|
||||
314 MX35_PAD_TX2_RX3__KPP_COL_0
|
||||
315 MX35_PAD_TX1__ESAI_TX1
|
||||
316 MX35_PAD_TX1__CCM_PMIC_RDY
|
||||
317 MX35_PAD_TX1__CSPI1_SS2
|
||||
318 MX35_PAD_TX1__EMI_NANDF_CE3
|
||||
319 MX35_PAD_TX1__UART2_RI
|
||||
320 MX35_PAD_TX1__GPIO1_14
|
||||
321 MX35_PAD_TX1__IPU_CSI_D_6
|
||||
322 MX35_PAD_TX1__KPP_COL_1
|
||||
323 MX35_PAD_TX0__ESAI_TX0
|
||||
324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
|
||||
325 MX35_PAD_TX0__CSPI1_SS3
|
||||
326 MX35_PAD_TX0__EMI_DTACK_B
|
||||
327 MX35_PAD_TX0__UART2_DCD
|
||||
328 MX35_PAD_TX0__GPIO1_15
|
||||
329 MX35_PAD_TX0__IPU_CSI_D_7
|
||||
330 MX35_PAD_TX0__KPP_COL_2
|
||||
331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
|
||||
332 MX35_PAD_CSPI1_MOSI__GPIO1_16
|
||||
333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
|
||||
334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
|
||||
335 MX35_PAD_CSPI1_MISO__GPIO1_17
|
||||
336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
|
||||
337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
|
||||
338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
|
||||
339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
|
||||
340 MX35_PAD_CSPI1_SS0__GPIO1_18
|
||||
341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
|
||||
342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
|
||||
343 MX35_PAD_CSPI1_SS1__PWM_PWMO
|
||||
344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
|
||||
345 MX35_PAD_CSPI1_SS1__GPIO1_19
|
||||
346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
|
||||
347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
|
||||
348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
|
||||
349 MX35_PAD_CSPI1_SCLK__GPIO3_4
|
||||
350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
|
||||
351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
|
||||
352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
|
||||
353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
|
||||
354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
|
||||
355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
|
||||
356 MX35_PAD_RXD1__UART1_RXD_MUX
|
||||
357 MX35_PAD_RXD1__CSPI2_MOSI
|
||||
358 MX35_PAD_RXD1__KPP_COL_4
|
||||
359 MX35_PAD_RXD1__GPIO3_6
|
||||
360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
|
||||
361 MX35_PAD_TXD1__UART1_TXD_MUX
|
||||
362 MX35_PAD_TXD1__CSPI2_MISO
|
||||
363 MX35_PAD_TXD1__KPP_COL_5
|
||||
364 MX35_PAD_TXD1__GPIO3_7
|
||||
365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
|
||||
366 MX35_PAD_RTS1__UART1_RTS
|
||||
367 MX35_PAD_RTS1__CSPI2_SCLK
|
||||
368 MX35_PAD_RTS1__I2C3_SCL
|
||||
369 MX35_PAD_RTS1__IPU_CSI_D_0
|
||||
370 MX35_PAD_RTS1__KPP_COL_6
|
||||
371 MX35_PAD_RTS1__GPIO3_8
|
||||
372 MX35_PAD_RTS1__EMI_NANDF_CE1
|
||||
373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
|
||||
374 MX35_PAD_CTS1__UART1_CTS
|
||||
375 MX35_PAD_CTS1__CSPI2_RDY
|
||||
376 MX35_PAD_CTS1__I2C3_SDA
|
||||
377 MX35_PAD_CTS1__IPU_CSI_D_1
|
||||
378 MX35_PAD_CTS1__KPP_COL_7
|
||||
379 MX35_PAD_CTS1__GPIO3_9
|
||||
380 MX35_PAD_CTS1__EMI_NANDF_CE2
|
||||
381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
|
||||
382 MX35_PAD_RXD2__UART2_RXD_MUX
|
||||
383 MX35_PAD_RXD2__KPP_ROW_4
|
||||
384 MX35_PAD_RXD2__GPIO3_10
|
||||
385 MX35_PAD_TXD2__UART2_TXD_MUX
|
||||
386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
|
||||
387 MX35_PAD_TXD2__KPP_ROW_5
|
||||
388 MX35_PAD_TXD2__GPIO3_11
|
||||
389 MX35_PAD_RTS2__UART2_RTS
|
||||
390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
|
||||
391 MX35_PAD_RTS2__CAN2_RXCAN
|
||||
392 MX35_PAD_RTS2__IPU_CSI_D_2
|
||||
393 MX35_PAD_RTS2__KPP_ROW_6
|
||||
394 MX35_PAD_RTS2__GPIO3_12
|
||||
395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
|
||||
396 MX35_PAD_RTS2__UART3_RXD_MUX
|
||||
397 MX35_PAD_CTS2__UART2_CTS
|
||||
398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
|
||||
399 MX35_PAD_CTS2__CAN2_TXCAN
|
||||
400 MX35_PAD_CTS2__IPU_CSI_D_3
|
||||
401 MX35_PAD_CTS2__KPP_ROW_7
|
||||
402 MX35_PAD_CTS2__GPIO3_13
|
||||
403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
|
||||
404 MX35_PAD_CTS2__UART3_TXD_MUX
|
||||
405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
|
||||
406 MX35_PAD_TCK__SJC_TCK
|
||||
407 MX35_PAD_TMS__SJC_TMS
|
||||
408 MX35_PAD_TDI__SJC_TDI
|
||||
409 MX35_PAD_TDO__SJC_TDO
|
||||
410 MX35_PAD_TRSTB__SJC_TRSTB
|
||||
411 MX35_PAD_DE_B__SJC_DE_B
|
||||
412 MX35_PAD_SJC_MOD__SJC_MOD
|
||||
413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
|
||||
414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
|
||||
415 MX35_PAD_USBOTG_PWR__GPIO3_14
|
||||
416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
|
||||
417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
|
||||
418 MX35_PAD_USBOTG_OC__GPIO3_15
|
||||
419 MX35_PAD_LD0__IPU_DISPB_DAT_0
|
||||
420 MX35_PAD_LD0__GPIO2_0
|
||||
421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
|
||||
422 MX35_PAD_LD1__IPU_DISPB_DAT_1
|
||||
423 MX35_PAD_LD1__GPIO2_1
|
||||
424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
|
||||
425 MX35_PAD_LD2__IPU_DISPB_DAT_2
|
||||
426 MX35_PAD_LD2__GPIO2_2
|
||||
427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
|
||||
428 MX35_PAD_LD3__IPU_DISPB_DAT_3
|
||||
429 MX35_PAD_LD3__GPIO2_3
|
||||
430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
|
||||
431 MX35_PAD_LD4__IPU_DISPB_DAT_4
|
||||
432 MX35_PAD_LD4__GPIO2_4
|
||||
433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
|
||||
434 MX35_PAD_LD5__IPU_DISPB_DAT_5
|
||||
435 MX35_PAD_LD5__GPIO2_5
|
||||
436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
|
||||
437 MX35_PAD_LD6__IPU_DISPB_DAT_6
|
||||
438 MX35_PAD_LD6__GPIO2_6
|
||||
439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
|
||||
440 MX35_PAD_LD7__IPU_DISPB_DAT_7
|
||||
441 MX35_PAD_LD7__GPIO2_7
|
||||
442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
|
||||
443 MX35_PAD_LD8__IPU_DISPB_DAT_8
|
||||
444 MX35_PAD_LD8__GPIO2_8
|
||||
445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
|
||||
446 MX35_PAD_LD9__IPU_DISPB_DAT_9
|
||||
447 MX35_PAD_LD9__GPIO2_9
|
||||
448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
|
||||
449 MX35_PAD_LD10__IPU_DISPB_DAT_10
|
||||
450 MX35_PAD_LD10__GPIO2_10
|
||||
451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
|
||||
452 MX35_PAD_LD11__IPU_DISPB_DAT_11
|
||||
453 MX35_PAD_LD11__GPIO2_11
|
||||
454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
|
||||
455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
|
||||
456 MX35_PAD_LD12__IPU_DISPB_DAT_12
|
||||
457 MX35_PAD_LD12__GPIO2_12
|
||||
458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
|
||||
459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
|
||||
460 MX35_PAD_LD13__IPU_DISPB_DAT_13
|
||||
461 MX35_PAD_LD13__GPIO2_13
|
||||
462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
|
||||
463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
|
||||
464 MX35_PAD_LD14__IPU_DISPB_DAT_14
|
||||
465 MX35_PAD_LD14__GPIO2_14
|
||||
466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
|
||||
467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
|
||||
468 MX35_PAD_LD15__IPU_DISPB_DAT_15
|
||||
469 MX35_PAD_LD15__GPIO2_15
|
||||
470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
|
||||
471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
|
||||
472 MX35_PAD_LD16__IPU_DISPB_DAT_16
|
||||
473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
|
||||
474 MX35_PAD_LD16__GPIO2_16
|
||||
475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
|
||||
476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
|
||||
477 MX35_PAD_LD17__IPU_DISPB_DAT_17
|
||||
478 MX35_PAD_LD17__IPU_DISPB_CS2
|
||||
479 MX35_PAD_LD17__GPIO2_17
|
||||
480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
|
||||
481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
|
||||
482 MX35_PAD_LD18__IPU_DISPB_DAT_18
|
||||
483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
|
||||
484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
|
||||
485 MX35_PAD_LD18__ESDHC3_CMD
|
||||
486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
|
||||
487 MX35_PAD_LD18__GPIO3_24
|
||||
488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
|
||||
489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
|
||||
490 MX35_PAD_LD19__IPU_DISPB_DAT_19
|
||||
491 MX35_PAD_LD19__IPU_DISPB_BCLK
|
||||
492 MX35_PAD_LD19__IPU_DISPB_CS1
|
||||
493 MX35_PAD_LD19__ESDHC3_CLK
|
||||
494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
|
||||
495 MX35_PAD_LD19__GPIO3_25
|
||||
496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
|
||||
497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
|
||||
498 MX35_PAD_LD20__IPU_DISPB_DAT_20
|
||||
499 MX35_PAD_LD20__IPU_DISPB_CS0
|
||||
500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
|
||||
501 MX35_PAD_LD20__ESDHC3_DAT0
|
||||
502 MX35_PAD_LD20__GPIO3_26
|
||||
503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
|
||||
504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
|
||||
505 MX35_PAD_LD21__IPU_DISPB_DAT_21
|
||||
506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
|
||||
507 MX35_PAD_LD21__IPU_DISPB_SER_RS
|
||||
508 MX35_PAD_LD21__ESDHC3_DAT1
|
||||
509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
|
||||
510 MX35_PAD_LD21__GPIO3_27
|
||||
511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
|
||||
512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
|
||||
513 MX35_PAD_LD22__IPU_DISPB_DAT_22
|
||||
514 MX35_PAD_LD22__IPU_DISPB_WR
|
||||
515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
|
||||
516 MX35_PAD_LD22__ESDHC3_DAT2
|
||||
517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
|
||||
518 MX35_PAD_LD22__GPIO3_28
|
||||
519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
|
||||
520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
|
||||
521 MX35_PAD_LD23__IPU_DISPB_DAT_23
|
||||
522 MX35_PAD_LD23__IPU_DISPB_RD
|
||||
523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
|
||||
524 MX35_PAD_LD23__ESDHC3_DAT3
|
||||
525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
|
||||
526 MX35_PAD_LD23__GPIO3_29
|
||||
527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
|
||||
528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
|
||||
529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
|
||||
530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
|
||||
531 MX35_PAD_D3_HSYNC__GPIO3_30
|
||||
532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
|
||||
533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
|
||||
534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
|
||||
535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
|
||||
536 MX35_PAD_D3_FPSHIFT__GPIO3_31
|
||||
537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
|
||||
538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
|
||||
539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
|
||||
540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
|
||||
541 MX35_PAD_D3_DRDY__GPIO1_0
|
||||
542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
|
||||
543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
|
||||
544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
|
||||
545 MX35_PAD_CONTRAST__GPIO1_1
|
||||
546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
|
||||
547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
|
||||
548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
|
||||
549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
|
||||
550 MX35_PAD_D3_VSYNC__GPIO1_2
|
||||
551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
|
||||
552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
|
||||
553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
|
||||
554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
|
||||
555 MX35_PAD_D3_REV__GPIO1_3
|
||||
556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
|
||||
557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
|
||||
558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
|
||||
559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
|
||||
560 MX35_PAD_D3_CLS__GPIO1_4
|
||||
561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
|
||||
562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
|
||||
563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
|
||||
564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
|
||||
565 MX35_PAD_D3_SPL__GPIO1_5
|
||||
566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
|
||||
567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
|
||||
568 MX35_PAD_SD1_CMD__ESDHC1_CMD
|
||||
569 MX35_PAD_SD1_CMD__MSHC_SCLK
|
||||
570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
|
||||
571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
|
||||
572 MX35_PAD_SD1_CMD__GPIO1_6
|
||||
573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
|
||||
574 MX35_PAD_SD1_CLK__ESDHC1_CLK
|
||||
575 MX35_PAD_SD1_CLK__MSHC_BS
|
||||
576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
|
||||
577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
|
||||
578 MX35_PAD_SD1_CLK__GPIO1_7
|
||||
579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
|
||||
580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
|
||||
581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
|
||||
582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
|
||||
583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
|
||||
584 MX35_PAD_SD1_DATA0__GPIO1_8
|
||||
585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
|
||||
586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
|
||||
587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
|
||||
588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
|
||||
589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
|
||||
590 MX35_PAD_SD1_DATA1__GPIO1_9
|
||||
591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
|
||||
592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
|
||||
593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
|
||||
594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
|
||||
595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
|
||||
596 MX35_PAD_SD1_DATA2__GPIO1_10
|
||||
597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
|
||||
598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
|
||||
599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
|
||||
600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
|
||||
601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
|
||||
602 MX35_PAD_SD1_DATA3__GPIO1_11
|
||||
603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
|
||||
604 MX35_PAD_SD2_CMD__ESDHC2_CMD
|
||||
605 MX35_PAD_SD2_CMD__I2C3_SCL
|
||||
606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
|
||||
607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
|
||||
608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
|
||||
609 MX35_PAD_SD2_CMD__GPIO2_0
|
||||
610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
|
||||
611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
|
||||
612 MX35_PAD_SD2_CLK__ESDHC2_CLK
|
||||
613 MX35_PAD_SD2_CLK__I2C3_SDA
|
||||
614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
|
||||
615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
|
||||
616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
|
||||
617 MX35_PAD_SD2_CLK__GPIO2_1
|
||||
618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
|
||||
619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
|
||||
620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
|
||||
621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
|
||||
622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
|
||||
623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
|
||||
624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
|
||||
625 MX35_PAD_SD2_DATA0__GPIO2_2
|
||||
626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
|
||||
627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
|
||||
628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
|
||||
629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
|
||||
630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
|
||||
631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
|
||||
632 MX35_PAD_SD2_DATA1__GPIO2_3
|
||||
633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
|
||||
634 MX35_PAD_SD2_DATA2__UART3_RTS
|
||||
635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
|
||||
636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
|
||||
637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
|
||||
638 MX35_PAD_SD2_DATA2__GPIO2_4
|
||||
639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
|
||||
640 MX35_PAD_SD2_DATA3__UART3_CTS
|
||||
641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
|
||||
642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
|
||||
643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
|
||||
644 MX35_PAD_SD2_DATA3__GPIO2_5
|
||||
645 MX35_PAD_ATA_CS0__ATA_CS0
|
||||
646 MX35_PAD_ATA_CS0__CSPI1_SS3
|
||||
647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
|
||||
648 MX35_PAD_ATA_CS0__GPIO2_6
|
||||
649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
|
||||
650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
|
||||
651 MX35_PAD_ATA_CS1__ATA_CS1
|
||||
652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
|
||||
653 MX35_PAD_ATA_CS1__CSPI2_SS0
|
||||
654 MX35_PAD_ATA_CS1__GPIO2_7
|
||||
655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
|
||||
656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
|
||||
657 MX35_PAD_ATA_DIOR__ATA_DIOR
|
||||
658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
|
||||
659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
|
||||
660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
|
||||
661 MX35_PAD_ATA_DIOR__CSPI2_SS1
|
||||
662 MX35_PAD_ATA_DIOR__GPIO2_8
|
||||
663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
|
||||
664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
|
||||
665 MX35_PAD_ATA_DIOW__ATA_DIOW
|
||||
666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
|
||||
667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
|
||||
668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
|
||||
669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
|
||||
670 MX35_PAD_ATA_DIOW__GPIO2_9
|
||||
671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
|
||||
672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
|
||||
673 MX35_PAD_ATA_DMACK__ATA_DMACK
|
||||
674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
|
||||
675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
|
||||
676 MX35_PAD_ATA_DMACK__CSPI2_MISO
|
||||
677 MX35_PAD_ATA_DMACK__GPIO2_10
|
||||
678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
|
||||
679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
|
||||
680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
|
||||
681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
|
||||
682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
|
||||
683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
|
||||
684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
|
||||
685 MX35_PAD_ATA_RESET_B__GPIO2_11
|
||||
686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
|
||||
687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
|
||||
688 MX35_PAD_ATA_IORDY__ATA_IORDY
|
||||
689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
|
||||
690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
|
||||
691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
|
||||
692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
|
||||
693 MX35_PAD_ATA_IORDY__GPIO2_12
|
||||
694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
|
||||
695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
|
||||
696 MX35_PAD_ATA_DATA0__ATA_DATA_0
|
||||
697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
|
||||
698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
|
||||
699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
|
||||
700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
|
||||
701 MX35_PAD_ATA_DATA0__GPIO2_13
|
||||
702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
|
||||
703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
|
||||
704 MX35_PAD_ATA_DATA1__ATA_DATA_1
|
||||
705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
|
||||
706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
|
||||
707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
|
||||
708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
|
||||
709 MX35_PAD_ATA_DATA1__GPIO2_14
|
||||
710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
|
||||
711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
|
||||
712 MX35_PAD_ATA_DATA2__ATA_DATA_2
|
||||
713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
|
||||
714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
|
||||
715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
|
||||
716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
|
||||
717 MX35_PAD_ATA_DATA2__GPIO2_15
|
||||
718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
|
||||
719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
|
||||
720 MX35_PAD_ATA_DATA3__ATA_DATA_3
|
||||
721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
|
||||
722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
|
||||
723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
|
||||
724 MX35_PAD_ATA_DATA3__GPIO2_16
|
||||
725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
|
||||
726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
|
||||
727 MX35_PAD_ATA_DATA4__ATA_DATA_4
|
||||
728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
|
||||
729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
|
||||
730 MX35_PAD_ATA_DATA4__GPIO2_17
|
||||
731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
|
||||
732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
|
||||
733 MX35_PAD_ATA_DATA5__ATA_DATA_5
|
||||
734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
|
||||
735 MX35_PAD_ATA_DATA5__GPIO2_18
|
||||
736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
|
||||
737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
|
||||
738 MX35_PAD_ATA_DATA6__ATA_DATA_6
|
||||
739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
|
||||
740 MX35_PAD_ATA_DATA6__UART1_DTR
|
||||
741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
|
||||
742 MX35_PAD_ATA_DATA6__GPIO2_19
|
||||
743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
|
||||
744 MX35_PAD_ATA_DATA7__ATA_DATA_7
|
||||
745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
|
||||
746 MX35_PAD_ATA_DATA7__UART1_DSR
|
||||
747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
|
||||
748 MX35_PAD_ATA_DATA7__GPIO2_20
|
||||
749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
|
||||
750 MX35_PAD_ATA_DATA8__ATA_DATA_8
|
||||
751 MX35_PAD_ATA_DATA8__UART3_RTS
|
||||
752 MX35_PAD_ATA_DATA8__UART1_RI
|
||||
753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
|
||||
754 MX35_PAD_ATA_DATA8__GPIO2_21
|
||||
755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
|
||||
756 MX35_PAD_ATA_DATA9__ATA_DATA_9
|
||||
757 MX35_PAD_ATA_DATA9__UART3_CTS
|
||||
758 MX35_PAD_ATA_DATA9__UART1_DCD
|
||||
759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
|
||||
760 MX35_PAD_ATA_DATA9__GPIO2_22
|
||||
761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
|
||||
762 MX35_PAD_ATA_DATA10__ATA_DATA_10
|
||||
763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
|
||||
764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
|
||||
765 MX35_PAD_ATA_DATA10__GPIO2_23
|
||||
766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
|
||||
767 MX35_PAD_ATA_DATA11__ATA_DATA_11
|
||||
768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
|
||||
769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
|
||||
770 MX35_PAD_ATA_DATA11__GPIO2_24
|
||||
771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
|
||||
772 MX35_PAD_ATA_DATA12__ATA_DATA_12
|
||||
773 MX35_PAD_ATA_DATA12__I2C3_SCL
|
||||
774 MX35_PAD_ATA_DATA12__GPIO2_25
|
||||
775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
|
||||
776 MX35_PAD_ATA_DATA13__ATA_DATA_13
|
||||
777 MX35_PAD_ATA_DATA13__I2C3_SDA
|
||||
778 MX35_PAD_ATA_DATA13__GPIO2_26
|
||||
779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
|
||||
780 MX35_PAD_ATA_DATA14__ATA_DATA_14
|
||||
781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
|
||||
782 MX35_PAD_ATA_DATA14__KPP_ROW_0
|
||||
783 MX35_PAD_ATA_DATA14__GPIO2_27
|
||||
784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
|
||||
785 MX35_PAD_ATA_DATA15__ATA_DATA_15
|
||||
786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
|
||||
787 MX35_PAD_ATA_DATA15__KPP_ROW_1
|
||||
788 MX35_PAD_ATA_DATA15__GPIO2_28
|
||||
789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
|
||||
790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
|
||||
791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
|
||||
792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
|
||||
793 MX35_PAD_ATA_INTRQ__GPIO2_29
|
||||
794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
|
||||
795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
|
||||
796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
|
||||
797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
|
||||
798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
|
||||
799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
|
||||
800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
|
||||
801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
|
||||
802 MX35_PAD_ATA_DMARQ__KPP_COL_0
|
||||
803 MX35_PAD_ATA_DMARQ__GPIO2_31
|
||||
804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
|
||||
805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
|
||||
806 MX35_PAD_ATA_DA0__ATA_DA_0
|
||||
807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
|
||||
808 MX35_PAD_ATA_DA0__KPP_COL_1
|
||||
809 MX35_PAD_ATA_DA0__GPIO3_0
|
||||
810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
|
||||
811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
|
||||
812 MX35_PAD_ATA_DA1__ATA_DA_1
|
||||
813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
|
||||
814 MX35_PAD_ATA_DA1__KPP_COL_2
|
||||
815 MX35_PAD_ATA_DA1__GPIO3_1
|
||||
816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
|
||||
817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
|
||||
818 MX35_PAD_ATA_DA2__ATA_DA_2
|
||||
819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
|
||||
820 MX35_PAD_ATA_DA2__KPP_COL_3
|
||||
821 MX35_PAD_ATA_DA2__GPIO3_2
|
||||
822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
|
||||
823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
|
||||
824 MX35_PAD_MLB_CLK__MLB_MLBCLK
|
||||
825 MX35_PAD_MLB_CLK__GPIO3_3
|
||||
826 MX35_PAD_MLB_DAT__MLB_MLBDAT
|
||||
827 MX35_PAD_MLB_DAT__GPIO3_4
|
||||
828 MX35_PAD_MLB_SIG__MLB_MLBSIG
|
||||
829 MX35_PAD_MLB_SIG__GPIO3_5
|
||||
830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
|
||||
831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
|
||||
832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
|
||||
833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
|
||||
834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
|
||||
835 MX35_PAD_FEC_TX_CLK__GPIO3_6
|
||||
836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
|
||||
837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
|
||||
838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
|
||||
839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
|
||||
840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
|
||||
841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
|
||||
842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
|
||||
843 MX35_PAD_FEC_RX_CLK__GPIO3_7
|
||||
844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
|
||||
845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
|
||||
846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
|
||||
847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
|
||||
848 MX35_PAD_FEC_RX_DV__UART3_RTS
|
||||
849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
|
||||
850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
|
||||
851 MX35_PAD_FEC_RX_DV__GPIO3_8
|
||||
852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
|
||||
853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
|
||||
854 MX35_PAD_FEC_COL__FEC_COL
|
||||
855 MX35_PAD_FEC_COL__ESDHC1_DAT7
|
||||
856 MX35_PAD_FEC_COL__UART3_CTS
|
||||
857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
|
||||
858 MX35_PAD_FEC_COL__CSPI2_RDY
|
||||
859 MX35_PAD_FEC_COL__GPIO3_9
|
||||
860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
|
||||
861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
|
||||
862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
|
||||
863 MX35_PAD_FEC_RDATA0__PWM_PWMO
|
||||
864 MX35_PAD_FEC_RDATA0__UART3_DTR
|
||||
865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
|
||||
866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
|
||||
867 MX35_PAD_FEC_RDATA0__GPIO3_10
|
||||
868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
|
||||
869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
|
||||
870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
|
||||
871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
|
||||
872 MX35_PAD_FEC_TDATA0__UART3_DSR
|
||||
873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
|
||||
874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
|
||||
875 MX35_PAD_FEC_TDATA0__GPIO3_11
|
||||
876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
|
||||
877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
|
||||
878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
|
||||
879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
|
||||
880 MX35_PAD_FEC_TX_EN__UART3_RI
|
||||
881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
|
||||
882 MX35_PAD_FEC_TX_EN__GPIO3_12
|
||||
883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
|
||||
884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
|
||||
885 MX35_PAD_FEC_MDC__FEC_MDC
|
||||
886 MX35_PAD_FEC_MDC__CAN2_TXCAN
|
||||
887 MX35_PAD_FEC_MDC__UART3_DCD
|
||||
888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
|
||||
889 MX35_PAD_FEC_MDC__GPIO3_13
|
||||
890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
|
||||
891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
|
||||
892 MX35_PAD_FEC_MDIO__FEC_MDIO
|
||||
893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
|
||||
894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
|
||||
895 MX35_PAD_FEC_MDIO__GPIO3_14
|
||||
896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
|
||||
897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
|
||||
898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
|
||||
899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
|
||||
900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
|
||||
901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
|
||||
902 MX35_PAD_FEC_TX_ERR__GPIO3_15
|
||||
903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
|
||||
904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
|
||||
905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
|
||||
906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
|
||||
907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
|
||||
908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
|
||||
909 MX35_PAD_FEC_RX_ERR__GPIO3_16
|
||||
910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
|
||||
911 MX35_PAD_FEC_CRS__FEC_CRS
|
||||
912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
|
||||
913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
|
||||
914 MX35_PAD_FEC_CRS__KPP_COL_5
|
||||
915 MX35_PAD_FEC_CRS__GPIO3_17
|
||||
916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
|
||||
917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
|
||||
918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
|
||||
919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
|
||||
920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
|
||||
921 MX35_PAD_FEC_RDATA1__KPP_COL_6
|
||||
922 MX35_PAD_FEC_RDATA1__GPIO3_18
|
||||
923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
|
||||
924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
|
||||
925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
|
||||
926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
|
||||
927 MX35_PAD_FEC_TDATA1__KPP_COL_7
|
||||
928 MX35_PAD_FEC_TDATA1__GPIO3_19
|
||||
929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
|
||||
930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
|
||||
931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
|
||||
932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
|
||||
933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
|
||||
934 MX35_PAD_FEC_RDATA2__GPIO3_20
|
||||
935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
|
||||
936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
|
||||
937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
|
||||
938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
|
||||
939 MX35_PAD_FEC_TDATA2__GPIO3_21
|
||||
940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
|
||||
941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
|
||||
942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
|
||||
943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
|
||||
944 MX35_PAD_FEC_RDATA3__GPIO3_22
|
||||
945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
|
||||
946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
|
||||
947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
|
||||
948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
|
||||
949 MX35_PAD_FEC_TDATA3__GPIO3_23
|
||||
950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
|
||||
951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
|
||||
Refer to imx35-pinfunc.h in device tree source folder for all available
|
||||
imx35 PIN_FUNC_ID.
|
||||
|
|
|
|||
|
|
@ -28,760 +28,5 @@ PAD_CTL_DSE_MAX (3 << 1)
|
|||
PAD_CTL_SRE_FAST (1 << 0)
|
||||
PAD_CTL_SRE_SLOW (0 << 0)
|
||||
|
||||
See below for available PIN_FUNC_ID for imx51:
|
||||
MX51_PAD_EIM_D16__AUD4_RXFS 0
|
||||
MX51_PAD_EIM_D16__AUD5_TXD 1
|
||||
MX51_PAD_EIM_D16__EIM_D16 2
|
||||
MX51_PAD_EIM_D16__GPIO2_0 3
|
||||
MX51_PAD_EIM_D16__I2C1_SDA 4
|
||||
MX51_PAD_EIM_D16__UART2_CTS 5
|
||||
MX51_PAD_EIM_D16__USBH2_DATA0 6
|
||||
MX51_PAD_EIM_D17__AUD5_RXD 7
|
||||
MX51_PAD_EIM_D17__EIM_D17 8
|
||||
MX51_PAD_EIM_D17__GPIO2_1 9
|
||||
MX51_PAD_EIM_D17__UART2_RXD 10
|
||||
MX51_PAD_EIM_D17__UART3_CTS 11
|
||||
MX51_PAD_EIM_D17__USBH2_DATA1 12
|
||||
MX51_PAD_EIM_D18__AUD5_TXC 13
|
||||
MX51_PAD_EIM_D18__EIM_D18 14
|
||||
MX51_PAD_EIM_D18__GPIO2_2 15
|
||||
MX51_PAD_EIM_D18__UART2_TXD 16
|
||||
MX51_PAD_EIM_D18__UART3_RTS 17
|
||||
MX51_PAD_EIM_D18__USBH2_DATA2 18
|
||||
MX51_PAD_EIM_D19__AUD4_RXC 19
|
||||
MX51_PAD_EIM_D19__AUD5_TXFS 20
|
||||
MX51_PAD_EIM_D19__EIM_D19 21
|
||||
MX51_PAD_EIM_D19__GPIO2_3 22
|
||||
MX51_PAD_EIM_D19__I2C1_SCL 23
|
||||
MX51_PAD_EIM_D19__UART2_RTS 24
|
||||
MX51_PAD_EIM_D19__USBH2_DATA3 25
|
||||
MX51_PAD_EIM_D20__AUD4_TXD 26
|
||||
MX51_PAD_EIM_D20__EIM_D20 27
|
||||
MX51_PAD_EIM_D20__GPIO2_4 28
|
||||
MX51_PAD_EIM_D20__SRTC_ALARM_DEB 29
|
||||
MX51_PAD_EIM_D20__USBH2_DATA4 30
|
||||
MX51_PAD_EIM_D21__AUD4_RXD 31
|
||||
MX51_PAD_EIM_D21__EIM_D21 32
|
||||
MX51_PAD_EIM_D21__GPIO2_5 33
|
||||
MX51_PAD_EIM_D21__SRTC_ALARM_DEB 34
|
||||
MX51_PAD_EIM_D21__USBH2_DATA5 35
|
||||
MX51_PAD_EIM_D22__AUD4_TXC 36
|
||||
MX51_PAD_EIM_D22__EIM_D22 37
|
||||
MX51_PAD_EIM_D22__GPIO2_6 38
|
||||
MX51_PAD_EIM_D22__USBH2_DATA6 39
|
||||
MX51_PAD_EIM_D23__AUD4_TXFS 40
|
||||
MX51_PAD_EIM_D23__EIM_D23 41
|
||||
MX51_PAD_EIM_D23__GPIO2_7 42
|
||||
MX51_PAD_EIM_D23__SPDIF_OUT1 43
|
||||
MX51_PAD_EIM_D23__USBH2_DATA7 44
|
||||
MX51_PAD_EIM_D24__AUD6_RXFS 45
|
||||
MX51_PAD_EIM_D24__EIM_D24 46
|
||||
MX51_PAD_EIM_D24__GPIO2_8 47
|
||||
MX51_PAD_EIM_D24__I2C2_SDA 48
|
||||
MX51_PAD_EIM_D24__UART3_CTS 49
|
||||
MX51_PAD_EIM_D24__USBOTG_DATA0 50
|
||||
MX51_PAD_EIM_D25__EIM_D25 51
|
||||
MX51_PAD_EIM_D25__KEY_COL6 52
|
||||
MX51_PAD_EIM_D25__UART2_CTS 53
|
||||
MX51_PAD_EIM_D25__UART3_RXD 54
|
||||
MX51_PAD_EIM_D25__USBOTG_DATA1 55
|
||||
MX51_PAD_EIM_D26__EIM_D26 56
|
||||
MX51_PAD_EIM_D26__KEY_COL7 57
|
||||
MX51_PAD_EIM_D26__UART2_RTS 58
|
||||
MX51_PAD_EIM_D26__UART3_TXD 59
|
||||
MX51_PAD_EIM_D26__USBOTG_DATA2 60
|
||||
MX51_PAD_EIM_D27__AUD6_RXC 61
|
||||
MX51_PAD_EIM_D27__EIM_D27 62
|
||||
MX51_PAD_EIM_D27__GPIO2_9 63
|
||||
MX51_PAD_EIM_D27__I2C2_SCL 64
|
||||
MX51_PAD_EIM_D27__UART3_RTS 65
|
||||
MX51_PAD_EIM_D27__USBOTG_DATA3 66
|
||||
MX51_PAD_EIM_D28__AUD6_TXD 67
|
||||
MX51_PAD_EIM_D28__EIM_D28 68
|
||||
MX51_PAD_EIM_D28__KEY_ROW4 69
|
||||
MX51_PAD_EIM_D28__USBOTG_DATA4 70
|
||||
MX51_PAD_EIM_D29__AUD6_RXD 71
|
||||
MX51_PAD_EIM_D29__EIM_D29 72
|
||||
MX51_PAD_EIM_D29__KEY_ROW5 73
|
||||
MX51_PAD_EIM_D29__USBOTG_DATA5 74
|
||||
MX51_PAD_EIM_D30__AUD6_TXC 75
|
||||
MX51_PAD_EIM_D30__EIM_D30 76
|
||||
MX51_PAD_EIM_D30__KEY_ROW6 77
|
||||
MX51_PAD_EIM_D30__USBOTG_DATA6 78
|
||||
MX51_PAD_EIM_D31__AUD6_TXFS 79
|
||||
MX51_PAD_EIM_D31__EIM_D31 80
|
||||
MX51_PAD_EIM_D31__KEY_ROW7 81
|
||||
MX51_PAD_EIM_D31__USBOTG_DATA7 82
|
||||
MX51_PAD_EIM_A16__EIM_A16 83
|
||||
MX51_PAD_EIM_A16__GPIO2_10 84
|
||||
MX51_PAD_EIM_A16__OSC_FREQ_SEL0 85
|
||||
MX51_PAD_EIM_A17__EIM_A17 86
|
||||
MX51_PAD_EIM_A17__GPIO2_11 87
|
||||
MX51_PAD_EIM_A17__OSC_FREQ_SEL1 88
|
||||
MX51_PAD_EIM_A18__BOOT_LPB0 89
|
||||
MX51_PAD_EIM_A18__EIM_A18 90
|
||||
MX51_PAD_EIM_A18__GPIO2_12 91
|
||||
MX51_PAD_EIM_A19__BOOT_LPB1 92
|
||||
MX51_PAD_EIM_A19__EIM_A19 93
|
||||
MX51_PAD_EIM_A19__GPIO2_13 94
|
||||
MX51_PAD_EIM_A20__BOOT_UART_SRC0 95
|
||||
MX51_PAD_EIM_A20__EIM_A20 96
|
||||
MX51_PAD_EIM_A20__GPIO2_14 97
|
||||
MX51_PAD_EIM_A21__BOOT_UART_SRC1 98
|
||||
MX51_PAD_EIM_A21__EIM_A21 99
|
||||
MX51_PAD_EIM_A21__GPIO2_15 100
|
||||
MX51_PAD_EIM_A22__EIM_A22 101
|
||||
MX51_PAD_EIM_A22__GPIO2_16 102
|
||||
MX51_PAD_EIM_A23__BOOT_HPN_EN 103
|
||||
MX51_PAD_EIM_A23__EIM_A23 104
|
||||
MX51_PAD_EIM_A23__GPIO2_17 105
|
||||
MX51_PAD_EIM_A24__EIM_A24 106
|
||||
MX51_PAD_EIM_A24__GPIO2_18 107
|
||||
MX51_PAD_EIM_A24__USBH2_CLK 108
|
||||
MX51_PAD_EIM_A25__DISP1_PIN4 109
|
||||
MX51_PAD_EIM_A25__EIM_A25 110
|
||||
MX51_PAD_EIM_A25__GPIO2_19 111
|
||||
MX51_PAD_EIM_A25__USBH2_DIR 112
|
||||
MX51_PAD_EIM_A26__CSI1_DATA_EN 113
|
||||
MX51_PAD_EIM_A26__DISP2_EXT_CLK 114
|
||||
MX51_PAD_EIM_A26__EIM_A26 115
|
||||
MX51_PAD_EIM_A26__GPIO2_20 116
|
||||
MX51_PAD_EIM_A26__USBH2_STP 117
|
||||
MX51_PAD_EIM_A27__CSI2_DATA_EN 118
|
||||
MX51_PAD_EIM_A27__DISP1_PIN1 119
|
||||
MX51_PAD_EIM_A27__EIM_A27 120
|
||||
MX51_PAD_EIM_A27__GPIO2_21 121
|
||||
MX51_PAD_EIM_A27__USBH2_NXT 122
|
||||
MX51_PAD_EIM_EB0__EIM_EB0 123
|
||||
MX51_PAD_EIM_EB1__EIM_EB1 124
|
||||
MX51_PAD_EIM_EB2__AUD5_RXFS 125
|
||||
MX51_PAD_EIM_EB2__CSI1_D2 126
|
||||
MX51_PAD_EIM_EB2__EIM_EB2 127
|
||||
MX51_PAD_EIM_EB2__FEC_MDIO 128
|
||||
MX51_PAD_EIM_EB2__GPIO2_22 129
|
||||
MX51_PAD_EIM_EB2__GPT_CMPOUT1 130
|
||||
MX51_PAD_EIM_EB3__AUD5_RXC 131
|
||||
MX51_PAD_EIM_EB3__CSI1_D3 132
|
||||
MX51_PAD_EIM_EB3__EIM_EB3 133
|
||||
MX51_PAD_EIM_EB3__FEC_RDATA1 134
|
||||
MX51_PAD_EIM_EB3__GPIO2_23 135
|
||||
MX51_PAD_EIM_EB3__GPT_CMPOUT2 136
|
||||
MX51_PAD_EIM_OE__EIM_OE 137
|
||||
MX51_PAD_EIM_OE__GPIO2_24 138
|
||||
MX51_PAD_EIM_CS0__EIM_CS0 139
|
||||
MX51_PAD_EIM_CS0__GPIO2_25 140
|
||||
MX51_PAD_EIM_CS1__EIM_CS1 141
|
||||
MX51_PAD_EIM_CS1__GPIO2_26 142
|
||||
MX51_PAD_EIM_CS2__AUD5_TXD 143
|
||||
MX51_PAD_EIM_CS2__CSI1_D4 144
|
||||
MX51_PAD_EIM_CS2__EIM_CS2 145
|
||||
MX51_PAD_EIM_CS2__FEC_RDATA2 146
|
||||
MX51_PAD_EIM_CS2__GPIO2_27 147
|
||||
MX51_PAD_EIM_CS2__USBOTG_STP 148
|
||||
MX51_PAD_EIM_CS3__AUD5_RXD 149
|
||||
MX51_PAD_EIM_CS3__CSI1_D5 150
|
||||
MX51_PAD_EIM_CS3__EIM_CS3 151
|
||||
MX51_PAD_EIM_CS3__FEC_RDATA3 152
|
||||
MX51_PAD_EIM_CS3__GPIO2_28 153
|
||||
MX51_PAD_EIM_CS3__USBOTG_NXT 154
|
||||
MX51_PAD_EIM_CS4__AUD5_TXC 155
|
||||
MX51_PAD_EIM_CS4__CSI1_D6 156
|
||||
MX51_PAD_EIM_CS4__EIM_CS4 157
|
||||
MX51_PAD_EIM_CS4__FEC_RX_ER 158
|
||||
MX51_PAD_EIM_CS4__GPIO2_29 159
|
||||
MX51_PAD_EIM_CS4__USBOTG_CLK 160
|
||||
MX51_PAD_EIM_CS5__AUD5_TXFS 161
|
||||
MX51_PAD_EIM_CS5__CSI1_D7 162
|
||||
MX51_PAD_EIM_CS5__DISP1_EXT_CLK 163
|
||||
MX51_PAD_EIM_CS5__EIM_CS5 164
|
||||
MX51_PAD_EIM_CS5__FEC_CRS 165
|
||||
MX51_PAD_EIM_CS5__GPIO2_30 166
|
||||
MX51_PAD_EIM_CS5__USBOTG_DIR 167
|
||||
MX51_PAD_EIM_DTACK__EIM_DTACK 168
|
||||
MX51_PAD_EIM_DTACK__GPIO2_31 169
|
||||
MX51_PAD_EIM_LBA__EIM_LBA 170
|
||||
MX51_PAD_EIM_LBA__GPIO3_1 171
|
||||
MX51_PAD_EIM_CRE__EIM_CRE 172
|
||||
MX51_PAD_EIM_CRE__GPIO3_2 173
|
||||
MX51_PAD_DRAM_CS1__DRAM_CS1 174
|
||||
MX51_PAD_NANDF_WE_B__GPIO3_3 175
|
||||
MX51_PAD_NANDF_WE_B__NANDF_WE_B 176
|
||||
MX51_PAD_NANDF_WE_B__PATA_DIOW 177
|
||||
MX51_PAD_NANDF_WE_B__SD3_DATA0 178
|
||||
MX51_PAD_NANDF_RE_B__GPIO3_4 179
|
||||
MX51_PAD_NANDF_RE_B__NANDF_RE_B 180
|
||||
MX51_PAD_NANDF_RE_B__PATA_DIOR 181
|
||||
MX51_PAD_NANDF_RE_B__SD3_DATA1 182
|
||||
MX51_PAD_NANDF_ALE__GPIO3_5 183
|
||||
MX51_PAD_NANDF_ALE__NANDF_ALE 184
|
||||
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 185
|
||||
MX51_PAD_NANDF_CLE__GPIO3_6 186
|
||||
MX51_PAD_NANDF_CLE__NANDF_CLE 187
|
||||
MX51_PAD_NANDF_CLE__PATA_RESET_B 188
|
||||
MX51_PAD_NANDF_WP_B__GPIO3_7 189
|
||||
MX51_PAD_NANDF_WP_B__NANDF_WP_B 190
|
||||
MX51_PAD_NANDF_WP_B__PATA_DMACK 191
|
||||
MX51_PAD_NANDF_WP_B__SD3_DATA2 192
|
||||
MX51_PAD_NANDF_RB0__ECSPI2_SS1 193
|
||||
MX51_PAD_NANDF_RB0__GPIO3_8 194
|
||||
MX51_PAD_NANDF_RB0__NANDF_RB0 195
|
||||
MX51_PAD_NANDF_RB0__PATA_DMARQ 196
|
||||
MX51_PAD_NANDF_RB0__SD3_DATA3 197
|
||||
MX51_PAD_NANDF_RB1__CSPI_MOSI 198
|
||||
MX51_PAD_NANDF_RB1__ECSPI2_RDY 199
|
||||
MX51_PAD_NANDF_RB1__GPIO3_9 200
|
||||
MX51_PAD_NANDF_RB1__NANDF_RB1 201
|
||||
MX51_PAD_NANDF_RB1__PATA_IORDY 202
|
||||
MX51_PAD_NANDF_RB1__SD4_CMD 203
|
||||
MX51_PAD_NANDF_RB2__DISP2_WAIT 204
|
||||
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 205
|
||||
MX51_PAD_NANDF_RB2__FEC_COL 206
|
||||
MX51_PAD_NANDF_RB2__GPIO3_10 207
|
||||
MX51_PAD_NANDF_RB2__NANDF_RB2 208
|
||||
MX51_PAD_NANDF_RB2__USBH3_H3_DP 209
|
||||
MX51_PAD_NANDF_RB2__USBH3_NXT 210
|
||||
MX51_PAD_NANDF_RB3__DISP1_WAIT 211
|
||||
MX51_PAD_NANDF_RB3__ECSPI2_MISO 212
|
||||
MX51_PAD_NANDF_RB3__FEC_RX_CLK 213
|
||||
MX51_PAD_NANDF_RB3__GPIO3_11 214
|
||||
MX51_PAD_NANDF_RB3__NANDF_RB3 215
|
||||
MX51_PAD_NANDF_RB3__USBH3_CLK 216
|
||||
MX51_PAD_NANDF_RB3__USBH3_H3_DM 217
|
||||
MX51_PAD_GPIO_NAND__GPIO_NAND 218
|
||||
MX51_PAD_GPIO_NAND__PATA_INTRQ 219
|
||||
MX51_PAD_NANDF_CS0__GPIO3_16 220
|
||||
MX51_PAD_NANDF_CS0__NANDF_CS0 221
|
||||
MX51_PAD_NANDF_CS1__GPIO3_17 222
|
||||
MX51_PAD_NANDF_CS1__NANDF_CS1 223
|
||||
MX51_PAD_NANDF_CS2__CSPI_SCLK 224
|
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER 225
|
||||
MX51_PAD_NANDF_CS2__GPIO3_18 226
|
||||
MX51_PAD_NANDF_CS2__NANDF_CS2 227
|
||||
MX51_PAD_NANDF_CS2__PATA_CS_0 228
|
||||
MX51_PAD_NANDF_CS2__SD4_CLK 229
|
||||
MX51_PAD_NANDF_CS2__USBH3_H1_DP 230
|
||||
MX51_PAD_NANDF_CS3__FEC_MDC 231
|
||||
MX51_PAD_NANDF_CS3__GPIO3_19 232
|
||||
MX51_PAD_NANDF_CS3__NANDF_CS3 233
|
||||
MX51_PAD_NANDF_CS3__PATA_CS_1 234
|
||||
MX51_PAD_NANDF_CS3__SD4_DAT0 235
|
||||
MX51_PAD_NANDF_CS3__USBH3_H1_DM 236
|
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1 237
|
||||
MX51_PAD_NANDF_CS4__GPIO3_20 238
|
||||
MX51_PAD_NANDF_CS4__NANDF_CS4 239
|
||||
MX51_PAD_NANDF_CS4__PATA_DA_0 240
|
||||
MX51_PAD_NANDF_CS4__SD4_DAT1 241
|
||||
MX51_PAD_NANDF_CS4__USBH3_STP 242
|
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2 243
|
||||
MX51_PAD_NANDF_CS5__GPIO3_21 244
|
||||
MX51_PAD_NANDF_CS5__NANDF_CS5 245
|
||||
MX51_PAD_NANDF_CS5__PATA_DA_1 246
|
||||
MX51_PAD_NANDF_CS5__SD4_DAT2 247
|
||||
MX51_PAD_NANDF_CS5__USBH3_DIR 248
|
||||
MX51_PAD_NANDF_CS6__CSPI_SS3 249
|
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3 250
|
||||
MX51_PAD_NANDF_CS6__GPIO3_22 251
|
||||
MX51_PAD_NANDF_CS6__NANDF_CS6 252
|
||||
MX51_PAD_NANDF_CS6__PATA_DA_2 253
|
||||
MX51_PAD_NANDF_CS6__SD4_DAT3 254
|
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN 255
|
||||
MX51_PAD_NANDF_CS7__GPIO3_23 256
|
||||
MX51_PAD_NANDF_CS7__NANDF_CS7 257
|
||||
MX51_PAD_NANDF_CS7__SD3_CLK 258
|
||||
MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 259
|
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 260
|
||||
MX51_PAD_NANDF_RDY_INT__GPIO3_24 261
|
||||
MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 262
|
||||
MX51_PAD_NANDF_RDY_INT__SD3_CMD 263
|
||||
MX51_PAD_NANDF_D15__ECSPI2_MOSI 264
|
||||
MX51_PAD_NANDF_D15__GPIO3_25 265
|
||||
MX51_PAD_NANDF_D15__NANDF_D15 266
|
||||
MX51_PAD_NANDF_D15__PATA_DATA15 267
|
||||
MX51_PAD_NANDF_D15__SD3_DAT7 268
|
||||
MX51_PAD_NANDF_D14__ECSPI2_SS3 269
|
||||
MX51_PAD_NANDF_D14__GPIO3_26 270
|
||||
MX51_PAD_NANDF_D14__NANDF_D14 271
|
||||
MX51_PAD_NANDF_D14__PATA_DATA14 272
|
||||
MX51_PAD_NANDF_D14__SD3_DAT6 273
|
||||
MX51_PAD_NANDF_D13__ECSPI2_SS2 274
|
||||
MX51_PAD_NANDF_D13__GPIO3_27 275
|
||||
MX51_PAD_NANDF_D13__NANDF_D13 276
|
||||
MX51_PAD_NANDF_D13__PATA_DATA13 277
|
||||
MX51_PAD_NANDF_D13__SD3_DAT5 278
|
||||
MX51_PAD_NANDF_D12__ECSPI2_SS1 279
|
||||
MX51_PAD_NANDF_D12__GPIO3_28 280
|
||||
MX51_PAD_NANDF_D12__NANDF_D12 281
|
||||
MX51_PAD_NANDF_D12__PATA_DATA12 282
|
||||
MX51_PAD_NANDF_D12__SD3_DAT4 283
|
||||
MX51_PAD_NANDF_D11__FEC_RX_DV 284
|
||||
MX51_PAD_NANDF_D11__GPIO3_29 285
|
||||
MX51_PAD_NANDF_D11__NANDF_D11 286
|
||||
MX51_PAD_NANDF_D11__PATA_DATA11 287
|
||||
MX51_PAD_NANDF_D11__SD3_DATA3 288
|
||||
MX51_PAD_NANDF_D10__GPIO3_30 289
|
||||
MX51_PAD_NANDF_D10__NANDF_D10 290
|
||||
MX51_PAD_NANDF_D10__PATA_DATA10 291
|
||||
MX51_PAD_NANDF_D10__SD3_DATA2 292
|
||||
MX51_PAD_NANDF_D9__FEC_RDATA0 293
|
||||
MX51_PAD_NANDF_D9__GPIO3_31 294
|
||||
MX51_PAD_NANDF_D9__NANDF_D9 295
|
||||
MX51_PAD_NANDF_D9__PATA_DATA9 296
|
||||
MX51_PAD_NANDF_D9__SD3_DATA1 297
|
||||
MX51_PAD_NANDF_D8__FEC_TDATA0 298
|
||||
MX51_PAD_NANDF_D8__GPIO4_0 299
|
||||
MX51_PAD_NANDF_D8__NANDF_D8 300
|
||||
MX51_PAD_NANDF_D8__PATA_DATA8 301
|
||||
MX51_PAD_NANDF_D8__SD3_DATA0 302
|
||||
MX51_PAD_NANDF_D7__GPIO4_1 303
|
||||
MX51_PAD_NANDF_D7__NANDF_D7 304
|
||||
MX51_PAD_NANDF_D7__PATA_DATA7 305
|
||||
MX51_PAD_NANDF_D7__USBH3_DATA0 306
|
||||
MX51_PAD_NANDF_D6__GPIO4_2 307
|
||||
MX51_PAD_NANDF_D6__NANDF_D6 308
|
||||
MX51_PAD_NANDF_D6__PATA_DATA6 309
|
||||
MX51_PAD_NANDF_D6__SD4_LCTL 310
|
||||
MX51_PAD_NANDF_D6__USBH3_DATA1 311
|
||||
MX51_PAD_NANDF_D5__GPIO4_3 312
|
||||
MX51_PAD_NANDF_D5__NANDF_D5 313
|
||||
MX51_PAD_NANDF_D5__PATA_DATA5 314
|
||||
MX51_PAD_NANDF_D5__SD4_WP 315
|
||||
MX51_PAD_NANDF_D5__USBH3_DATA2 316
|
||||
MX51_PAD_NANDF_D4__GPIO4_4 317
|
||||
MX51_PAD_NANDF_D4__NANDF_D4 318
|
||||
MX51_PAD_NANDF_D4__PATA_DATA4 319
|
||||
MX51_PAD_NANDF_D4__SD4_CD 320
|
||||
MX51_PAD_NANDF_D4__USBH3_DATA3 321
|
||||
MX51_PAD_NANDF_D3__GPIO4_5 322
|
||||
MX51_PAD_NANDF_D3__NANDF_D3 323
|
||||
MX51_PAD_NANDF_D3__PATA_DATA3 324
|
||||
MX51_PAD_NANDF_D3__SD4_DAT4 325
|
||||
MX51_PAD_NANDF_D3__USBH3_DATA4 326
|
||||
MX51_PAD_NANDF_D2__GPIO4_6 327
|
||||
MX51_PAD_NANDF_D2__NANDF_D2 328
|
||||
MX51_PAD_NANDF_D2__PATA_DATA2 329
|
||||
MX51_PAD_NANDF_D2__SD4_DAT5 330
|
||||
MX51_PAD_NANDF_D2__USBH3_DATA5 331
|
||||
MX51_PAD_NANDF_D1__GPIO4_7 332
|
||||
MX51_PAD_NANDF_D1__NANDF_D1 333
|
||||
MX51_PAD_NANDF_D1__PATA_DATA1 334
|
||||
MX51_PAD_NANDF_D1__SD4_DAT6 335
|
||||
MX51_PAD_NANDF_D1__USBH3_DATA6 336
|
||||
MX51_PAD_NANDF_D0__GPIO4_8 337
|
||||
MX51_PAD_NANDF_D0__NANDF_D0 338
|
||||
MX51_PAD_NANDF_D0__PATA_DATA0 339
|
||||
MX51_PAD_NANDF_D0__SD4_DAT7 340
|
||||
MX51_PAD_NANDF_D0__USBH3_DATA7 341
|
||||
MX51_PAD_CSI1_D8__CSI1_D8 342
|
||||
MX51_PAD_CSI1_D8__GPIO3_12 343
|
||||
MX51_PAD_CSI1_D9__CSI1_D9 344
|
||||
MX51_PAD_CSI1_D9__GPIO3_13 345
|
||||
MX51_PAD_CSI1_D10__CSI1_D10 346
|
||||
MX51_PAD_CSI1_D11__CSI1_D11 347
|
||||
MX51_PAD_CSI1_D12__CSI1_D12 348
|
||||
MX51_PAD_CSI1_D13__CSI1_D13 349
|
||||
MX51_PAD_CSI1_D14__CSI1_D14 350
|
||||
MX51_PAD_CSI1_D15__CSI1_D15 351
|
||||
MX51_PAD_CSI1_D16__CSI1_D16 352
|
||||
MX51_PAD_CSI1_D17__CSI1_D17 353
|
||||
MX51_PAD_CSI1_D18__CSI1_D18 354
|
||||
MX51_PAD_CSI1_D19__CSI1_D19 355
|
||||
MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 356
|
||||
MX51_PAD_CSI1_VSYNC__GPIO3_14 357
|
||||
MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 358
|
||||
MX51_PAD_CSI1_HSYNC__GPIO3_15 359
|
||||
MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 360
|
||||
MX51_PAD_CSI1_MCLK__CSI1_MCLK 361
|
||||
MX51_PAD_CSI2_D12__CSI2_D12 362
|
||||
MX51_PAD_CSI2_D12__GPIO4_9 363
|
||||
MX51_PAD_CSI2_D13__CSI2_D13 364
|
||||
MX51_PAD_CSI2_D13__GPIO4_10 365
|
||||
MX51_PAD_CSI2_D14__CSI2_D14 366
|
||||
MX51_PAD_CSI2_D15__CSI2_D15 367
|
||||
MX51_PAD_CSI2_D16__CSI2_D16 368
|
||||
MX51_PAD_CSI2_D17__CSI2_D17 369
|
||||
MX51_PAD_CSI2_D18__CSI2_D18 370
|
||||
MX51_PAD_CSI2_D18__GPIO4_11 371
|
||||
MX51_PAD_CSI2_D19__CSI2_D19 372
|
||||
MX51_PAD_CSI2_D19__GPIO4_12 373
|
||||
MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 374
|
||||
MX51_PAD_CSI2_VSYNC__GPIO4_13 375
|
||||
MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 376
|
||||
MX51_PAD_CSI2_HSYNC__GPIO4_14 377
|
||||
MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 378
|
||||
MX51_PAD_CSI2_PIXCLK__GPIO4_15 379
|
||||
MX51_PAD_I2C1_CLK__GPIO4_16 380
|
||||
MX51_PAD_I2C1_CLK__I2C1_CLK 381
|
||||
MX51_PAD_I2C1_DAT__GPIO4_17 382
|
||||
MX51_PAD_I2C1_DAT__I2C1_DAT 383
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 384
|
||||
MX51_PAD_AUD3_BB_TXD__GPIO4_18 385
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 386
|
||||
MX51_PAD_AUD3_BB_RXD__GPIO4_19 387
|
||||
MX51_PAD_AUD3_BB_RXD__UART3_RXD 388
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 389
|
||||
MX51_PAD_AUD3_BB_CK__GPIO4_20 390
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 391
|
||||
MX51_PAD_AUD3_BB_FS__GPIO4_21 392
|
||||
MX51_PAD_AUD3_BB_FS__UART3_TXD 393
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 394
|
||||
MX51_PAD_CSPI1_MOSI__GPIO4_22 395
|
||||
MX51_PAD_CSPI1_MOSI__I2C1_SDA 396
|
||||
MX51_PAD_CSPI1_MISO__AUD4_RXD 397
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 398
|
||||
MX51_PAD_CSPI1_MISO__GPIO4_23 399
|
||||
MX51_PAD_CSPI1_SS0__AUD4_TXC 400
|
||||
MX51_PAD_CSPI1_SS0__ECSPI1_SS0 401
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 402
|
||||
MX51_PAD_CSPI1_SS1__AUD4_TXD 403
|
||||
MX51_PAD_CSPI1_SS1__ECSPI1_SS1 404
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 405
|
||||
MX51_PAD_CSPI1_RDY__AUD4_TXFS 406
|
||||
MX51_PAD_CSPI1_RDY__ECSPI1_RDY 407
|
||||
MX51_PAD_CSPI1_RDY__GPIO4_26 408
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 409
|
||||
MX51_PAD_CSPI1_SCLK__GPIO4_27 410
|
||||
MX51_PAD_CSPI1_SCLK__I2C1_SCL 411
|
||||
MX51_PAD_UART1_RXD__GPIO4_28 412
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 413
|
||||
MX51_PAD_UART1_TXD__GPIO4_29 414
|
||||
MX51_PAD_UART1_TXD__PWM2_PWMO 415
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 416
|
||||
MX51_PAD_UART1_RTS__GPIO4_30 417
|
||||
MX51_PAD_UART1_RTS__UART1_RTS 418
|
||||
MX51_PAD_UART1_CTS__GPIO4_31 419
|
||||
MX51_PAD_UART1_CTS__UART1_CTS 420
|
||||
MX51_PAD_UART2_RXD__FIRI_TXD 421
|
||||
MX51_PAD_UART2_RXD__GPIO1_20 422
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 423
|
||||
MX51_PAD_UART2_TXD__FIRI_RXD 424
|
||||
MX51_PAD_UART2_TXD__GPIO1_21 425
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 426
|
||||
MX51_PAD_UART3_RXD__CSI1_D0 427
|
||||
MX51_PAD_UART3_RXD__GPIO1_22 428
|
||||
MX51_PAD_UART3_RXD__UART1_DTR 429
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 430
|
||||
MX51_PAD_UART3_TXD__CSI1_D1 431
|
||||
MX51_PAD_UART3_TXD__GPIO1_23 432
|
||||
MX51_PAD_UART3_TXD__UART1_DSR 433
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 434
|
||||
MX51_PAD_OWIRE_LINE__GPIO1_24 435
|
||||
MX51_PAD_OWIRE_LINE__OWIRE_LINE 436
|
||||
MX51_PAD_OWIRE_LINE__SPDIF_OUT 437
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0 438
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1 439
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2 440
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3 441
|
||||
MX51_PAD_KEY_COL0__KEY_COL0 442
|
||||
MX51_PAD_KEY_COL0__PLL1_BYP 443
|
||||
MX51_PAD_KEY_COL1__KEY_COL1 444
|
||||
MX51_PAD_KEY_COL1__PLL2_BYP 445
|
||||
MX51_PAD_KEY_COL2__KEY_COL2 446
|
||||
MX51_PAD_KEY_COL2__PLL3_BYP 447
|
||||
MX51_PAD_KEY_COL3__KEY_COL3 448
|
||||
MX51_PAD_KEY_COL4__I2C2_SCL 449
|
||||
MX51_PAD_KEY_COL4__KEY_COL4 450
|
||||
MX51_PAD_KEY_COL4__SPDIF_OUT1 451
|
||||
MX51_PAD_KEY_COL4__UART1_RI 452
|
||||
MX51_PAD_KEY_COL4__UART3_RTS 453
|
||||
MX51_PAD_KEY_COL5__I2C2_SDA 454
|
||||
MX51_PAD_KEY_COL5__KEY_COL5 455
|
||||
MX51_PAD_KEY_COL5__UART1_DCD 456
|
||||
MX51_PAD_KEY_COL5__UART3_CTS 457
|
||||
MX51_PAD_USBH1_CLK__CSPI_SCLK 458
|
||||
MX51_PAD_USBH1_CLK__GPIO1_25 459
|
||||
MX51_PAD_USBH1_CLK__I2C2_SCL 460
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 461
|
||||
MX51_PAD_USBH1_DIR__CSPI_MOSI 462
|
||||
MX51_PAD_USBH1_DIR__GPIO1_26 463
|
||||
MX51_PAD_USBH1_DIR__I2C2_SDA 464
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 465
|
||||
MX51_PAD_USBH1_STP__CSPI_RDY 466
|
||||
MX51_PAD_USBH1_STP__GPIO1_27 467
|
||||
MX51_PAD_USBH1_STP__UART3_RXD 468
|
||||
MX51_PAD_USBH1_STP__USBH1_STP 469
|
||||
MX51_PAD_USBH1_NXT__CSPI_MISO 470
|
||||
MX51_PAD_USBH1_NXT__GPIO1_28 471
|
||||
MX51_PAD_USBH1_NXT__UART3_TXD 472
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 473
|
||||
MX51_PAD_USBH1_DATA0__GPIO1_11 474
|
||||
MX51_PAD_USBH1_DATA0__UART2_CTS 475
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 476
|
||||
MX51_PAD_USBH1_DATA1__GPIO1_12 477
|
||||
MX51_PAD_USBH1_DATA1__UART2_RXD 478
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 479
|
||||
MX51_PAD_USBH1_DATA2__GPIO1_13 480
|
||||
MX51_PAD_USBH1_DATA2__UART2_TXD 481
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 482
|
||||
MX51_PAD_USBH1_DATA3__GPIO1_14 483
|
||||
MX51_PAD_USBH1_DATA3__UART2_RTS 484
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 485
|
||||
MX51_PAD_USBH1_DATA4__CSPI_SS0 486
|
||||
MX51_PAD_USBH1_DATA4__GPIO1_15 487
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 488
|
||||
MX51_PAD_USBH1_DATA5__CSPI_SS1 489
|
||||
MX51_PAD_USBH1_DATA5__GPIO1_16 490
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 491
|
||||
MX51_PAD_USBH1_DATA6__CSPI_SS3 492
|
||||
MX51_PAD_USBH1_DATA6__GPIO1_17 493
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 494
|
||||
MX51_PAD_USBH1_DATA7__ECSPI1_SS3 495
|
||||
MX51_PAD_USBH1_DATA7__ECSPI2_SS3 496
|
||||
MX51_PAD_USBH1_DATA7__GPIO1_18 497
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 498
|
||||
MX51_PAD_DI1_PIN11__DI1_PIN11 499
|
||||
MX51_PAD_DI1_PIN11__ECSPI1_SS2 500
|
||||
MX51_PAD_DI1_PIN11__GPIO3_0 501
|
||||
MX51_PAD_DI1_PIN12__DI1_PIN12 502
|
||||
MX51_PAD_DI1_PIN12__GPIO3_1 503
|
||||
MX51_PAD_DI1_PIN13__DI1_PIN13 504
|
||||
MX51_PAD_DI1_PIN13__GPIO3_2 505
|
||||
MX51_PAD_DI1_D0_CS__DI1_D0_CS 506
|
||||
MX51_PAD_DI1_D0_CS__GPIO3_3 507
|
||||
MX51_PAD_DI1_D1_CS__DI1_D1_CS 508
|
||||
MX51_PAD_DI1_D1_CS__DISP1_PIN14 509
|
||||
MX51_PAD_DI1_D1_CS__DISP1_PIN5 510
|
||||
MX51_PAD_DI1_D1_CS__GPIO3_4 511
|
||||
MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 512
|
||||
MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 513
|
||||
MX51_PAD_DISPB2_SER_DIN__GPIO3_5 514
|
||||
MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 515
|
||||
MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 516
|
||||
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 517
|
||||
MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 518
|
||||
MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 519
|
||||
MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 520
|
||||
MX51_PAD_DISPB2_SER_CLK__GPIO3_7 521
|
||||
MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 522
|
||||
MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 523
|
||||
MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 524
|
||||
MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 525
|
||||
MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 526
|
||||
MX51_PAD_DISPB2_SER_RS__GPIO3_8 527
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 528
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 529
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 530
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 531
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 532
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 533
|
||||
MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 534
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 535
|
||||
MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 536
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 537
|
||||
MX51_PAD_DISP1_DAT8__BOOT_SRC0 538
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 539
|
||||
MX51_PAD_DISP1_DAT9__BOOT_SRC1 540
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 541
|
||||
MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 542
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 543
|
||||
MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 544
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 545
|
||||
MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 546
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 547
|
||||
MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 548
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 549
|
||||
MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 550
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 551
|
||||
MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 552
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 553
|
||||
MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 554
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 555
|
||||
MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 556
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 557
|
||||
MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 558
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 559
|
||||
MX51_PAD_DISP1_DAT18__DISP2_PIN11 560
|
||||
MX51_PAD_DISP1_DAT18__DISP2_PIN5 561
|
||||
MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 562
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 563
|
||||
MX51_PAD_DISP1_DAT19__DISP2_PIN12 564
|
||||
MX51_PAD_DISP1_DAT19__DISP2_PIN6 565
|
||||
MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 566
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 567
|
||||
MX51_PAD_DISP1_DAT20__DISP2_PIN13 568
|
||||
MX51_PAD_DISP1_DAT20__DISP2_PIN7 569
|
||||
MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 570
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 571
|
||||
MX51_PAD_DISP1_DAT21__DISP2_PIN14 572
|
||||
MX51_PAD_DISP1_DAT21__DISP2_PIN8 573
|
||||
MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 574
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 575
|
||||
MX51_PAD_DISP1_DAT22__DISP2_D0_CS 576
|
||||
MX51_PAD_DISP1_DAT22__DISP2_DAT16 577
|
||||
MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 578
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 579
|
||||
MX51_PAD_DISP1_DAT23__DISP2_D1_CS 580
|
||||
MX51_PAD_DISP1_DAT23__DISP2_DAT17 581
|
||||
MX51_PAD_DISP1_DAT23__DISP2_SER_CS 582
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 583
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 584
|
||||
MX51_PAD_DI_GP2__DISP1_SER_CLK 585
|
||||
MX51_PAD_DI_GP2__DISP2_WAIT 586
|
||||
MX51_PAD_DI_GP3__CSI1_DATA_EN 587
|
||||
MX51_PAD_DI_GP3__DISP1_SER_DIO 588
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 589
|
||||
MX51_PAD_DI2_PIN4__CSI2_DATA_EN 590
|
||||
MX51_PAD_DI2_PIN4__DI2_PIN4 591
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 592
|
||||
MX51_PAD_DI2_PIN2__DI2_PIN2 593
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 594
|
||||
MX51_PAD_DI2_PIN3__DI2_PIN3 595
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 596
|
||||
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 597
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 598
|
||||
MX51_PAD_DI_GP4__DI2_PIN15 599
|
||||
MX51_PAD_DI_GP4__DISP1_SER_DIN 600
|
||||
MX51_PAD_DI_GP4__DISP2_PIN1 601
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 602
|
||||
MX51_PAD_DISP2_DAT0__DISP2_DAT0 603
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 604
|
||||
MX51_PAD_DISP2_DAT0__KEY_COL6 605
|
||||
MX51_PAD_DISP2_DAT0__UART3_RXD 606
|
||||
MX51_PAD_DISP2_DAT0__USBH3_CLK 607
|
||||
MX51_PAD_DISP2_DAT1__DISP2_DAT1 608
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 609
|
||||
MX51_PAD_DISP2_DAT1__KEY_COL7 610
|
||||
MX51_PAD_DISP2_DAT1__UART3_TXD 611
|
||||
MX51_PAD_DISP2_DAT1__USBH3_DIR 612
|
||||
MX51_PAD_DISP2_DAT2__DISP2_DAT2 613
|
||||
MX51_PAD_DISP2_DAT3__DISP2_DAT3 614
|
||||
MX51_PAD_DISP2_DAT4__DISP2_DAT4 615
|
||||
MX51_PAD_DISP2_DAT5__DISP2_DAT5 616
|
||||
MX51_PAD_DISP2_DAT6__DISP2_DAT6 617
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 618
|
||||
MX51_PAD_DISP2_DAT6__GPIO1_19 619
|
||||
MX51_PAD_DISP2_DAT6__KEY_ROW4 620
|
||||
MX51_PAD_DISP2_DAT6__USBH3_STP 621
|
||||
MX51_PAD_DISP2_DAT7__DISP2_DAT7 622
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 623
|
||||
MX51_PAD_DISP2_DAT7__GPIO1_29 624
|
||||
MX51_PAD_DISP2_DAT7__KEY_ROW5 625
|
||||
MX51_PAD_DISP2_DAT7__USBH3_NXT 626
|
||||
MX51_PAD_DISP2_DAT8__DISP2_DAT8 627
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 628
|
||||
MX51_PAD_DISP2_DAT8__GPIO1_30 629
|
||||
MX51_PAD_DISP2_DAT8__KEY_ROW6 630
|
||||
MX51_PAD_DISP2_DAT8__USBH3_DATA0 631
|
||||
MX51_PAD_DISP2_DAT9__AUD6_RXC 632
|
||||
MX51_PAD_DISP2_DAT9__DISP2_DAT9 633
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 634
|
||||
MX51_PAD_DISP2_DAT9__GPIO1_31 635
|
||||
MX51_PAD_DISP2_DAT9__USBH3_DATA1 636
|
||||
MX51_PAD_DISP2_DAT10__DISP2_DAT10 637
|
||||
MX51_PAD_DISP2_DAT10__DISP2_SER_CS 638
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 639
|
||||
MX51_PAD_DISP2_DAT10__KEY_ROW7 640
|
||||
MX51_PAD_DISP2_DAT10__USBH3_DATA2 641
|
||||
MX51_PAD_DISP2_DAT11__AUD6_TXD 642
|
||||
MX51_PAD_DISP2_DAT11__DISP2_DAT11 643
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 644
|
||||
MX51_PAD_DISP2_DAT11__GPIO1_10 645
|
||||
MX51_PAD_DISP2_DAT11__USBH3_DATA3 646
|
||||
MX51_PAD_DISP2_DAT12__AUD6_RXD 647
|
||||
MX51_PAD_DISP2_DAT12__DISP2_DAT12 648
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 649
|
||||
MX51_PAD_DISP2_DAT12__USBH3_DATA4 650
|
||||
MX51_PAD_DISP2_DAT13__AUD6_TXC 651
|
||||
MX51_PAD_DISP2_DAT13__DISP2_DAT13 652
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 653
|
||||
MX51_PAD_DISP2_DAT13__USBH3_DATA5 654
|
||||
MX51_PAD_DISP2_DAT14__AUD6_TXFS 655
|
||||
MX51_PAD_DISP2_DAT14__DISP2_DAT14 656
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 657
|
||||
MX51_PAD_DISP2_DAT14__USBH3_DATA6 658
|
||||
MX51_PAD_DISP2_DAT15__AUD6_RXFS 659
|
||||
MX51_PAD_DISP2_DAT15__DISP1_SER_CS 660
|
||||
MX51_PAD_DISP2_DAT15__DISP2_DAT15 661
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 662
|
||||
MX51_PAD_DISP2_DAT15__USBH3_DATA7 663
|
||||
MX51_PAD_SD1_CMD__AUD5_RXFS 664
|
||||
MX51_PAD_SD1_CMD__CSPI_MOSI 665
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 666
|
||||
MX51_PAD_SD1_CLK__AUD5_RXC 667
|
||||
MX51_PAD_SD1_CLK__CSPI_SCLK 668
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 669
|
||||
MX51_PAD_SD1_DATA0__AUD5_TXD 670
|
||||
MX51_PAD_SD1_DATA0__CSPI_MISO 671
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 672
|
||||
MX51_PAD_EIM_DA0__EIM_DA0 673
|
||||
MX51_PAD_EIM_DA1__EIM_DA1 674
|
||||
MX51_PAD_EIM_DA2__EIM_DA2 675
|
||||
MX51_PAD_EIM_DA3__EIM_DA3 676
|
||||
MX51_PAD_SD1_DATA1__AUD5_RXD 677
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 678
|
||||
MX51_PAD_EIM_DA4__EIM_DA4 679
|
||||
MX51_PAD_EIM_DA5__EIM_DA5 680
|
||||
MX51_PAD_EIM_DA6__EIM_DA6 681
|
||||
MX51_PAD_EIM_DA7__EIM_DA7 682
|
||||
MX51_PAD_SD1_DATA2__AUD5_TXC 683
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 684
|
||||
MX51_PAD_EIM_DA10__EIM_DA10 685
|
||||
MX51_PAD_EIM_DA11__EIM_DA11 686
|
||||
MX51_PAD_EIM_DA8__EIM_DA8 687
|
||||
MX51_PAD_EIM_DA9__EIM_DA9 688
|
||||
MX51_PAD_SD1_DATA3__AUD5_TXFS 689
|
||||
MX51_PAD_SD1_DATA3__CSPI_SS1 690
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 691
|
||||
MX51_PAD_GPIO1_0__CSPI_SS2 692
|
||||
MX51_PAD_GPIO1_0__GPIO1_0 693
|
||||
MX51_PAD_GPIO1_0__SD1_CD 694
|
||||
MX51_PAD_GPIO1_1__CSPI_MISO 695
|
||||
MX51_PAD_GPIO1_1__GPIO1_1 696
|
||||
MX51_PAD_GPIO1_1__SD1_WP 697
|
||||
MX51_PAD_EIM_DA12__EIM_DA12 698
|
||||
MX51_PAD_EIM_DA13__EIM_DA13 699
|
||||
MX51_PAD_EIM_DA14__EIM_DA14 700
|
||||
MX51_PAD_EIM_DA15__EIM_DA15 701
|
||||
MX51_PAD_SD2_CMD__CSPI_MOSI 702
|
||||
MX51_PAD_SD2_CMD__I2C1_SCL 703
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 704
|
||||
MX51_PAD_SD2_CLK__CSPI_SCLK 705
|
||||
MX51_PAD_SD2_CLK__I2C1_SDA 706
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 707
|
||||
MX51_PAD_SD2_DATA0__CSPI_MISO 708
|
||||
MX51_PAD_SD2_DATA0__SD1_DAT4 709
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 710
|
||||
MX51_PAD_SD2_DATA1__SD1_DAT5 711
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 712
|
||||
MX51_PAD_SD2_DATA1__USBH3_H2_DP 713
|
||||
MX51_PAD_SD2_DATA2__SD1_DAT6 714
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 715
|
||||
MX51_PAD_SD2_DATA2__USBH3_H2_DM 716
|
||||
MX51_PAD_SD2_DATA3__CSPI_SS2 717
|
||||
MX51_PAD_SD2_DATA3__SD1_DAT7 718
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 719
|
||||
MX51_PAD_GPIO1_2__CCM_OUT_2 720
|
||||
MX51_PAD_GPIO1_2__GPIO1_2 721
|
||||
MX51_PAD_GPIO1_2__I2C2_SCL 722
|
||||
MX51_PAD_GPIO1_2__PLL1_BYP 723
|
||||
MX51_PAD_GPIO1_2__PWM1_PWMO 724
|
||||
MX51_PAD_GPIO1_3__GPIO1_3 725
|
||||
MX51_PAD_GPIO1_3__I2C2_SDA 726
|
||||
MX51_PAD_GPIO1_3__PLL2_BYP 727
|
||||
MX51_PAD_GPIO1_3__PWM2_PWMO 728
|
||||
MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 729
|
||||
MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 730
|
||||
MX51_PAD_GPIO1_4__DISP2_EXT_CLK 731
|
||||
MX51_PAD_GPIO1_4__EIM_RDY 732
|
||||
MX51_PAD_GPIO1_4__GPIO1_4 733
|
||||
MX51_PAD_GPIO1_4__WDOG1_WDOG_B 734
|
||||
MX51_PAD_GPIO1_5__CSI2_MCLK 735
|
||||
MX51_PAD_GPIO1_5__DISP2_PIN16 736
|
||||
MX51_PAD_GPIO1_5__GPIO1_5 737
|
||||
MX51_PAD_GPIO1_5__WDOG2_WDOG_B 738
|
||||
MX51_PAD_GPIO1_6__DISP2_PIN17 739
|
||||
MX51_PAD_GPIO1_6__GPIO1_6 740
|
||||
MX51_PAD_GPIO1_6__REF_EN_B 741
|
||||
MX51_PAD_GPIO1_7__CCM_OUT_0 742
|
||||
MX51_PAD_GPIO1_7__GPIO1_7 743
|
||||
MX51_PAD_GPIO1_7__SD2_WP 744
|
||||
MX51_PAD_GPIO1_7__SPDIF_OUT1 745
|
||||
MX51_PAD_GPIO1_8__CSI2_DATA_EN 746
|
||||
MX51_PAD_GPIO1_8__GPIO1_8 747
|
||||
MX51_PAD_GPIO1_8__SD2_CD 748
|
||||
MX51_PAD_GPIO1_8__USBH3_PWR 749
|
||||
MX51_PAD_GPIO1_9__CCM_OUT_1 750
|
||||
MX51_PAD_GPIO1_9__DISP2_D1_CS 751
|
||||
MX51_PAD_GPIO1_9__DISP2_SER_CS 752
|
||||
MX51_PAD_GPIO1_9__GPIO1_9 753
|
||||
MX51_PAD_GPIO1_9__SD2_LCTL 754
|
||||
MX51_PAD_GPIO1_9__USBH3_OC 755
|
||||
Refer to imx51-pinfunc.h in device tree source folder for all available
|
||||
imx51 PIN_FUNC_ID.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,38 @@
|
|||
* Freescale IMX6 DualLite/Solo IOMUX Controller
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
|
||||
and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx6dl-iomuxc"
|
||||
- fsl,pins: two integers array, represents a group of pins mux and config
|
||||
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
|
||||
pin working on a specific function, CONFIG is the pad setting value like
|
||||
pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
|
||||
config settings.
|
||||
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_HYS (1 << 16)
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 14)
|
||||
PAD_CTL_PUS_47K_UP (1 << 14)
|
||||
PAD_CTL_PUS_100K_UP (2 << 14)
|
||||
PAD_CTL_PUS_22K_UP (3 << 14)
|
||||
PAD_CTL_PUE (1 << 13)
|
||||
PAD_CTL_PKE (1 << 12)
|
||||
PAD_CTL_ODE (1 << 11)
|
||||
PAD_CTL_SPEED_LOW (1 << 6)
|
||||
PAD_CTL_SPEED_MED (2 << 6)
|
||||
PAD_CTL_SPEED_HIGH (3 << 6)
|
||||
PAD_CTL_DSE_DISABLE (0 << 3)
|
||||
PAD_CTL_DSE_240ohm (1 << 3)
|
||||
PAD_CTL_DSE_120ohm (2 << 3)
|
||||
PAD_CTL_DSE_80ohm (3 << 3)
|
||||
PAD_CTL_DSE_60ohm (4 << 3)
|
||||
PAD_CTL_DSE_48ohm (5 << 3)
|
||||
PAD_CTL_DSE_40ohm (6 << 3)
|
||||
PAD_CTL_DSE_34ohm (7 << 3)
|
||||
PAD_CTL_SRE_FAST (1 << 0)
|
||||
PAD_CTL_SRE_SLOW (0 << 0)
|
||||
|
||||
Refer to imx6dl-pinfunc.h in device tree source folder for all available
|
||||
imx6dl PIN_FUNC_ID.
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,39 @@
|
|||
* Freescale IMX6 SoloLite IOMUX Controller
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
|
||||
and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx6sl-iomuxc"
|
||||
- fsl,pins: two integers array, represents a group of pins mux and config
|
||||
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
|
||||
pin working on a specific function, CONFIG is the pad setting value like
|
||||
pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
|
||||
config settings.
|
||||
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_LVE (1 << 22)
|
||||
PAD_CTL_HYS (1 << 16)
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 14)
|
||||
PAD_CTL_PUS_47K_UP (1 << 14)
|
||||
PAD_CTL_PUS_100K_UP (2 << 14)
|
||||
PAD_CTL_PUS_22K_UP (3 << 14)
|
||||
PAD_CTL_PUE (1 << 13)
|
||||
PAD_CTL_PKE (1 << 12)
|
||||
PAD_CTL_ODE (1 << 11)
|
||||
PAD_CTL_SPEED_LOW (1 << 6)
|
||||
PAD_CTL_SPEED_MED (2 << 6)
|
||||
PAD_CTL_SPEED_HIGH (3 << 6)
|
||||
PAD_CTL_DSE_DISABLE (0 << 3)
|
||||
PAD_CTL_DSE_240ohm (1 << 3)
|
||||
PAD_CTL_DSE_120ohm (2 << 3)
|
||||
PAD_CTL_DSE_80ohm (3 << 3)
|
||||
PAD_CTL_DSE_60ohm (4 << 3)
|
||||
PAD_CTL_DSE_48ohm (5 << 3)
|
||||
PAD_CTL_DSE_40ohm (6 << 3)
|
||||
PAD_CTL_DSE_34ohm (7 << 3)
|
||||
PAD_CTL_SRE_FAST (1 << 0)
|
||||
PAD_CTL_SRE_SLOW (0 << 0)
|
||||
|
||||
Refer to imx6sl-pinfunc.h in device tree source folder for all available
|
||||
imx6sl PIN_FUNC_ID.
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
Freescale i.MX General Purpose Timer (GPT)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "fsl,<soc>-gpt"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A list of 4 interrupts; one per timer channel.
|
||||
- clocks : The clocks provided by the SoC to drive the timer.
|
||||
|
||||
Example:
|
||||
|
||||
gpt1: timer@10003000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10003000 0x1000>;
|
||||
interrupts = <26>;
|
||||
clocks = <&clks 46>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
|
@ -23,7 +23,7 @@ Supported chips:
|
|||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/
|
||||
* Microchip (TelCom) TCN75
|
||||
Prefix: 'lm75'
|
||||
Prefix: 'tcn75'
|
||||
Addresses scanned: none
|
||||
Datasheet: Publicly available at the Microchip website
|
||||
http://www.microchip.com/
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ Supported adapters:
|
|||
Documentation:
|
||||
http://www.diolan.com/i2c/u2c12.html
|
||||
|
||||
Author: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
Author: Guenter Roeck <linux@roeck-us.net>
|
||||
|
||||
Description
|
||||
-----------
|
||||
|
|
|
|||
|
|
@ -15,6 +15,13 @@ amemthresh - INTEGER
|
|||
enabled and the variable is automatically set to 2, otherwise
|
||||
the strategy is disabled and the variable is set to 1.
|
||||
|
||||
backup_only - BOOLEAN
|
||||
0 - disabled (default)
|
||||
not 0 - enabled
|
||||
|
||||
If set, disable the director function while the server is
|
||||
in backup mode to avoid packet loops for DR/TUN methods.
|
||||
|
||||
conntrack - BOOLEAN
|
||||
0 - disabled (default)
|
||||
not 0 - enabled
|
||||
|
|
|
|||
|
|
@ -912,7 +912,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
|
|||
models depending on the codec chip. The list of available models
|
||||
is found in HD-Audio-Models.txt
|
||||
|
||||
The model name "genric" is treated as a special case. When this
|
||||
The model name "generic" is treated as a special case. When this
|
||||
model is given, the driver uses the generic codec parser without
|
||||
"codec-patch". It's sometimes good for testing and debugging.
|
||||
|
||||
|
|
|
|||
|
|
@ -285,7 +285,7 @@ sample data.
|
|||
<H4>
|
||||
7.2.4 Close Callback</H4>
|
||||
The <TT>close</TT> callback is called when this device is closed by the
|
||||
applicaion. If any private data was allocated in open callback, it must
|
||||
application. If any private data was allocated in open callback, it must
|
||||
be released in the close callback. The deletion of ALSA port should be
|
||||
done here, too. This callback must not be NULL.
|
||||
<H4>
|
||||
|
|
|
|||
56
MAINTAINERS
56
MAINTAINERS
|
|
@ -1338,12 +1338,6 @@ S: Maintained
|
|||
F: drivers/platform/x86/asus*.c
|
||||
F: drivers/platform/x86/eeepc*.c
|
||||
|
||||
ASUS ASB100 HARDWARE MONITOR DRIVER
|
||||
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
S: Maintained
|
||||
F: drivers/hwmon/asb100.c
|
||||
|
||||
ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API
|
||||
M: Dan Williams <djbw@fb.com>
|
||||
W: http://sourceforge.net/projects/xscaleiop
|
||||
|
|
@ -1467,6 +1461,12 @@ F: drivers/dma/at_hdmac.c
|
|||
F: drivers/dma/at_hdmac_regs.h
|
||||
F: include/linux/platform_data/dma-atmel.h
|
||||
|
||||
ATMEL I2C DRIVER
|
||||
M: Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/i2c/busses/i2c-at91.c
|
||||
|
||||
ATMEL ISI DRIVER
|
||||
M: Josh Wu <josh.wu@atmel.com>
|
||||
L: linux-media@vger.kernel.org
|
||||
|
|
@ -2629,7 +2629,7 @@ F: include/uapi/drm/
|
|||
|
||||
INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
|
||||
M: Daniel Vetter <daniel.vetter@ffwll.ch>
|
||||
L: intel-gfx@lists.freedesktop.org (subscribers-only)
|
||||
L: intel-gfx@lists.freedesktop.org
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
T: git git://people.freedesktop.org/~danvet/drm-intel
|
||||
S: Supported
|
||||
|
|
@ -3242,6 +3242,12 @@ F: Documentation/firmware_class/
|
|||
F: drivers/base/firmware*.c
|
||||
F: include/linux/firmware.h
|
||||
|
||||
FLASHSYSTEM DRIVER (IBM FlashSystem 70/80 PCI SSD Flash Card)
|
||||
M: Joshua Morris <josh.h.morris@us.ibm.com>
|
||||
M: Philip Kelleher <pjk1939@linux.vnet.ibm.com>
|
||||
S: Maintained
|
||||
F: drivers/block/rsxx/
|
||||
|
||||
FLOPPY DRIVER
|
||||
M: Jiri Kosina <jkosina@suse.cz>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/floppy.git
|
||||
|
|
@ -3851,7 +3857,7 @@ F: drivers/i2c/busses/i2c-ismt.c
|
|||
F: Documentation/i2c/busses/i2c-ismt
|
||||
|
||||
I2C/SMBUS STUB DRIVER
|
||||
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
|
||||
M: Jean Delvare <khali@linux-fr.org>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/i2c/i2c-stub.c
|
||||
|
|
@ -5647,6 +5653,14 @@ S: Maintained
|
|||
F: drivers/video/riva/
|
||||
F: drivers/video/nvidia/
|
||||
|
||||
NVM EXPRESS DRIVER
|
||||
M: Matthew Wilcox <willy@linux.intel.com>
|
||||
L: linux-nvme@lists.infradead.org
|
||||
T: git git://git.infradead.org/users/willy/linux-nvme.git
|
||||
S: Supported
|
||||
F: drivers/block/nvme.c
|
||||
F: include/linux/nvme.h
|
||||
|
||||
OMAP SUPPORT
|
||||
M: Tony Lindgren <tony@atomide.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
|
|
@ -5675,7 +5689,7 @@ S: Maintained
|
|||
F: arch/arm/*omap*/*clock*
|
||||
|
||||
OMAP POWER MANAGEMENT SUPPORT
|
||||
M: Kevin Hilman <khilman@ti.com>
|
||||
M: Kevin Hilman <khilman@deeprootsystems.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
F: arch/arm/*omap*/*pm*
|
||||
|
|
@ -5769,7 +5783,7 @@ F: arch/arm/*omap*/usb*
|
|||
|
||||
OMAP GPIO DRIVER
|
||||
M: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
M: Kevin Hilman <khilman@ti.com>
|
||||
M: Kevin Hilman <khilman@deeprootsystems.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/gpio/gpio-omap.c
|
||||
|
|
@ -6201,7 +6215,7 @@ F: include/linux/power_supply.h
|
|||
F: drivers/power/
|
||||
|
||||
PNP SUPPORT
|
||||
M: Adam Belay <abelay@mit.edu>
|
||||
M: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
|
||||
M: Bjorn Helgaas <bhelgaas@google.com>
|
||||
S: Maintained
|
||||
F: drivers/pnp/
|
||||
|
|
@ -6543,12 +6557,6 @@ S: Maintained
|
|||
F: Documentation/blockdev/ramdisk.txt
|
||||
F: drivers/block/brd.c
|
||||
|
||||
RAMSAM DRIVER (IBM RamSan 70/80 PCI SSD Flash Card)
|
||||
M: Joshua Morris <josh.h.morris@us.ibm.com>
|
||||
M: Philip Kelleher <pjk1939@linux.vnet.ibm.com>
|
||||
S: Maintained
|
||||
F: drivers/block/rsxx/
|
||||
|
||||
RANDOM NUMBER DRIVER
|
||||
M: Theodore Ts'o" <tytso@mit.edu>
|
||||
S: Maintained
|
||||
|
|
@ -7165,7 +7173,7 @@ F: arch/arm/mach-s3c2410/bast-irq.c
|
|||
|
||||
TI DAVINCI MACHINE SUPPORT
|
||||
M: Sekhar Nori <nsekhar@ti.com>
|
||||
M: Kevin Hilman <khilman@ti.com>
|
||||
M: Kevin Hilman <khilman@deeprootsystems.com>
|
||||
L: davinci-linux-open-source@linux.davincidsp.com (moderated for non-subscribers)
|
||||
T: git git://gitorious.org/linux-davinci/linux-davinci.git
|
||||
Q: http://patchwork.kernel.org/project/linux-davinci/list/
|
||||
|
|
@ -7198,13 +7206,6 @@ L: netdev@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/net/ethernet/sis/sis900.*
|
||||
|
||||
SIS 96X I2C/SMBUS DRIVER
|
||||
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/i2c/busses/i2c-sis96x
|
||||
F: drivers/i2c/busses/i2c-sis96x.c
|
||||
|
||||
SIS FRAMEBUFFER DRIVER
|
||||
M: Thomas Winischhofer <thomas@winischhofer.net>
|
||||
W: http://www.winischhofer.net/linuxsisvga.shtml
|
||||
|
|
@ -7282,7 +7283,7 @@ F: Documentation/hwmon/sch5627
|
|||
F: drivers/hwmon/sch5627.c
|
||||
|
||||
SMSC47B397 HARDWARE MONITOR DRIVER
|
||||
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
|
||||
M: Jean Delvare <khali@linux-fr.org>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
S: Maintained
|
||||
F: Documentation/hwmon/smsc47b397
|
||||
|
|
@ -7705,9 +7706,10 @@ F: include/linux/swiotlb.h
|
|||
|
||||
SYNOPSYS ARC ARCHITECTURE
|
||||
M: Vineet Gupta <vgupta@synopsys.com>
|
||||
L: linux-snps-arc@vger.kernel.org
|
||||
S: Supported
|
||||
F: arch/arc/
|
||||
F: Documentation/devicetree/bindings/arc/
|
||||
F: drivers/tty/serial/arc-uart.c
|
||||
|
||||
SYSV FILESYSTEM
|
||||
M: Christoph Hellwig <hch@infradead.org>
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 9
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Unicycling Gorilla
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@ dma_map_sg(struct device *dev, struct scatterlist *sg,
|
|||
int i;
|
||||
|
||||
for_each_sg(sg, s, nents, i)
|
||||
sg->dma_address = dma_map_page(dev, sg_page(s), s->offset,
|
||||
s->dma_address = dma_map_page(dev, sg_page(s), s->offset,
|
||||
s->length, dir);
|
||||
|
||||
return nents;
|
||||
|
|
|
|||
|
|
@ -72,7 +72,4 @@ extern int elf_check_arch(const struct elf32_hdr *);
|
|||
*/
|
||||
#define ELF_PLATFORM (NULL)
|
||||
|
||||
#define SET_PERSONALITY(ex) \
|
||||
set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -415,7 +415,7 @@
|
|||
*-------------------------------------------------------------*/
|
||||
.macro SAVE_ALL_EXCEPTION marker
|
||||
|
||||
st \marker, [sp, 8]
|
||||
st \marker, [sp, 8] /* orig_r8 */
|
||||
st r0, [sp, 4] /* orig_r0, needed only for sys calls */
|
||||
|
||||
/* Restore r9 used to code the early prologue */
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
#ifdef CONFIG_KGDB
|
||||
|
||||
#include <asm/user.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
/* to ensure compatibility with Linux 2.6.35, we don't implement the get/set
|
||||
* register API yet */
|
||||
|
|
@ -53,9 +53,7 @@ enum arc700_linux_regnums {
|
|||
};
|
||||
|
||||
#else
|
||||
static inline void kgdb_trap(struct pt_regs *regs, int param)
|
||||
{
|
||||
}
|
||||
#define kgdb_trap(regs, param)
|
||||
#endif
|
||||
|
||||
#endif /* __ARC_KGDB_H__ */
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@ static inline long regs_return_value(struct pt_regs *regs)
|
|||
#define orig_r8_IS_SCALL 0x0001
|
||||
#define orig_r8_IS_SCALL_RESTARTED 0x0002
|
||||
#define orig_r8_IS_BRKPT 0x0004
|
||||
#define orig_r8_IS_EXCPN 0x0004
|
||||
#define orig_r8_IS_EXCPN 0x0008
|
||||
#define orig_r8_IS_IRQ1 0x0010
|
||||
#define orig_r8_IS_IRQ2 0x0020
|
||||
|
||||
|
|
|
|||
|
|
@ -16,8 +16,6 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
int sys_clone_wrapper(int, int, int, int, int);
|
||||
int sys_fork_wrapper(void);
|
||||
int sys_vfork_wrapper(void);
|
||||
int sys_cacheflush(uint32_t, uint32_t uint32_t);
|
||||
int sys_arc_settls(void *);
|
||||
int sys_arc_gettls(void);
|
||||
|
|
|
|||
|
|
@ -28,14 +28,14 @@
|
|||
*/
|
||||
struct user_regs_struct {
|
||||
|
||||
struct scratch {
|
||||
struct {
|
||||
long pad;
|
||||
long bta, lp_start, lp_end, lp_count;
|
||||
long status32, ret, blink, fp, gp;
|
||||
long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;
|
||||
long sp;
|
||||
} scratch;
|
||||
struct callee {
|
||||
struct {
|
||||
long pad;
|
||||
long r25, r24, r23, r22, r21, r20;
|
||||
long r19, r18, r17, r16, r15, r14, r13;
|
||||
|
|
|
|||
|
|
@ -452,7 +452,7 @@ tracesys:
|
|||
; using ERET won't work since next-PC has already committed
|
||||
lr r12, [efa]
|
||||
GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11
|
||||
st r12, [r11, THREAD_FAULT_ADDR]
|
||||
st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address
|
||||
|
||||
; PRE Sys Call Ptrace hook
|
||||
mov r0, sp ; pt_regs needed
|
||||
|
|
@ -792,31 +792,6 @@ ARC_EXIT ret_from_fork
|
|||
|
||||
;################### Special Sys Call Wrappers ##########################
|
||||
|
||||
; TBD: call do_fork directly from here
|
||||
ARC_ENTRY sys_fork_wrapper
|
||||
SAVE_CALLEE_SAVED_USER
|
||||
bl @sys_fork
|
||||
DISCARD_CALLEE_SAVED_USER
|
||||
|
||||
GET_CURR_THR_INFO_FLAGS r10
|
||||
btst r10, TIF_SYSCALL_TRACE
|
||||
bnz tracesys_exit
|
||||
|
||||
b ret_from_system_call
|
||||
ARC_EXIT sys_fork_wrapper
|
||||
|
||||
ARC_ENTRY sys_vfork_wrapper
|
||||
SAVE_CALLEE_SAVED_USER
|
||||
bl @sys_vfork
|
||||
DISCARD_CALLEE_SAVED_USER
|
||||
|
||||
GET_CURR_THR_INFO_FLAGS r10
|
||||
btst r10, TIF_SYSCALL_TRACE
|
||||
bnz tracesys_exit
|
||||
|
||||
b ret_from_system_call
|
||||
ARC_EXIT sys_vfork_wrapper
|
||||
|
||||
ARC_ENTRY sys_clone_wrapper
|
||||
SAVE_CALLEE_SAVED_USER
|
||||
bl @sys_clone
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/kgdb.h>
|
||||
#include <linux/sched.h>
|
||||
#include <asm/disasm.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -232,10 +232,8 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
|
|||
|
||||
n += scnprintf(buf + n, len - n, "\n");
|
||||
|
||||
#ifdef _ASM_GENERIC_UNISTD_H
|
||||
n += scnprintf(buf + n, len - n,
|
||||
"OS ABI [v2]\t: asm-generic/{unistd,stat,fcntl}\n");
|
||||
#endif
|
||||
"OS ABI [v3]\t: no-legacy-syscalls\n");
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,8 +6,6 @@
|
|||
#include <asm/syscalls.h>
|
||||
|
||||
#define sys_clone sys_clone_wrapper
|
||||
#define sys_fork sys_fork_wrapper
|
||||
#define sys_vfork sys_vfork_wrapper
|
||||
|
||||
#undef __SYSCALL
|
||||
#define __SYSCALL(nr, call) [nr] = (call),
|
||||
|
|
|
|||
|
|
@ -49,7 +49,6 @@ config ARM
|
|||
select HAVE_REGS_AND_STACK_ACCESS_API
|
||||
select HAVE_SYSCALL_TRACEPOINTS
|
||||
select HAVE_UID16
|
||||
select VIRT_TO_BUS
|
||||
select KTIME_SCALAR
|
||||
select PERF_USE_VMALLOC
|
||||
select RTC_LIB
|
||||
|
|
@ -743,6 +742,7 @@ config ARCH_RPC
|
|||
select NEED_MACH_IO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
select NO_IOPORT
|
||||
select VIRT_TO_BUS
|
||||
help
|
||||
On the Acorn Risc-PC, Linux can support the internal IDE disk and
|
||||
CD-ROM interface, serial and parallel port, and the floppy drive.
|
||||
|
|
@ -878,6 +878,7 @@ config ARCH_SHARK
|
|||
select ISA_DMA
|
||||
select NEED_MACH_MEMORY_H
|
||||
select PCI
|
||||
select VIRT_TO_BUS
|
||||
select ZONE_DMA
|
||||
help
|
||||
Support for the StrongARM based Digital DNARD machine, also known
|
||||
|
|
@ -1005,12 +1006,12 @@ config ARCH_MULTI_V4_V5
|
|||
bool
|
||||
|
||||
config ARCH_MULTI_V6
|
||||
bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
|
||||
bool "ARMv6 based platforms (ARM11)"
|
||||
select ARCH_MULTI_V6_V7
|
||||
select CPU_V6
|
||||
|
||||
config ARCH_MULTI_V7
|
||||
bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
|
||||
bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
|
||||
default y
|
||||
select ARCH_MULTI_V6_V7
|
||||
select ARCH_VEXPRESS
|
||||
|
|
@ -1461,10 +1462,6 @@ config ISA_DMA
|
|||
bool
|
||||
select ISA_DMA_API
|
||||
|
||||
config ARCH_NO_VIRT_TO_BUS
|
||||
def_bool y
|
||||
depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
|
||||
|
||||
# Select ISA DMA interface
|
||||
config ISA_DMA_API
|
||||
bool
|
||||
|
|
@ -2156,13 +2153,6 @@ if ARCH_HAS_CPUFREQ
|
|||
|
||||
source "drivers/cpufreq/Kconfig"
|
||||
|
||||
config CPU_FREQ_IMX
|
||||
tristate "CPUfreq driver for i.MX CPUs"
|
||||
depends on ARCH_MXC && CPU_FREQ
|
||||
select CPU_FREQ_TABLE
|
||||
help
|
||||
This enables the CPUfreq driver for i.MX CPUs.
|
||||
|
||||
config CPU_FREQ_SA1100
|
||||
bool
|
||||
|
||||
|
|
|
|||
|
|
@ -495,6 +495,7 @@ config DEBUG_IMX_UART_PORT
|
|||
DEBUG_IMX53_UART || \
|
||||
DEBUG_IMX6Q_UART
|
||||
default 1
|
||||
depends on ARCH_MXC
|
||||
help
|
||||
Choose UART port on which kernel low-level debug messages
|
||||
should be output.
|
||||
|
|
|
|||
|
|
@ -89,19 +89,26 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|||
imx25-karo-tx25.dtb \
|
||||
imx25-pdk.dtb \
|
||||
imx27-apf27.dtb \
|
||||
imx27-apf27dev.dtb \
|
||||
imx27-pdk.dtb \
|
||||
imx27-phytec-phycore.dtb \
|
||||
imx31-bug.dtb \
|
||||
imx51-apf51.dtb \
|
||||
imx51-apf51dev.dtb \
|
||||
imx51-babbage.dtb \
|
||||
imx53-ard.dtb \
|
||||
imx53-evk.dtb \
|
||||
imx53-mba53.dtb \
|
||||
imx53-qsb.dtb \
|
||||
imx53-smd.dtb \
|
||||
imx6dl-sabreauto.dtb \
|
||||
imx6dl-sabresd.dtb \
|
||||
imx6dl-wandboard.dtb \
|
||||
imx6q-arm2.dtb \
|
||||
imx6q-sabreauto.dtb \
|
||||
imx6q-sabrelite.dtb \
|
||||
imx6q-sabresd.dtb
|
||||
imx6q-sabresd.dtb \
|
||||
imx6q-sbc6x.dtb
|
||||
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
|
||||
imx23-olinuxino.dtb \
|
||||
imx23-stmp378x_devb.dtb \
|
||||
|
|
|
|||
|
|
@ -238,8 +238,32 @@
|
|||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
|
||||
3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
|
||||
<3 0 0x1 0x0 /* PD0 periph A Read Enable */
|
||||
3 1 0x1 0x0 /* PD1 periph A Write Enable */
|
||||
3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */
|
||||
3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */
|
||||
3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */
|
||||
3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */
|
||||
3 6 0x1 0x0 /* PD6 periph A Data bit 0 */
|
||||
3 7 0x1 0x0 /* PD7 periph A Data bit 1 */
|
||||
3 8 0x1 0x0 /* PD8 periph A Data bit 2 */
|
||||
3 9 0x1 0x0 /* PD9 periph A Data bit 3 */
|
||||
3 10 0x1 0x0 /* PD10 periph A Data bit 4 */
|
||||
3 11 0x1 0x0 /* PD11 periph A Data bit 5 */
|
||||
3 12 0x1 0x0 /* PD12 periph A Data bit 6 */
|
||||
3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
|
||||
};
|
||||
|
||||
pinctrl_nand_16bits: nand_16bits-0 {
|
||||
atmel,pins =
|
||||
<3 14 0x1 0x0 /* PD14 periph A Data bit 8 */
|
||||
3 15 0x1 0x0 /* PD15 periph A Data bit 9 */
|
||||
3 16 0x1 0x0 /* PD16 periph A Data bit 10 */
|
||||
3 17 0x1 0x0 /* PD17 periph A Data bit 11 */
|
||||
3 18 0x1 0x0 /* PD18 periph A Data bit 12 */
|
||||
3 19 0x1 0x0 /* PD19 periph A Data bit 13 */
|
||||
3 20 0x1 0x0 /* PD20 periph A Data bit 14 */
|
||||
3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -275,18 +275,27 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12680000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
|
||||
pdma1: pdma@12690000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12690000 0x1000>;
|
||||
interrupts = <0 36 0>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
|
||||
mdma1: mdma@12850000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x12850000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -142,12 +142,18 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x120000 0x1000>;
|
||||
interrupts = <0 34 0>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
|
||||
pdma1: pdma@121B0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x121000 0x1000>;
|
||||
interrupts = <0 35 0>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx25.dtsi"
|
||||
#include "imx25.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro TX25";
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx25.dtsi"
|
||||
#include "imx25.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX25 Product Development Kit";
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx27.dtsi"
|
||||
#include "imx27.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Armadeus Systems APF27 module";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright 2013 Armadeus Systems - <support@armadeus.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/* APF27Dev is a docking board for the APF27 SOM */
|
||||
#include "imx27-apf27.dts"
|
||||
|
||||
/ {
|
||||
model = "Armadeus Systems APF27Dev docking/development board";
|
||||
compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27";
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
user-key {
|
||||
label = "user";
|
||||
gpios = <&gpio6 13 0>;
|
||||
linux,code = <276>; /* BTN_EXTRA */
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio6 14 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 28 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cspi2 {
|
||||
fsl,spi-num-chipselects = <3>;
|
||||
cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>,
|
||||
<&gpio2 17 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx27.dtsi"
|
||||
#include "imx27.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX27 Product Development Kit";
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx27.dtsi"
|
||||
#include "imx27.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Phytec pcm038";
|
||||
|
|
@ -71,3 +71,9 @@
|
|||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -60,14 +60,41 @@
|
|||
|
||||
wdog: wdog@10002000 {
|
||||
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x10002000 0x4000>;
|
||||
reg = <0x10002000 0x1000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&clks 0>;
|
||||
};
|
||||
|
||||
gpt1: timer@10003000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10003000 0x1000>;
|
||||
interrupts = <26>;
|
||||
clocks = <&clks 46>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpt2: timer@10004000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10004000 0x1000>;
|
||||
interrupts = <25>;
|
||||
clocks = <&clks 45>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpt3: timer@10005000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10005000 0x1000>;
|
||||
interrupts = <24>;
|
||||
clocks = <&clks 44>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks 81>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -75,6 +102,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000b000 0x1000>;
|
||||
interrupts = <19>;
|
||||
clocks = <&clks 80>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -82,6 +111,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000c000 0x1000>;
|
||||
interrupts = <18>;
|
||||
clocks = <&clks 79>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -89,6 +120,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks 78>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -98,6 +131,8 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x1000e000 0x1000>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks 53>, <&clks 0>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -107,6 +142,8 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x1000f000 0x1000>;
|
||||
interrupts = <15>;
|
||||
clocks = <&clks 52>, <&clks 0>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -116,6 +153,7 @@
|
|||
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x10012000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&clks 40>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -185,13 +223,33 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x10017000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks 51>, <&clks 0>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt4: timer@10019000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x10019000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clks 43>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpt5: timer@1001a000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x1001a000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clks 42>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
uart5: serial@1001b000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1001b000 0x1000>;
|
||||
interrupts = <49>;
|
||||
clocks = <&clks 77>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -199,6 +257,8 @@
|
|||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1001c000 0x1000>;
|
||||
interrupts = <48>;
|
||||
clocks = <&clks 78>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -208,9 +268,17 @@
|
|||
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x1001d000 0x1000>;
|
||||
interrupts = <1>;
|
||||
clocks = <&clks 39>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt6: timer@1001f000 {
|
||||
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
|
||||
reg = <0x1001f000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&clks 41>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
};
|
||||
|
||||
aipi@10020000 { /* AIPI2 */
|
||||
|
|
@ -224,10 +292,19 @@
|
|||
compatible = "fsl,imx27-fec";
|
||||
reg = <0x1002b000 0x4000>;
|
||||
interrupts = <50>;
|
||||
clocks = <&clks 48>, <&clks 67>, <&clks 0>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
nfc: nand@d8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -235,6 +312,7 @@
|
|||
compatible = "fsl,imx27-nand";
|
||||
reg = <0xd8000000 0x1000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 54>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx31.dtsi"
|
||||
#include "imx31.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Buglabs i.MX31 Bug 1.x";
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -101,5 +101,21 @@
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aips@53f00000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x53f00000 0x100000>;
|
||||
ranges;
|
||||
|
||||
gpt: timer@53f90000 {
|
||||
compatible = "fsl,imx31-gpt";
|
||||
reg = <0x53f90000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 10>, <&clks 22>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,970 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX35_PINFUNC_H
|
||||
#define __DTS_IMX35_PINFUNC_H
|
||||
|
||||
/*
|
||||
* The pin function ID is a tuple of
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
#define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
|
||||
#define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
|
||||
#define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
|
||||
#define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
|
||||
#define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
|
||||
#define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
|
||||
#define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
|
||||
#define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
|
||||
#define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
|
||||
#define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
|
||||
#define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0
|
||||
#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x008 0x32c 0x000 0x7 0x0
|
||||
#define MX35_PAD_WDOG_RST__WDOG_WDOG_B 0x00c 0x330 0x000 0x0 0x0
|
||||
#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE 0x00c 0x330 0x000 0x3 0x0
|
||||
#define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0
|
||||
#define MX35_PAD_GPIO1_0__GPIO1_0 0x010 0x334 0x82c 0x0 0x0
|
||||
#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY 0x010 0x334 0x7d4 0x1 0x0
|
||||
#define MX35_PAD_GPIO1_0__OWIRE_LINE 0x010 0x334 0x990 0x2 0x0
|
||||
#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 0x010 0x334 0x000 0x7 0x0
|
||||
#define MX35_PAD_GPIO1_1__GPIO1_1 0x014 0x338 0x838 0x0 0x0
|
||||
#define MX35_PAD_GPIO1_1__PWM_PWMO 0x014 0x338 0x000 0x2 0x0
|
||||
#define MX35_PAD_GPIO1_1__CSPI1_SS2 0x014 0x338 0x7d8 0x3 0x0
|
||||
#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT 0x014 0x338 0x000 0x6 0x0
|
||||
#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 0x014 0x338 0x000 0x7 0x0
|
||||
#define MX35_PAD_GPIO2_0__GPIO2_0 0x018 0x33c 0x868 0x0 0x0
|
||||
#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK 0x018 0x33c 0x000 0x1 0x0
|
||||
#define MX35_PAD_GPIO3_0__GPIO3_0 0x01c 0x340 0x8e8 0x0 0x0
|
||||
#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK 0x01c 0x340 0x000 0x1 0x0
|
||||
#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B 0x000 0x344 0x000 0x0 0x0
|
||||
#define MX35_PAD_POR_B__CCM_POR_B 0x000 0x348 0x000 0x0 0x0
|
||||
#define MX35_PAD_CLKO__CCM_CLKO 0x020 0x34c 0x000 0x0 0x0
|
||||
#define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0
|
||||
#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 0x000 0x350 0x000 0x0 0x0
|
||||
#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 0x000 0x354 0x000 0x0 0x0
|
||||
#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 0x000 0x358 0x000 0x0 0x0
|
||||
#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 0x000 0x35c 0x000 0x0 0x0
|
||||
#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 0x000 0x360 0x000 0x0 0x0
|
||||
#define MX35_PAD_VSTBY__CCM_VSTBY 0x024 0x364 0x000 0x0 0x0
|
||||
#define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0
|
||||
#define MX35_PAD_A0__EMI_EIM_DA_L_0 0x028 0x368 0x000 0x0 0x0
|
||||
#define MX35_PAD_A1__EMI_EIM_DA_L_1 0x02c 0x36c 0x000 0x0 0x0
|
||||
#define MX35_PAD_A2__EMI_EIM_DA_L_2 0x030 0x370 0x000 0x0 0x0
|
||||
#define MX35_PAD_A3__EMI_EIM_DA_L_3 0x034 0x374 0x000 0x0 0x0
|
||||
#define MX35_PAD_A4__EMI_EIM_DA_L_4 0x038 0x378 0x000 0x0 0x0
|
||||
#define MX35_PAD_A5__EMI_EIM_DA_L_5 0x03c 0x37c 0x000 0x0 0x0
|
||||
#define MX35_PAD_A6__EMI_EIM_DA_L_6 0x040 0x380 0x000 0x0 0x0
|
||||
#define MX35_PAD_A7__EMI_EIM_DA_L_7 0x044 0x384 0x000 0x0 0x0
|
||||
#define MX35_PAD_A8__EMI_EIM_DA_H_8 0x048 0x388 0x000 0x0 0x0
|
||||
#define MX35_PAD_A9__EMI_EIM_DA_H_9 0x04c 0x38c 0x000 0x0 0x0
|
||||
#define MX35_PAD_A10__EMI_EIM_DA_H_10 0x050 0x390 0x000 0x0 0x0
|
||||
#define MX35_PAD_MA10__EMI_MA10 0x054 0x394 0x000 0x0 0x0
|
||||
#define MX35_PAD_A11__EMI_EIM_DA_H_11 0x058 0x398 0x000 0x0 0x0
|
||||
#define MX35_PAD_A12__EMI_EIM_DA_H_12 0x05c 0x39c 0x000 0x0 0x0
|
||||
#define MX35_PAD_A13__EMI_EIM_DA_H_13 0x060 0x3a0 0x000 0x0 0x0
|
||||
#define MX35_PAD_A14__EMI_EIM_DA_H2_14 0x064 0x3a4 0x000 0x0 0x0
|
||||
#define MX35_PAD_A15__EMI_EIM_DA_H2_15 0x068 0x3a8 0x000 0x0 0x0
|
||||
#define MX35_PAD_A16__EMI_EIM_A_16 0x06c 0x3ac 0x000 0x0 0x0
|
||||
#define MX35_PAD_A17__EMI_EIM_A_17 0x070 0x3b0 0x000 0x0 0x0
|
||||
#define MX35_PAD_A18__EMI_EIM_A_18 0x074 0x3b4 0x000 0x0 0x0
|
||||
#define MX35_PAD_A19__EMI_EIM_A_19 0x078 0x3b8 0x000 0x0 0x0
|
||||
#define MX35_PAD_A20__EMI_EIM_A_20 0x07c 0x3bc 0x000 0x0 0x0
|
||||
#define MX35_PAD_A21__EMI_EIM_A_21 0x080 0x3c0 0x000 0x0 0x0
|
||||
#define MX35_PAD_A22__EMI_EIM_A_22 0x084 0x3c4 0x000 0x0 0x0
|
||||
#define MX35_PAD_A23__EMI_EIM_A_23 0x088 0x3c8 0x000 0x0 0x0
|
||||
#define MX35_PAD_A24__EMI_EIM_A_24 0x08c 0x3cc 0x000 0x0 0x0
|
||||
#define MX35_PAD_A25__EMI_EIM_A_25 0x090 0x3d0 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 0x000 0x3d4 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 0x000 0x3d8 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD0__EMI_DRAM_D_0 0x000 0x3dc 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD1__EMI_DRAM_D_1 0x000 0x3e0 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD2__EMI_DRAM_D_2 0x000 0x3e4 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD3__EMI_DRAM_D_3 0x000 0x3e8 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD4__EMI_DRAM_D_4 0x000 0x3ec 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD5__EMI_DRAM_D_5 0x000 0x3f0 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD6__EMI_DRAM_D_6 0x000 0x3f4 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD7__EMI_DRAM_D_7 0x000 0x3f8 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD8__EMI_DRAM_D_8 0x000 0x3fc 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD9__EMI_DRAM_D_9 0x000 0x400 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD10__EMI_DRAM_D_10 0x000 0x404 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD11__EMI_DRAM_D_11 0x000 0x408 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD12__EMI_DRAM_D_12 0x000 0x40c 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD13__EMI_DRAM_D_13 0x000 0x410 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD14__EMI_DRAM_D_14 0x000 0x414 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD15__EMI_DRAM_D_15 0x000 0x418 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD16__EMI_DRAM_D_16 0x000 0x41c 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD17__EMI_DRAM_D_17 0x000 0x420 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD18__EMI_DRAM_D_18 0x000 0x424 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD19__EMI_DRAM_D_19 0x000 0x428 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD20__EMI_DRAM_D_20 0x000 0x42c 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD21__EMI_DRAM_D_21 0x000 0x430 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD22__EMI_DRAM_D_22 0x000 0x434 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD23__EMI_DRAM_D_23 0x000 0x438 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD24__EMI_DRAM_D_24 0x000 0x43c 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD25__EMI_DRAM_D_25 0x000 0x440 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD26__EMI_DRAM_D_26 0x000 0x444 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD27__EMI_DRAM_D_27 0x000 0x448 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD28__EMI_DRAM_D_28 0x000 0x44c 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD29__EMI_DRAM_D_29 0x000 0x450 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD30__EMI_DRAM_D_30 0x000 0x454 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD31__EMI_DRAM_D_31 0x000 0x458 0x000 0x0 0x0
|
||||
#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 0x000 0x45c 0x000 0x0 0x0
|
||||
#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 0x000 0x460 0x000 0x0 0x0
|
||||
#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 0x000 0x464 0x000 0x0 0x0
|
||||
#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 0x000 0x468 0x000 0x0 0x0
|
||||
#define MX35_PAD_EB0__EMI_EIM_EB0_B 0x094 0x46c 0x000 0x0 0x0
|
||||
#define MX35_PAD_EB1__EMI_EIM_EB1_B 0x098 0x470 0x000 0x0 0x0
|
||||
#define MX35_PAD_OE__EMI_EIM_OE 0x09c 0x474 0x000 0x0 0x0
|
||||
#define MX35_PAD_CS0__EMI_EIM_CS0 0x0a0 0x478 0x000 0x0 0x0
|
||||
#define MX35_PAD_CS1__EMI_EIM_CS1 0x0a4 0x47c 0x000 0x0 0x0
|
||||
#define MX35_PAD_CS1__EMI_NANDF_CE3 0x0a4 0x47c 0x000 0x3 0x0
|
||||
#define MX35_PAD_CS2__EMI_EIM_CS2 0x0a8 0x480 0x000 0x0 0x0
|
||||
#define MX35_PAD_CS3__EMI_EIM_CS3 0x0ac 0x484 0x000 0x0 0x0
|
||||
#define MX35_PAD_CS4__EMI_EIM_CS4 0x0b0 0x488 0x000 0x0 0x0
|
||||
#define MX35_PAD_CS4__EMI_DTACK_B 0x0b0 0x488 0x800 0x1 0x0
|
||||
#define MX35_PAD_CS4__EMI_NANDF_CE1 0x0b0 0x488 0x000 0x3 0x0
|
||||
#define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0
|
||||
#define MX35_PAD_CS5__EMI_EIM_CS5 0x0b4 0x48c 0x000 0x0 0x0
|
||||
#define MX35_PAD_CS5__CSPI2_SS2 0x0b4 0x48c 0x7f8 0x1 0x0
|
||||
#define MX35_PAD_CS5__CSPI1_SS2 0x0b4 0x48c 0x7d8 0x2 0x1
|
||||
#define MX35_PAD_CS5__EMI_NANDF_CE2 0x0b4 0x48c 0x000 0x3 0x0
|
||||
#define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0
|
||||
#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 0x0b8 0x490 0x000 0x0 0x0
|
||||
#define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0
|
||||
#define MX35_PAD_ECB__EMI_EIM_ECB 0x000 0x494 0x000 0x0 0x0
|
||||
#define MX35_PAD_LBA__EMI_EIM_LBA 0x0bc 0x498 0x000 0x0 0x0
|
||||
#define MX35_PAD_BCLK__EMI_EIM_BCLK 0x0c0 0x49c 0x000 0x0 0x0
|
||||
#define MX35_PAD_RW__EMI_EIM_RW 0x0c4 0x4a0 0x000 0x0 0x0
|
||||
#define MX35_PAD_RAS__EMI_DRAM_RAS 0x000 0x4a4 0x000 0x0 0x0
|
||||
#define MX35_PAD_CAS__EMI_DRAM_CAS 0x000 0x4a8 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDWE__EMI_DRAM_SDWE 0x000 0x4ac 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 0x000 0x4b0 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 0x000 0x4b4 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK 0x000 0x4b8 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 0x000 0x4bc 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 0x000 0x4c0 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 0x000 0x4c4 0x000 0x0 0x0
|
||||
#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 0x000 0x4c8 0x000 0x0 0x0
|
||||
#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B 0x0c8 0x4cc 0x000 0x0 0x0
|
||||
#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 0x0c8 0x4cc 0x9d8 0x1 0x0
|
||||
#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC 0x0c8 0x4cc 0x924 0x2 0x0
|
||||
#define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0
|
||||
#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 0x0c8 0x4cc 0x000 0x7 0x0
|
||||
#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B 0x0cc 0x4d0 0x000 0x0 0x0
|
||||
#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR 0x0cc 0x4d0 0x9ec 0x1 0x0
|
||||
#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK 0x0cc 0x4d0 0x000 0x2 0x0
|
||||
#define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 0x0
|
||||
#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 0x0cc 0x4d0 0x000 0x7 0x0
|
||||
#define MX35_PAD_NFALE__EMI_NANDF_ALE 0x0d0 0x4d4 0x000 0x0 0x0
|
||||
#define MX35_PAD_NFALE__USB_TOP_USBH2_STP 0x0d0 0x4d4 0x000 0x1 0x0
|
||||
#define MX35_PAD_NFALE__IPU_DISPB_CS0 0x0d0 0x4d4 0x000 0x2 0x0
|
||||
#define MX35_PAD_NFALE__GPIO2_20 0x0d0 0x4d4 0x898 0x5 0x0
|
||||
#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 0x0d0 0x4d4 0x000 0x7 0x0
|
||||
#define MX35_PAD_NFCLE__EMI_NANDF_CLE 0x0d4 0x4d8 0x000 0x0 0x0
|
||||
#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT 0x0d4 0x4d8 0x9f0 0x1 0x0
|
||||
#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS 0x0d4 0x4d8 0x000 0x2 0x0
|
||||
#define MX35_PAD_NFCLE__GPIO2_21 0x0d4 0x4d8 0x89c 0x5 0x0
|
||||
#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 0x0d4 0x4d8 0x000 0x7 0x0
|
||||
#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B 0x0d8 0x4dc 0x000 0x0 0x0
|
||||
#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 0x0d8 0x4dc 0x9e8 0x1 0x0
|
||||
#define MX35_PAD_NFWP_B__IPU_DISPB_WR 0x0d8 0x4dc 0x000 0x2 0x0
|
||||
#define MX35_PAD_NFWP_B__GPIO2_22 0x0d8 0x4dc 0x8a0 0x5 0x0
|
||||
#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL 0x0d8 0x4dc 0x000 0x7 0x0
|
||||
#define MX35_PAD_NFRB__EMI_NANDF_RB 0x0dc 0x4e0 0x000 0x0 0x0
|
||||
#define MX35_PAD_NFRB__IPU_DISPB_RD 0x0dc 0x4e0 0x000 0x2 0x0
|
||||
#define MX35_PAD_NFRB__GPIO2_23 0x0dc 0x4e0 0x8a4 0x5 0x0
|
||||
#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK 0x0dc 0x4e0 0x000 0x7 0x0
|
||||
#define MX35_PAD_D15__EMI_EIM_D_15 0x000 0x4e4 0x000 0x0 0x0
|
||||
#define MX35_PAD_D14__EMI_EIM_D_14 0x000 0x4e8 0x000 0x0 0x0
|
||||
#define MX35_PAD_D13__EMI_EIM_D_13 0x000 0x4ec 0x000 0x0 0x0
|
||||
#define MX35_PAD_D12__EMI_EIM_D_12 0x000 0x4f0 0x000 0x0 0x0
|
||||
#define MX35_PAD_D11__EMI_EIM_D_11 0x000 0x4f4 0x000 0x0 0x0
|
||||
#define MX35_PAD_D10__EMI_EIM_D_10 0x000 0x4f8 0x000 0x0 0x0
|
||||
#define MX35_PAD_D9__EMI_EIM_D_9 0x000 0x4fc 0x000 0x0 0x0
|
||||
#define MX35_PAD_D8__EMI_EIM_D_8 0x000 0x500 0x000 0x0 0x0
|
||||
#define MX35_PAD_D7__EMI_EIM_D_7 0x000 0x504 0x000 0x0 0x0
|
||||
#define MX35_PAD_D6__EMI_EIM_D_6 0x000 0x508 0x000 0x0 0x0
|
||||
#define MX35_PAD_D5__EMI_EIM_D_5 0x000 0x50c 0x000 0x0 0x0
|
||||
#define MX35_PAD_D4__EMI_EIM_D_4 0x000 0x510 0x000 0x0 0x0
|
||||
#define MX35_PAD_D3__EMI_EIM_D_3 0x000 0x514 0x000 0x0 0x0
|
||||
#define MX35_PAD_D2__EMI_EIM_D_2 0x000 0x518 0x000 0x0 0x0
|
||||
#define MX35_PAD_D1__EMI_EIM_D_1 0x000 0x51c 0x000 0x0 0x0
|
||||
#define MX35_PAD_D0__EMI_EIM_D_0 0x000 0x520 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_D8__IPU_CSI_D_8 0x0e0 0x524 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_D8__KPP_COL_0 0x0e0 0x524 0x950 0x1 0x0
|
||||
#define MX35_PAD_CSI_D8__GPIO1_20 0x0e0 0x524 0x83c 0x5 0x1
|
||||
#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 0x0e0 0x524 0x000 0x7 0x0
|
||||
#define MX35_PAD_CSI_D9__IPU_CSI_D_9 0x0e4 0x528 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_D9__KPP_COL_1 0x0e4 0x528 0x954 0x1 0x0
|
||||
#define MX35_PAD_CSI_D9__GPIO1_21 0x0e4 0x528 0x840 0x5 0x1
|
||||
#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 0x0e4 0x528 0x000 0x7 0x0
|
||||
#define MX35_PAD_CSI_D10__IPU_CSI_D_10 0x0e8 0x52c 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_D10__KPP_COL_2 0x0e8 0x52c 0x958 0x1 0x0
|
||||
#define MX35_PAD_CSI_D10__GPIO1_22 0x0e8 0x52c 0x844 0x5 0x1
|
||||
#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 0x0e8 0x52c 0x000 0x7 0x0
|
||||
#define MX35_PAD_CSI_D11__IPU_CSI_D_11 0x0ec 0x530 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_D11__KPP_COL_3 0x0ec 0x530 0x95c 0x1 0x0
|
||||
#define MX35_PAD_CSI_D11__GPIO1_23 0x0ec 0x530 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSI_D12__IPU_CSI_D_12 0x0f0 0x534 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_D12__KPP_ROW_0 0x0f0 0x534 0x970 0x1 0x0
|
||||
#define MX35_PAD_CSI_D12__GPIO1_24 0x0f0 0x534 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSI_D13__IPU_CSI_D_13 0x0f4 0x538 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_D13__KPP_ROW_1 0x0f4 0x538 0x974 0x1 0x0
|
||||
#define MX35_PAD_CSI_D13__GPIO1_25 0x0f4 0x538 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSI_D14__IPU_CSI_D_14 0x0f8 0x53c 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_D14__KPP_ROW_2 0x0f8 0x53c 0x978 0x1 0x0
|
||||
#define MX35_PAD_CSI_D14__GPIO1_26 0x0f8 0x53c 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSI_D15__IPU_CSI_D_15 0x0fc 0x540 0x97c 0x0 0x0
|
||||
#define MX35_PAD_CSI_D15__KPP_ROW_3 0x0fc 0x540 0x000 0x1 0x0
|
||||
#define MX35_PAD_CSI_D15__GPIO1_27 0x0fc 0x540 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK 0x100 0x544 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_MCLK__GPIO1_28 0x100 0x544 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC 0x104 0x548 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_VSYNC__GPIO1_29 0x104 0x548 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC 0x108 0x54c 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_HSYNC__GPIO1_30 0x108 0x54c 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK 0x10c 0x550 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSI_PIXCLK__GPIO1_31 0x10c 0x550 0x000 0x5 0x0
|
||||
#define MX35_PAD_I2C1_CLK__I2C1_SCL 0x110 0x554 0x000 0x0 0x0
|
||||
#define MX35_PAD_I2C1_CLK__GPIO2_24 0x110 0x554 0x8a8 0x5 0x0
|
||||
#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK 0x110 0x554 0x000 0x6 0x0
|
||||
#define MX35_PAD_I2C1_DAT__I2C1_SDA 0x114 0x558 0x000 0x0 0x0
|
||||
#define MX35_PAD_I2C1_DAT__GPIO2_25 0x114 0x558 0x8ac 0x5 0x0
|
||||
#define MX35_PAD_I2C2_CLK__I2C2_SCL 0x118 0x55c 0x000 0x0 0x0
|
||||
#define MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x118 0x55c 0x000 0x1 0x0
|
||||
#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR 0x118 0x55c 0x000 0x2 0x0
|
||||
#define MX35_PAD_I2C2_CLK__GPIO2_26 0x118 0x55c 0x8b0 0x5 0x0
|
||||
#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 0x118 0x55c 0x000 0x6 0x0
|
||||
#define MX35_PAD_I2C2_DAT__I2C2_SDA 0x11c 0x560 0x000 0x0 0x0
|
||||
#define MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x11c 0x560 0x7c8 0x1 0x0
|
||||
#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC 0x11c 0x560 0x9f4 0x2 0x0
|
||||
#define MX35_PAD_I2C2_DAT__GPIO2_27 0x11c 0x560 0x8b4 0x5 0x0
|
||||
#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 0x11c 0x560 0x000 0x6 0x0
|
||||
#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x120 0x564 0x000 0x0 0x0
|
||||
#define MX35_PAD_STXD4__GPIO2_28 0x120 0x564 0x8b8 0x5 0x0
|
||||
#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 0x120 0x564 0x000 0x7 0x0
|
||||
#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x124 0x568 0x000 0x0 0x0
|
||||
#define MX35_PAD_SRXD4__GPIO2_29 0x124 0x568 0x8bc 0x5 0x0
|
||||
#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 0x124 0x568 0x000 0x7 0x0
|
||||
#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x128 0x56c 0x000 0x0 0x0
|
||||
#define MX35_PAD_SCK4__GPIO2_30 0x128 0x56c 0x8c4 0x5 0x0
|
||||
#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 0x128 0x56c 0x000 0x7 0x0
|
||||
#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x12c 0x570 0x000 0x0 0x0
|
||||
#define MX35_PAD_STXFS4__GPIO2_31 0x12c 0x570 0x8c8 0x5 0x0
|
||||
#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 0x12c 0x570 0x000 0x7 0x0
|
||||
#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD 0x130 0x574 0x000 0x0 0x0
|
||||
#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 0x130 0x574 0x000 0x1 0x0
|
||||
#define MX35_PAD_STXD5__CSPI2_MOSI 0x130 0x574 0x7ec 0x2 0x0
|
||||
#define MX35_PAD_STXD5__GPIO1_0 0x130 0x574 0x82c 0x5 0x1
|
||||
#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 0x130 0x574 0x000 0x7 0x0
|
||||
#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD 0x134 0x578 0x000 0x0 0x0
|
||||
#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 0x134 0x578 0x998 0x1 0x0
|
||||
#define MX35_PAD_SRXD5__CSPI2_MISO 0x134 0x578 0x7e8 0x2 0x0
|
||||
#define MX35_PAD_SRXD5__GPIO1_1 0x134 0x578 0x838 0x5 0x1
|
||||
#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 0x134 0x578 0x000 0x7 0x0
|
||||
#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC 0x138 0x57c 0x000 0x0 0x0
|
||||
#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK 0x138 0x57c 0x994 0x1 0x0
|
||||
#define MX35_PAD_SCK5__CSPI2_SCLK 0x138 0x57c 0x7e0 0x2 0x0
|
||||
#define MX35_PAD_SCK5__GPIO1_2 0x138 0x57c 0x848 0x5 0x0
|
||||
#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 0x138 0x57c 0x000 0x7 0x0
|
||||
#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS 0x13c 0x580 0x000 0x0 0x0
|
||||
#define MX35_PAD_STXFS5__CSPI2_RDY 0x13c 0x580 0x7e4 0x2 0x0
|
||||
#define MX35_PAD_STXFS5__GPIO1_3 0x13c 0x580 0x84c 0x5 0x0
|
||||
#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 0x13c 0x580 0x000 0x7 0x0
|
||||
#define MX35_PAD_SCKR__ESAI_SCKR 0x140 0x584 0x000 0x0 0x0
|
||||
#define MX35_PAD_SCKR__GPIO1_4 0x140 0x584 0x850 0x5 0x1
|
||||
#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 0x140 0x584 0x000 0x7 0x0
|
||||
#define MX35_PAD_FSR__ESAI_FSR 0x144 0x588 0x000 0x0 0x0
|
||||
#define MX35_PAD_FSR__GPIO1_5 0x144 0x588 0x854 0x5 0x1
|
||||
#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 0x144 0x588 0x000 0x7 0x0
|
||||
#define MX35_PAD_HCKR__ESAI_HCKR 0x148 0x58c 0x000 0x0 0x0
|
||||
#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS 0x148 0x58c 0x000 0x1 0x0
|
||||
#define MX35_PAD_HCKR__CSPI2_SS0 0x148 0x58c 0x7f0 0x2 0x0
|
||||
#define MX35_PAD_HCKR__IPU_FLASH_STROBE 0x148 0x58c 0x000 0x3 0x0
|
||||
#define MX35_PAD_HCKR__GPIO1_6 0x148 0x58c 0x858 0x5 0x1
|
||||
#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 0x148 0x58c 0x000 0x7 0x0
|
||||
#define MX35_PAD_SCKT__ESAI_SCKT 0x14c 0x590 0x000 0x0 0x0
|
||||
#define MX35_PAD_SCKT__GPIO1_7 0x14c 0x590 0x85c 0x5 0x1
|
||||
#define MX35_PAD_SCKT__IPU_CSI_D_0 0x14c 0x590 0x930 0x6 0x0
|
||||
#define MX35_PAD_SCKT__KPP_ROW_2 0x14c 0x590 0x978 0x7 0x1
|
||||
#define MX35_PAD_FST__ESAI_FST 0x150 0x594 0x000 0x0 0x0
|
||||
#define MX35_PAD_FST__GPIO1_8 0x150 0x594 0x860 0x5 0x1
|
||||
#define MX35_PAD_FST__IPU_CSI_D_1 0x150 0x594 0x934 0x6 0x0
|
||||
#define MX35_PAD_FST__KPP_ROW_3 0x150 0x594 0x97c 0x7 0x1
|
||||
#define MX35_PAD_HCKT__ESAI_HCKT 0x154 0x598 0x000 0x0 0x0
|
||||
#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC 0x154 0x598 0x7a8 0x1 0x0
|
||||
#define MX35_PAD_HCKT__GPIO1_9 0x154 0x598 0x864 0x5 0x0
|
||||
#define MX35_PAD_HCKT__IPU_CSI_D_2 0x154 0x598 0x938 0x6 0x0
|
||||
#define MX35_PAD_HCKT__KPP_COL_3 0x154 0x598 0x95c 0x7 0x1
|
||||
#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 0x158 0x59c 0x000 0x0 0x0
|
||||
#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC 0x158 0x59c 0x000 0x1 0x0
|
||||
#define MX35_PAD_TX5_RX0__CSPI2_SS2 0x158 0x59c 0x7f8 0x2 0x1
|
||||
#define MX35_PAD_TX5_RX0__CAN2_TXCAN 0x158 0x59c 0x000 0x3 0x0
|
||||
#define MX35_PAD_TX5_RX0__UART2_DTR 0x158 0x59c 0x000 0x4 0x0
|
||||
#define MX35_PAD_TX5_RX0__GPIO1_10 0x158 0x59c 0x830 0x5 0x0
|
||||
#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 0x158 0x59c 0x000 0x7 0x0
|
||||
#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 0x15c 0x5a0 0x000 0x0 0x0
|
||||
#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS 0x15c 0x5a0 0x000 0x1 0x0
|
||||
#define MX35_PAD_TX4_RX1__CSPI2_SS3 0x15c 0x5a0 0x7fc 0x2 0x0
|
||||
#define MX35_PAD_TX4_RX1__CAN2_RXCAN 0x15c 0x5a0 0x7cc 0x3 0x0
|
||||
#define MX35_PAD_TX4_RX1__UART2_DSR 0x15c 0x5a0 0x000 0x4 0x0
|
||||
#define MX35_PAD_TX4_RX1__GPIO1_11 0x15c 0x5a0 0x834 0x5 0x0
|
||||
#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 0x15c 0x5a0 0x93c 0x6 0x0
|
||||
#define MX35_PAD_TX4_RX1__KPP_ROW_0 0x15c 0x5a0 0x970 0x7 0x1
|
||||
#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 0x160 0x5a4 0x000 0x0 0x0
|
||||
#define MX35_PAD_TX3_RX2__I2C3_SCL 0x160 0x5a4 0x91c 0x1 0x0
|
||||
#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 0x160 0x5a4 0x000 0x3 0x0
|
||||
#define MX35_PAD_TX3_RX2__GPIO1_12 0x160 0x5a4 0x000 0x5 0x0
|
||||
#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 0x160 0x5a4 0x940 0x6 0x0
|
||||
#define MX35_PAD_TX3_RX2__KPP_ROW_1 0x160 0x5a4 0x974 0x7 0x1
|
||||
#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 0x164 0x5a8 0x000 0x0 0x0
|
||||
#define MX35_PAD_TX2_RX3__I2C3_SDA 0x164 0x5a8 0x920 0x1 0x0
|
||||
#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 0x164 0x5a8 0x000 0x3 0x0
|
||||
#define MX35_PAD_TX2_RX3__GPIO1_13 0x164 0x5a8 0x000 0x5 0x0
|
||||
#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 0x164 0x5a8 0x944 0x6 0x0
|
||||
#define MX35_PAD_TX2_RX3__KPP_COL_0 0x164 0x5a8 0x950 0x7 0x1
|
||||
#define MX35_PAD_TX1__ESAI_TX1 0x168 0x5ac 0x000 0x0 0x0
|
||||
#define MX35_PAD_TX1__CCM_PMIC_RDY 0x168 0x5ac 0x7d4 0x1 0x1
|
||||
#define MX35_PAD_TX1__CSPI1_SS2 0x168 0x5ac 0x7d8 0x2 0x2
|
||||
#define MX35_PAD_TX1__EMI_NANDF_CE3 0x168 0x5ac 0x000 0x3 0x0
|
||||
#define MX35_PAD_TX1__UART2_RI 0x168 0x5ac 0x000 0x4 0x0
|
||||
#define MX35_PAD_TX1__GPIO1_14 0x168 0x5ac 0x000 0x5 0x0
|
||||
#define MX35_PAD_TX1__IPU_CSI_D_6 0x168 0x5ac 0x948 0x6 0x0
|
||||
#define MX35_PAD_TX1__KPP_COL_1 0x168 0x5ac 0x954 0x7 0x1
|
||||
#define MX35_PAD_TX0__ESAI_TX0 0x16c 0x5b0 0x000 0x0 0x0
|
||||
#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK 0x16c 0x5b0 0x994 0x1 0x1
|
||||
#define MX35_PAD_TX0__CSPI1_SS3 0x16c 0x5b0 0x7dc 0x2 0x0
|
||||
#define MX35_PAD_TX0__EMI_DTACK_B 0x16c 0x5b0 0x800 0x3 0x1
|
||||
#define MX35_PAD_TX0__UART2_DCD 0x16c 0x5b0 0x000 0x4 0x0
|
||||
#define MX35_PAD_TX0__GPIO1_15 0x16c 0x5b0 0x000 0x5 0x0
|
||||
#define MX35_PAD_TX0__IPU_CSI_D_7 0x16c 0x5b0 0x94c 0x6 0x0
|
||||
#define MX35_PAD_TX0__KPP_COL_2 0x16c 0x5b0 0x958 0x7 0x1
|
||||
#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI 0x170 0x5b4 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSPI1_MOSI__GPIO1_16 0x170 0x5b4 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 0x170 0x5b4 0x000 0x7 0x0
|
||||
#define MX35_PAD_CSPI1_MISO__CSPI1_MISO 0x174 0x5b8 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSPI1_MISO__GPIO1_17 0x174 0x5b8 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 0x174 0x5b8 0x000 0x7 0x0
|
||||
#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 0x178 0x5bc 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSPI1_SS0__OWIRE_LINE 0x178 0x5bc 0x990 0x1 0x1
|
||||
#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 0x178 0x5bc 0x7fc 0x2 0x1
|
||||
#define MX35_PAD_CSPI1_SS0__GPIO1_18 0x178 0x5bc 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 0x178 0x5bc 0x000 0x7 0x0
|
||||
#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 0x17c 0x5c0 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSPI1_SS1__PWM_PWMO 0x17c 0x5c0 0x000 0x1 0x0
|
||||
#define MX35_PAD_CSPI1_SS1__CCM_CLK32K 0x17c 0x5c0 0x7d0 0x2 0x1
|
||||
#define MX35_PAD_CSPI1_SS1__GPIO1_19 0x17c 0x5c0 0x000 0x5 0x0
|
||||
#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 0x17c 0x5c0 0x000 0x6 0x0
|
||||
#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 0x17c 0x5c0 0x000 0x7 0x0
|
||||
#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK 0x180 0x5c4 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSPI1_SCLK__GPIO3_4 0x180 0x5c4 0x904 0x5 0x0
|
||||
#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 0x180 0x5c4 0x000 0x6 0x0
|
||||
#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 0x180 0x5c4 0x000 0x7 0x0
|
||||
#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY 0x184 0x5c8 0x000 0x0 0x0
|
||||
#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 0x184 0x5c8 0x908 0x5 0x0
|
||||
#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 0x184 0x5c8 0x000 0x6 0x0
|
||||
#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 0x184 0x5c8 0x000 0x7 0x0
|
||||
#define MX35_PAD_RXD1__UART1_RXD_MUX 0x188 0x5cc 0x000 0x0 0x0
|
||||
#define MX35_PAD_RXD1__CSPI2_MOSI 0x188 0x5cc 0x7ec 0x1 0x1
|
||||
#define MX35_PAD_RXD1__KPP_COL_4 0x188 0x5cc 0x960 0x4 0x0
|
||||
#define MX35_PAD_RXD1__GPIO3_6 0x188 0x5cc 0x90c 0x5 0x0
|
||||
#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 0x188 0x5cc 0x000 0x7 0x0
|
||||
#define MX35_PAD_TXD1__UART1_TXD_MUX 0x18c 0x5d0 0x000 0x0 0x0
|
||||
#define MX35_PAD_TXD1__CSPI2_MISO 0x18c 0x5d0 0x7e8 0x1 0x1
|
||||
#define MX35_PAD_TXD1__KPP_COL_5 0x18c 0x5d0 0x964 0x4 0x0
|
||||
#define MX35_PAD_TXD1__GPIO3_7 0x18c 0x5d0 0x910 0x5 0x0
|
||||
#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 0x18c 0x5d0 0x000 0x7 0x0
|
||||
#define MX35_PAD_RTS1__UART1_RTS 0x190 0x5d4 0x000 0x0 0x0
|
||||
#define MX35_PAD_RTS1__CSPI2_SCLK 0x190 0x5d4 0x7e0 0x1 0x1
|
||||
#define MX35_PAD_RTS1__I2C3_SCL 0x190 0x5d4 0x91c 0x2 0x1
|
||||
#define MX35_PAD_RTS1__IPU_CSI_D_0 0x190 0x5d4 0x930 0x3 0x1
|
||||
#define MX35_PAD_RTS1__KPP_COL_6 0x190 0x5d4 0x968 0x4 0x0
|
||||
#define MX35_PAD_RTS1__GPIO3_8 0x190 0x5d4 0x914 0x5 0x0
|
||||
#define MX35_PAD_RTS1__EMI_NANDF_CE1 0x190 0x5d4 0x000 0x6 0x0
|
||||
#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 0x190 0x5d4 0x000 0x7 0x0
|
||||
#define MX35_PAD_CTS1__UART1_CTS 0x194 0x5d8 0x000 0x0 0x0
|
||||
#define MX35_PAD_CTS1__CSPI2_RDY 0x194 0x5d8 0x7e4 0x1 0x1
|
||||
#define MX35_PAD_CTS1__I2C3_SDA 0x194 0x5d8 0x920 0x2 0x1
|
||||
#define MX35_PAD_CTS1__IPU_CSI_D_1 0x194 0x5d8 0x934 0x3 0x1
|
||||
#define MX35_PAD_CTS1__KPP_COL_7 0x194 0x5d8 0x96c 0x4 0x0
|
||||
#define MX35_PAD_CTS1__GPIO3_9 0x194 0x5d8 0x918 0x5 0x0
|
||||
#define MX35_PAD_CTS1__EMI_NANDF_CE2 0x194 0x5d8 0x000 0x6 0x0
|
||||
#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 0x194 0x5d8 0x000 0x7 0x0
|
||||
#define MX35_PAD_RXD2__UART2_RXD_MUX 0x198 0x5dc 0x000 0x0 0x0
|
||||
#define MX35_PAD_RXD2__KPP_ROW_4 0x198 0x5dc 0x980 0x4 0x0
|
||||
#define MX35_PAD_RXD2__GPIO3_10 0x198 0x5dc 0x8ec 0x5 0x0
|
||||
#define MX35_PAD_TXD2__UART2_TXD_MUX 0x19c 0x5e0 0x000 0x0 0x0
|
||||
#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK 0x19c 0x5e0 0x994 0x1 0x2
|
||||
#define MX35_PAD_TXD2__KPP_ROW_5 0x19c 0x5e0 0x984 0x4 0x0
|
||||
#define MX35_PAD_TXD2__GPIO3_11 0x19c 0x5e0 0x8f0 0x5 0x0
|
||||
#define MX35_PAD_RTS2__UART2_RTS 0x1a0 0x5e4 0x000 0x0 0x0
|
||||
#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 0x1a0 0x5e4 0x998 0x1 0x1
|
||||
#define MX35_PAD_RTS2__CAN2_RXCAN 0x1a0 0x5e4 0x7cc 0x2 0x1
|
||||
#define MX35_PAD_RTS2__IPU_CSI_D_2 0x1a0 0x5e4 0x938 0x3 0x1
|
||||
#define MX35_PAD_RTS2__KPP_ROW_6 0x1a0 0x5e4 0x988 0x4 0x0
|
||||
#define MX35_PAD_RTS2__GPIO3_12 0x1a0 0x5e4 0x8f4 0x5 0x0
|
||||
#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC 0x1a0 0x5e4 0x000 0x6 0x0
|
||||
#define MX35_PAD_RTS2__UART3_RXD_MUX 0x1a0 0x5e4 0x9a0 0x7 0x0
|
||||
#define MX35_PAD_CTS2__UART2_CTS 0x1a4 0x5e8 0x000 0x0 0x0
|
||||
#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 0x1a4 0x5e8 0x000 0x1 0x0
|
||||
#define MX35_PAD_CTS2__CAN2_TXCAN 0x1a4 0x5e8 0x000 0x2 0x0
|
||||
#define MX35_PAD_CTS2__IPU_CSI_D_3 0x1a4 0x5e8 0x93c 0x3 0x1
|
||||
#define MX35_PAD_CTS2__KPP_ROW_7 0x1a4 0x5e8 0x98c 0x4 0x0
|
||||
#define MX35_PAD_CTS2__GPIO3_13 0x1a4 0x5e8 0x8f8 0x5 0x0
|
||||
#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS 0x1a4 0x5e8 0x000 0x6 0x0
|
||||
#define MX35_PAD_CTS2__UART3_TXD_MUX 0x1a4 0x5e8 0x000 0x7 0x0
|
||||
#define MX35_PAD_RTCK__ARM11P_TOP_RTCK 0x000 0x5ec 0x000 0x0 0x0
|
||||
#define MX35_PAD_TCK__SJC_TCK 0x000 0x5f0 0x000 0x0 0x0
|
||||
#define MX35_PAD_TMS__SJC_TMS 0x000 0x5f4 0x000 0x0 0x0
|
||||
#define MX35_PAD_TDI__SJC_TDI 0x000 0x5f8 0x000 0x0 0x0
|
||||
#define MX35_PAD_TDO__SJC_TDO 0x000 0x5fc 0x000 0x0 0x0
|
||||
#define MX35_PAD_TRSTB__SJC_TRSTB 0x000 0x600 0x000 0x0 0x0
|
||||
#define MX35_PAD_DE_B__SJC_DE_B 0x000 0x604 0x000 0x0 0x0
|
||||
#define MX35_PAD_SJC_MOD__SJC_MOD 0x000 0x608 0x000 0x0 0x0
|
||||
#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR 0x1a8 0x60c 0x000 0x0 0x0
|
||||
#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR 0x1a8 0x60c 0x000 0x1 0x0
|
||||
#define MX35_PAD_USBOTG_PWR__GPIO3_14 0x1a8 0x60c 0x8fc 0x5 0x0
|
||||
#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC 0x1ac 0x610 0x000 0x0 0x0
|
||||
#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC 0x1ac 0x610 0x9f4 0x1 0x1
|
||||
#define MX35_PAD_USBOTG_OC__GPIO3_15 0x1ac 0x610 0x900 0x5 0x0
|
||||
#define MX35_PAD_LD0__IPU_DISPB_DAT_0 0x1b0 0x614 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD0__GPIO2_0 0x1b0 0x614 0x868 0x5 0x1
|
||||
#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 0x1b0 0x614 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD1__IPU_DISPB_DAT_1 0x1b4 0x618 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD1__GPIO2_1 0x1b4 0x618 0x894 0x5 0x0
|
||||
#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 0x1b4 0x618 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD2__IPU_DISPB_DAT_2 0x1b8 0x61c 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD2__GPIO2_2 0x1b8 0x61c 0x8c0 0x5 0x0
|
||||
#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 0x1b8 0x61c 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD3__IPU_DISPB_DAT_3 0x1bc 0x620 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD3__GPIO2_3 0x1bc 0x620 0x8cc 0x5 0x0
|
||||
#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 0x1bc 0x620 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD4__IPU_DISPB_DAT_4 0x1c0 0x624 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD4__GPIO2_4 0x1c0 0x624 0x8d0 0x5 0x0
|
||||
#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 0x1c0 0x624 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD5__IPU_DISPB_DAT_5 0x1c4 0x628 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD5__GPIO2_5 0x1c4 0x628 0x8d4 0x5 0x0
|
||||
#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 0x1c4 0x628 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD6__IPU_DISPB_DAT_6 0x1c8 0x62c 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD6__GPIO2_6 0x1c8 0x62c 0x8d8 0x5 0x0
|
||||
#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 0x1c8 0x62c 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD7__IPU_DISPB_DAT_7 0x1cc 0x630 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD7__GPIO2_7 0x1cc 0x630 0x8dc 0x5 0x0
|
||||
#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 0x1cc 0x630 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD8__IPU_DISPB_DAT_8 0x1d0 0x634 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD8__GPIO2_8 0x1d0 0x634 0x8e0 0x5 0x0
|
||||
#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 0x1d0 0x634 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD9__IPU_DISPB_DAT_9 0x1d4 0x638 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD9__GPIO2_9 0x1d4 0x638 0x8e4 0x5 0x0
|
||||
#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 0x1d4 0x638 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD10__IPU_DISPB_DAT_10 0x1d8 0x63c 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD10__GPIO2_10 0x1d8 0x63c 0x86c 0x5 0x0
|
||||
#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 0x1d8 0x63c 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD11__IPU_DISPB_DAT_11 0x1dc 0x640 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD11__GPIO2_11 0x1dc 0x640 0x870 0x5 0x0
|
||||
#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 0x1dc 0x640 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 0x1dc 0x640 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD12__IPU_DISPB_DAT_12 0x1e0 0x644 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD12__GPIO2_12 0x1e0 0x644 0x874 0x5 0x0
|
||||
#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 0x1e0 0x644 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 0x1e0 0x644 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD13__IPU_DISPB_DAT_13 0x1e4 0x648 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD13__GPIO2_13 0x1e4 0x648 0x878 0x5 0x0
|
||||
#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 0x1e4 0x648 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 0x1e4 0x648 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD14__IPU_DISPB_DAT_14 0x1e8 0x64c 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD14__GPIO2_14 0x1e8 0x64c 0x87c 0x5 0x0
|
||||
#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 0x1e8 0x64c 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 0x1e8 0x64c 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD15__IPU_DISPB_DAT_15 0x1ec 0x650 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD15__GPIO2_15 0x1ec 0x650 0x880 0x5 0x0
|
||||
#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 0x1ec 0x650 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 0x1ec 0x650 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD16__IPU_DISPB_DAT_16 0x1f0 0x654 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC 0x1f0 0x654 0x928 0x2 0x0
|
||||
#define MX35_PAD_LD16__GPIO2_16 0x1f0 0x654 0x884 0x5 0x0
|
||||
#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 0x1f0 0x654 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 0x1f0 0x654 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD17__IPU_DISPB_DAT_17 0x1f4 0x658 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD17__IPU_DISPB_CS2 0x1f4 0x658 0x000 0x2 0x0
|
||||
#define MX35_PAD_LD17__GPIO2_17 0x1f4 0x658 0x888 0x5 0x0
|
||||
#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 0x1f4 0x658 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 0x1f4 0x658 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD18__IPU_DISPB_DAT_18 0x1f8 0x65c 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC 0x1f8 0x65c 0x924 0x1 0x1
|
||||
#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC 0x1f8 0x65c 0x928 0x2 0x1
|
||||
#define MX35_PAD_LD18__ESDHC3_CMD 0x1f8 0x65c 0x818 0x3 0x0
|
||||
#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 0x1f8 0x65c 0x9b0 0x4 0x0
|
||||
#define MX35_PAD_LD18__GPIO3_24 0x1f8 0x65c 0x000 0x5 0x0
|
||||
#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 0x1f8 0x65c 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 0x1f8 0x65c 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD19__IPU_DISPB_DAT_19 0x1fc 0x660 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD19__IPU_DISPB_BCLK 0x1fc 0x660 0x000 0x1 0x0
|
||||
#define MX35_PAD_LD19__IPU_DISPB_CS1 0x1fc 0x660 0x000 0x2 0x0
|
||||
#define MX35_PAD_LD19__ESDHC3_CLK 0x1fc 0x660 0x814 0x3 0x0
|
||||
#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR 0x1fc 0x660 0x9c4 0x4 0x0
|
||||
#define MX35_PAD_LD19__GPIO3_25 0x1fc 0x660 0x000 0x5 0x0
|
||||
#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 0x1fc 0x660 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 0x1fc 0x660 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD20__IPU_DISPB_DAT_20 0x200 0x664 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD20__IPU_DISPB_CS0 0x200 0x664 0x000 0x1 0x0
|
||||
#define MX35_PAD_LD20__IPU_DISPB_SD_CLK 0x200 0x664 0x000 0x2 0x0
|
||||
#define MX35_PAD_LD20__ESDHC3_DAT0 0x200 0x664 0x81c 0x3 0x0
|
||||
#define MX35_PAD_LD20__GPIO3_26 0x200 0x664 0x000 0x5 0x0
|
||||
#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 0x200 0x664 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 0x200 0x664 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD21__IPU_DISPB_DAT_21 0x204 0x668 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD21__IPU_DISPB_PAR_RS 0x204 0x668 0x000 0x1 0x0
|
||||
#define MX35_PAD_LD21__IPU_DISPB_SER_RS 0x204 0x668 0x000 0x2 0x0
|
||||
#define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0
|
||||
#define MX35_PAD_LD21__USB_TOP_USBOTG_STP 0x204 0x668 0x000 0x4 0x0
|
||||
#define MX35_PAD_LD21__GPIO3_27 0x204 0x668 0x000 0x5 0x0
|
||||
#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x204 0x668 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 0x204 0x668 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD22__IPU_DISPB_DAT_22 0x208 0x66c 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD22__IPU_DISPB_WR 0x208 0x66c 0x000 0x1 0x0
|
||||
#define MX35_PAD_LD22__IPU_DISPB_SD_D_I 0x208 0x66c 0x92c 0x2 0x0
|
||||
#define MX35_PAD_LD22__ESDHC3_DAT2 0x208 0x66c 0x824 0x3 0x0
|
||||
#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT 0x208 0x66c 0x9c8 0x4 0x0
|
||||
#define MX35_PAD_LD22__GPIO3_28 0x208 0x66c 0x000 0x5 0x0
|
||||
#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR 0x208 0x66c 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD22__ARM11P_TOP_TRCTL 0x208 0x66c 0x000 0x7 0x0
|
||||
#define MX35_PAD_LD23__IPU_DISPB_DAT_23 0x20c 0x670 0x000 0x0 0x0
|
||||
#define MX35_PAD_LD23__IPU_DISPB_RD 0x20c 0x670 0x000 0x1 0x0
|
||||
#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO 0x20c 0x670 0x92c 0x2 0x1
|
||||
#define MX35_PAD_LD23__ESDHC3_DAT3 0x20c 0x670 0x828 0x3 0x0
|
||||
#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 0x20c 0x670 0x9c0 0x4 0x0
|
||||
#define MX35_PAD_LD23__GPIO3_29 0x20c 0x670 0x000 0x5 0x0
|
||||
#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS 0x20c 0x670 0x000 0x6 0x0
|
||||
#define MX35_PAD_LD23__ARM11P_TOP_TRCLK 0x20c 0x670 0x000 0x7 0x0
|
||||
#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x210 0x674 0x000 0x0 0x0
|
||||
#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO 0x210 0x674 0x92c 0x2 0x2
|
||||
#define MX35_PAD_D3_HSYNC__GPIO3_30 0x210 0x674 0x000 0x5 0x0
|
||||
#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE 0x210 0x674 0x000 0x6 0x0
|
||||
#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 0x210 0x674 0x000 0x7 0x0
|
||||
#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x214 0x678 0x000 0x0 0x0
|
||||
#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK 0x214 0x678 0x000 0x2 0x0
|
||||
#define MX35_PAD_D3_FPSHIFT__GPIO3_31 0x214 0x678 0x000 0x5 0x0
|
||||
#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 0x214 0x678 0x000 0x6 0x0
|
||||
#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 0x214 0x678 0x000 0x7 0x0
|
||||
#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x218 0x67c 0x000 0x0 0x0
|
||||
#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O 0x218 0x67c 0x000 0x2 0x0
|
||||
#define MX35_PAD_D3_DRDY__GPIO1_0 0x218 0x67c 0x82c 0x5 0x2
|
||||
#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 0x218 0x67c 0x000 0x6 0x0
|
||||
#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 0x218 0x67c 0x000 0x7 0x0
|
||||
#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x21c 0x680 0x000 0x0 0x0
|
||||
#define MX35_PAD_CONTRAST__GPIO1_1 0x21c 0x680 0x838 0x5 0x2
|
||||
#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 0x21c 0x680 0x000 0x6 0x0
|
||||
#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 0x21c 0x680 0x000 0x7 0x0
|
||||
#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x220 0x684 0x000 0x0 0x0
|
||||
#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 0x220 0x684 0x000 0x2 0x0
|
||||
#define MX35_PAD_D3_VSYNC__GPIO1_2 0x220 0x684 0x848 0x5 0x1
|
||||
#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD 0x220 0x684 0x000 0x6 0x0
|
||||
#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 0x220 0x684 0x000 0x7 0x0
|
||||
#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV 0x224 0x688 0x000 0x0 0x0
|
||||
#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS 0x224 0x688 0x000 0x2 0x0
|
||||
#define MX35_PAD_D3_REV__GPIO1_3 0x224 0x688 0x84c 0x5 0x1
|
||||
#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB 0x224 0x688 0x000 0x6 0x0
|
||||
#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 0x224 0x688 0x000 0x7 0x0
|
||||
#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS 0x228 0x68c 0x000 0x0 0x0
|
||||
#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 0x228 0x68c 0x000 0x2 0x0
|
||||
#define MX35_PAD_D3_CLS__GPIO1_4 0x228 0x68c 0x850 0x5 0x2
|
||||
#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 0x228 0x68c 0x000 0x6 0x0
|
||||
#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 0x228 0x68c 0x000 0x7 0x0
|
||||
#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL 0x22c 0x690 0x000 0x0 0x0
|
||||
#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC 0x22c 0x690 0x928 0x2 0x2
|
||||
#define MX35_PAD_D3_SPL__GPIO1_5 0x22c 0x690 0x854 0x5 0x2
|
||||
#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 0x22c 0x690 0x000 0x6 0x0
|
||||
#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 0x22c 0x690 0x000 0x7 0x0
|
||||
#define MX35_PAD_SD1_CMD__ESDHC1_CMD 0x230 0x694 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD1_CMD__MSHC_SCLK 0x230 0x694 0x000 0x1 0x0
|
||||
#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC 0x230 0x694 0x924 0x3 0x2
|
||||
#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 0x230 0x694 0x9b4 0x4 0x0
|
||||
#define MX35_PAD_SD1_CMD__GPIO1_6 0x230 0x694 0x858 0x5 0x2
|
||||
#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL 0x230 0x694 0x000 0x7 0x0
|
||||
#define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0
|
||||
#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0
|
||||
#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0
|
||||
#define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2
|
||||
#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0
|
||||
#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0
|
||||
#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0
|
||||
#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0
|
||||
#define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2
|
||||
#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0
|
||||
#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x23c 0x6a0 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 0x23c 0x6a0 0x000 0x1 0x0
|
||||
#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS 0x23c 0x6a0 0x000 0x3 0x0
|
||||
#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 0x23c 0x6a0 0x9a4 0x4 0x0
|
||||
#define MX35_PAD_SD1_DATA1__GPIO1_9 0x23c 0x6a0 0x864 0x5 0x1
|
||||
#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 0x23c 0x6a0 0x000 0x7 0x0
|
||||
#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x240 0x6a4 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 0x240 0x6a4 0x000 0x1 0x0
|
||||
#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR 0x240 0x6a4 0x000 0x3 0x0
|
||||
#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 0x240 0x6a4 0x9a8 0x4 0x0
|
||||
#define MX35_PAD_SD1_DATA2__GPIO1_10 0x240 0x6a4 0x830 0x5 0x1
|
||||
#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 0x240 0x6a4 0x000 0x7 0x0
|
||||
#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x244 0x6a8 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 0x244 0x6a8 0x000 0x1 0x0
|
||||
#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD 0x244 0x6a8 0x000 0x3 0x0
|
||||
#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 0x244 0x6a8 0x9ac 0x4 0x0
|
||||
#define MX35_PAD_SD1_DATA3__GPIO1_11 0x244 0x6a8 0x834 0x5 0x1
|
||||
#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 0x244 0x6a8 0x000 0x7 0x0
|
||||
#define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2
|
||||
#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0
|
||||
#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2
|
||||
#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0
|
||||
#define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2
|
||||
#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0
|
||||
#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3
|
||||
#define MX35_PAD_SD2_CLK__ESDHC2_CLK 0x24c 0x6b0 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD2_CLK__I2C3_SDA 0x24c 0x6b0 0x920 0x1 0x2
|
||||
#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 0x24c 0x6b0 0x808 0x2 0x0
|
||||
#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 0x24c 0x6b0 0x93c 0x3 0x2
|
||||
#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 0x24c 0x6b0 0x9e0 0x4 0x0
|
||||
#define MX35_PAD_SD2_CLK__GPIO2_1 0x24c 0x6b0 0x894 0x5 0x1
|
||||
#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 0x24c 0x6b0 0x998 0x6 0x2
|
||||
#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 0x24c 0x6b0 0x000 0x7 0x0
|
||||
#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1
|
||||
#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0
|
||||
#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1
|
||||
#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0
|
||||
#define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1
|
||||
#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3
|
||||
#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 0x254 0x6b8 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX 0x254 0x6b8 0x000 0x1 0x0
|
||||
#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 0x254 0x6b8 0x810 0x2 0x0
|
||||
#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 0x254 0x6b8 0x944 0x3 0x1
|
||||
#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 0x254 0x6b8 0x9cc 0x4 0x0
|
||||
#define MX35_PAD_SD2_DATA1__GPIO2_3 0x254 0x6b8 0x8cc 0x5 0x1
|
||||
#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 0x258 0x6bc 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD2_DATA2__UART3_RTS 0x258 0x6bc 0x99c 0x1 0x0
|
||||
#define MX35_PAD_SD2_DATA2__CAN1_RXCAN 0x258 0x6bc 0x7c8 0x2 0x1
|
||||
#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 0x258 0x6bc 0x948 0x3 0x1
|
||||
#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 0x258 0x6bc 0x9d0 0x4 0x0
|
||||
#define MX35_PAD_SD2_DATA2__GPIO2_4 0x258 0x6bc 0x8d0 0x5 0x1
|
||||
#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 0x25c 0x6c0 0x000 0x0 0x0
|
||||
#define MX35_PAD_SD2_DATA3__UART3_CTS 0x25c 0x6c0 0x000 0x1 0x0
|
||||
#define MX35_PAD_SD2_DATA3__CAN1_TXCAN 0x25c 0x6c0 0x000 0x2 0x0
|
||||
#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 0x25c 0x6c0 0x94c 0x3 0x1
|
||||
#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 0x25c 0x6c0 0x9d4 0x4 0x0
|
||||
#define MX35_PAD_SD2_DATA3__GPIO2_5 0x25c 0x6c0 0x8d4 0x5 0x1
|
||||
#define MX35_PAD_ATA_CS0__ATA_CS0 0x260 0x6c4 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_CS0__CSPI1_SS3 0x260 0x6c4 0x7dc 0x1 0x1
|
||||
#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 0x260 0x6c4 0x000 0x3 0x0
|
||||
#define MX35_PAD_ATA_CS0__GPIO2_6 0x260 0x6c4 0x8d8 0x5 0x1
|
||||
#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 0x260 0x6c4 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 0x260 0x6c4 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_CS1__ATA_CS1 0x264 0x6c8 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 0x264 0x6c8 0x000 0x3 0x0
|
||||
#define MX35_PAD_ATA_CS1__CSPI2_SS0 0x264 0x6c8 0x7f0 0x4 0x1
|
||||
#define MX35_PAD_ATA_CS1__GPIO2_7 0x264 0x6c8 0x8dc 0x5 0x1
|
||||
#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 0x264 0x6c8 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 0x264 0x6c8 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DIOR__ATA_DIOR 0x268 0x6cc 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 0x268 0x6cc 0x81c 0x1 0x1
|
||||
#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR 0x268 0x6cc 0x9c4 0x2 0x1
|
||||
#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 0x268 0x6cc 0x000 0x3 0x0
|
||||
#define MX35_PAD_ATA_DIOR__CSPI2_SS1 0x268 0x6cc 0x7f4 0x4 0x1
|
||||
#define MX35_PAD_ATA_DIOR__GPIO2_8 0x268 0x6cc 0x8e0 0x5 0x1
|
||||
#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 0x268 0x6cc 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 0x268 0x6cc 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DIOW__ATA_DIOW 0x26c 0x6d0 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1
|
||||
#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP 0x26c 0x6d0 0x000 0x2 0x0
|
||||
#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 0x26c 0x6d0 0x000 0x3 0x0
|
||||
#define MX35_PAD_ATA_DIOW__CSPI2_MOSI 0x26c 0x6d0 0x7ec 0x4 0x2
|
||||
#define MX35_PAD_ATA_DIOW__GPIO2_9 0x26c 0x6d0 0x8e4 0x5 0x1
|
||||
#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 0x26c 0x6d0 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 0x26c 0x6d0 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DMACK__ATA_DMACK 0x270 0x6d4 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 0x270 0x6d4 0x824 0x1 0x1
|
||||
#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT 0x270 0x6d4 0x9c8 0x2 0x1
|
||||
#define MX35_PAD_ATA_DMACK__CSPI2_MISO 0x270 0x6d4 0x7e8 0x4 0x2
|
||||
#define MX35_PAD_ATA_DMACK__GPIO2_10 0x270 0x6d4 0x86c 0x5 0x1
|
||||
#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 0x270 0x6d4 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 0x270 0x6d4 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_RESET_B__ATA_RESET_B 0x274 0x6d8 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 0x274 0x6d8 0x828 0x1 0x1
|
||||
#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 0x274 0x6d8 0x9a4 0x2 0x1
|
||||
#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O 0x274 0x6d8 0x000 0x3 0x0
|
||||
#define MX35_PAD_ATA_RESET_B__CSPI2_RDY 0x274 0x6d8 0x7e4 0x4 0x2
|
||||
#define MX35_PAD_ATA_RESET_B__GPIO2_11 0x274 0x6d8 0x870 0x5 0x1
|
||||
#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 0x274 0x6d8 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 0x274 0x6d8 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_IORDY__ATA_IORDY 0x278 0x6dc 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 0x278 0x6dc 0x000 0x1 0x0
|
||||
#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 0x278 0x6dc 0x9a8 0x2 0x1
|
||||
#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO 0x278 0x6dc 0x92c 0x3 0x3
|
||||
#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 0x278 0x6dc 0x000 0x4 0x0
|
||||
#define MX35_PAD_ATA_IORDY__GPIO2_12 0x278 0x6dc 0x874 0x5 0x1
|
||||
#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 0x278 0x6dc 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 0x278 0x6dc 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DATA0__ATA_DATA_0 0x27c 0x6e0 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 0x27c 0x6e0 0x000 0x1 0x0
|
||||
#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 0x27c 0x6e0 0x9ac 0x2 0x1
|
||||
#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC 0x27c 0x6e0 0x928 0x3 0x4
|
||||
#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 0x27c 0x6e0 0x000 0x4 0x0
|
||||
#define MX35_PAD_ATA_DATA0__GPIO2_13 0x27c 0x6e0 0x878 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 0x27c 0x6e0 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 0x27c 0x6e0 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DATA1__ATA_DATA_1 0x280 0x6e4 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 0x280 0x6e4 0x000 0x1 0x0
|
||||
#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 0x280 0x6e4 0x9b0 0x2 0x1
|
||||
#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK 0x280 0x6e4 0x000 0x3 0x0
|
||||
#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 0x280 0x6e4 0x000 0x4 0x0
|
||||
#define MX35_PAD_ATA_DATA1__GPIO2_14 0x280 0x6e4 0x87c 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 0x280 0x6e4 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 0x280 0x6e4 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DATA2__ATA_DATA_2 0x284 0x6e8 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 0x284 0x6e8 0x000 0x1 0x0
|
||||
#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 0x284 0x6e8 0x9b4 0x2 0x1
|
||||
#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS 0x284 0x6e8 0x000 0x3 0x0
|
||||
#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 0x284 0x6e8 0x000 0x4 0x0
|
||||
#define MX35_PAD_ATA_DATA2__GPIO2_15 0x284 0x6e8 0x880 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 0x284 0x6e8 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 0x284 0x6e8 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DATA3__ATA_DATA_3 0x288 0x6ec 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA3__ESDHC3_CLK 0x288 0x6ec 0x814 0x1 0x1
|
||||
#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 0x288 0x6ec 0x9b8 0x2 0x1
|
||||
#define MX35_PAD_ATA_DATA3__CSPI2_SCLK 0x288 0x6ec 0x7e0 0x4 0x2
|
||||
#define MX35_PAD_ATA_DATA3__GPIO2_16 0x288 0x6ec 0x884 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 0x288 0x6ec 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 0x288 0x6ec 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DATA4__ATA_DATA_4 0x28c 0x6f0 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA4__ESDHC3_CMD 0x28c 0x6f0 0x818 0x1 0x1
|
||||
#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 0x28c 0x6f0 0x9bc 0x2 0x1
|
||||
#define MX35_PAD_ATA_DATA4__GPIO2_17 0x28c 0x6f0 0x888 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 0x28c 0x6f0 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 0x28c 0x6f0 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DATA5__ATA_DATA_5 0x290 0x6f4 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 0x290 0x6f4 0x9c0 0x2 0x1
|
||||
#define MX35_PAD_ATA_DATA5__GPIO2_18 0x290 0x6f4 0x88c 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 0x290 0x6f4 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 0x290 0x6f4 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DATA6__ATA_DATA_6 0x294 0x6f8 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA6__CAN1_TXCAN 0x294 0x6f8 0x000 0x1 0x0
|
||||
#define MX35_PAD_ATA_DATA6__UART1_DTR 0x294 0x6f8 0x000 0x2 0x0
|
||||
#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD 0x294 0x6f8 0x7b4 0x3 0x0
|
||||
#define MX35_PAD_ATA_DATA6__GPIO2_19 0x294 0x6f8 0x890 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 0x294 0x6f8 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA7__ATA_DATA_7 0x298 0x6fc 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA7__CAN1_RXCAN 0x298 0x6fc 0x7c8 0x1 0x2
|
||||
#define MX35_PAD_ATA_DATA7__UART1_DSR 0x298 0x6fc 0x000 0x2 0x0
|
||||
#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD 0x298 0x6fc 0x7b0 0x3 0x0
|
||||
#define MX35_PAD_ATA_DATA7__GPIO2_20 0x298 0x6fc 0x898 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 0x298 0x6fc 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA8__ATA_DATA_8 0x29c 0x700 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA8__UART3_RTS 0x29c 0x700 0x99c 0x1 0x1
|
||||
#define MX35_PAD_ATA_DATA8__UART1_RI 0x29c 0x700 0x000 0x2 0x0
|
||||
#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC 0x29c 0x700 0x7c0 0x3 0x0
|
||||
#define MX35_PAD_ATA_DATA8__GPIO2_21 0x29c 0x700 0x89c 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 0x29c 0x700 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA9__ATA_DATA_9 0x2a0 0x704 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA9__UART3_CTS 0x2a0 0x704 0x000 0x1 0x0
|
||||
#define MX35_PAD_ATA_DATA9__UART1_DCD 0x2a0 0x704 0x000 0x2 0x0
|
||||
#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS 0x2a0 0x704 0x7c4 0x3 0x0
|
||||
#define MX35_PAD_ATA_DATA9__GPIO2_22 0x2a0 0x704 0x8a0 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 0x2a0 0x704 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA10__ATA_DATA_10 0x2a4 0x708 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX 0x2a4 0x708 0x9a0 0x1 0x2
|
||||
#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC 0x2a4 0x708 0x7b8 0x3 0x0
|
||||
#define MX35_PAD_ATA_DATA10__GPIO2_23 0x2a4 0x708 0x8a4 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 0x2a4 0x708 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA11__ATA_DATA_11 0x2a8 0x70c 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX 0x2a8 0x70c 0x000 0x1 0x0
|
||||
#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS 0x2a8 0x70c 0x7bc 0x3 0x0
|
||||
#define MX35_PAD_ATA_DATA11__GPIO2_24 0x2a8 0x70c 0x8a8 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 0x2a8 0x70c 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA12__ATA_DATA_12 0x2ac 0x710 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA12__I2C3_SCL 0x2ac 0x710 0x91c 0x1 0x3
|
||||
#define MX35_PAD_ATA_DATA12__GPIO2_25 0x2ac 0x710 0x8ac 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 0x2ac 0x710 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA13__ATA_DATA_13 0x2b0 0x714 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA13__I2C3_SDA 0x2b0 0x714 0x920 0x1 0x3
|
||||
#define MX35_PAD_ATA_DATA13__GPIO2_26 0x2b0 0x714 0x8b0 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 0x2b0 0x714 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA14__ATA_DATA_14 0x2b4 0x718 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 0x2b4 0x718 0x930 0x1 0x2
|
||||
#define MX35_PAD_ATA_DATA14__KPP_ROW_0 0x2b4 0x718 0x970 0x3 0x2
|
||||
#define MX35_PAD_ATA_DATA14__GPIO2_27 0x2b4 0x718 0x8b4 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 0x2b4 0x718 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DATA15__ATA_DATA_15 0x2b8 0x71c 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 0x2b8 0x71c 0x934 0x1 0x2
|
||||
#define MX35_PAD_ATA_DATA15__KPP_ROW_1 0x2b8 0x71c 0x974 0x3 0x2
|
||||
#define MX35_PAD_ATA_DATA15__GPIO2_28 0x2b8 0x71c 0x8b8 0x5 0x1
|
||||
#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 0x2b8 0x71c 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_INTRQ__ATA_INTRQ 0x2bc 0x720 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 0x2bc 0x720 0x938 0x1 0x3
|
||||
#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 0x2bc 0x720 0x978 0x3 0x2
|
||||
#define MX35_PAD_ATA_INTRQ__GPIO2_29 0x2bc 0x720 0x8bc 0x5 0x1
|
||||
#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 0x2bc 0x720 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN 0x2c0 0x724 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 0x2c0 0x724 0x93c 0x1 0x3
|
||||
#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 0x2c0 0x724 0x97c 0x3 0x2
|
||||
#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 0x2c0 0x724 0x8c4 0x5 0x1
|
||||
#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 0x2c0 0x724 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DMARQ__ATA_DMARQ 0x2c4 0x728 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 0x2c4 0x728 0x940 0x1 0x2
|
||||
#define MX35_PAD_ATA_DMARQ__KPP_COL_0 0x2c4 0x728 0x950 0x3 0x2
|
||||
#define MX35_PAD_ATA_DMARQ__GPIO2_31 0x2c4 0x728 0x8c8 0x5 0x1
|
||||
#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 0x2c4 0x728 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 0x2c4 0x728 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DA0__ATA_DA_0 0x2c8 0x72c 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 0x2c8 0x72c 0x944 0x1 0x2
|
||||
#define MX35_PAD_ATA_DA0__KPP_COL_1 0x2c8 0x72c 0x954 0x3 0x2
|
||||
#define MX35_PAD_ATA_DA0__GPIO3_0 0x2c8 0x72c 0x8e8 0x5 0x1
|
||||
#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 0x2c8 0x72c 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 0x2c8 0x72c 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DA1__ATA_DA_1 0x2cc 0x730 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 0x2cc 0x730 0x948 0x1 0x2
|
||||
#define MX35_PAD_ATA_DA1__KPP_COL_2 0x2cc 0x730 0x958 0x3 0x2
|
||||
#define MX35_PAD_ATA_DA1__GPIO3_1 0x2cc 0x730 0x000 0x5 0x0
|
||||
#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 0x2cc 0x730 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 0x2cc 0x730 0x000 0x7 0x0
|
||||
#define MX35_PAD_ATA_DA2__ATA_DA_2 0x2d0 0x734 0x000 0x0 0x0
|
||||
#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 0x2d0 0x734 0x94c 0x1 0x2
|
||||
#define MX35_PAD_ATA_DA2__KPP_COL_3 0x2d0 0x734 0x95c 0x3 0x2
|
||||
#define MX35_PAD_ATA_DA2__GPIO3_2 0x2d0 0x734 0x000 0x5 0x0
|
||||
#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 0x2d0 0x734 0x000 0x6 0x0
|
||||
#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 0x2d0 0x734 0x000 0x7 0x0
|
||||
#define MX35_PAD_MLB_CLK__MLB_MLBCLK 0x2d4 0x738 0x000 0x0 0x0
|
||||
#define MX35_PAD_MLB_CLK__GPIO3_3 0x2d4 0x738 0x000 0x5 0x0
|
||||
#define MX35_PAD_MLB_DAT__MLB_MLBDAT 0x2d8 0x73c 0x000 0x0 0x0
|
||||
#define MX35_PAD_MLB_DAT__GPIO3_4 0x2d8 0x73c 0x904 0x5 0x1
|
||||
#define MX35_PAD_MLB_SIG__MLB_MLBSIG 0x2dc 0x740 0x000 0x0 0x0
|
||||
#define MX35_PAD_MLB_SIG__GPIO3_5 0x2dc 0x740 0x908 0x5 0x1
|
||||
#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x2e0 0x744 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 0x2e0 0x744 0x804 0x1 0x1
|
||||
#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX 0x2e0 0x744 0x9a0 0x2 0x3
|
||||
#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR 0x2e0 0x744 0x9ec 0x3 0x1
|
||||
#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI 0x2e0 0x744 0x7ec 0x4 0x3
|
||||
#define MX35_PAD_FEC_TX_CLK__GPIO3_6 0x2e0 0x744 0x90c 0x5 0x1
|
||||
#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC 0x2e0 0x744 0x928 0x6 0x5
|
||||
#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 0x2e0 0x744 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x2e4 0x748 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 0x2e4 0x748 0x808 0x1 0x1
|
||||
#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX 0x2e4 0x748 0x000 0x2 0x0
|
||||
#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP 0x2e4 0x748 0x000 0x3 0x0
|
||||
#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO 0x2e4 0x748 0x7e8 0x4 0x3
|
||||
#define MX35_PAD_FEC_RX_CLK__GPIO3_7 0x2e4 0x748 0x910 0x5 0x1
|
||||
#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I 0x2e4 0x748 0x92c 0x6 0x4
|
||||
#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 0x2e4 0x748 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x2e8 0x74c 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 0x2e8 0x74c 0x80c 0x1 0x1
|
||||
#define MX35_PAD_FEC_RX_DV__UART3_RTS 0x2e8 0x74c 0x99c 0x2 0x2
|
||||
#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT 0x2e8 0x74c 0x9f0 0x3 0x1
|
||||
#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK 0x2e8 0x74c 0x7e0 0x4 0x3
|
||||
#define MX35_PAD_FEC_RX_DV__GPIO3_8 0x2e8 0x74c 0x914 0x5 0x1
|
||||
#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK 0x2e8 0x74c 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 0x2e8 0x74c 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_COL__FEC_COL 0x2ec 0x750 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_COL__ESDHC1_DAT7 0x2ec 0x750 0x810 0x1 0x1
|
||||
#define MX35_PAD_FEC_COL__UART3_CTS 0x2ec 0x750 0x000 0x2 0x0
|
||||
#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 0x2ec 0x750 0x9cc 0x3 0x1
|
||||
#define MX35_PAD_FEC_COL__CSPI2_RDY 0x2ec 0x750 0x7e4 0x4 0x3
|
||||
#define MX35_PAD_FEC_COL__GPIO3_9 0x2ec 0x750 0x918 0x5 0x1
|
||||
#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS 0x2ec 0x750 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 0x2ec 0x750 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x2f0 0x754 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_RDATA0__PWM_PWMO 0x2f0 0x754 0x000 0x1 0x0
|
||||
#define MX35_PAD_FEC_RDATA0__UART3_DTR 0x2f0 0x754 0x000 0x2 0x0
|
||||
#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 0x2f0 0x754 0x9d0 0x3 0x1
|
||||
#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 0x2f0 0x754 0x7f0 0x4 0x2
|
||||
#define MX35_PAD_FEC_RDATA0__GPIO3_10 0x2f0 0x754 0x8ec 0x5 0x1
|
||||
#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 0x2f0 0x754 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 0x2f0 0x754 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x2f4 0x758 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 0x2f4 0x758 0x000 0x1 0x0
|
||||
#define MX35_PAD_FEC_TDATA0__UART3_DSR 0x2f4 0x758 0x000 0x2 0x0
|
||||
#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 0x2f4 0x758 0x9d4 0x3 0x1
|
||||
#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 0x2f4 0x758 0x7f4 0x4 0x2
|
||||
#define MX35_PAD_FEC_TDATA0__GPIO3_11 0x2f4 0x758 0x8f0 0x5 0x1
|
||||
#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 0x2f4 0x758 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 0x2f4 0x758 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x2f8 0x75c 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 0x2f8 0x75c 0x998 0x1 0x3
|
||||
#define MX35_PAD_FEC_TX_EN__UART3_RI 0x2f8 0x75c 0x000 0x2 0x0
|
||||
#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 0x2f8 0x75c 0x9d8 0x3 0x1
|
||||
#define MX35_PAD_FEC_TX_EN__GPIO3_12 0x2f8 0x75c 0x8f4 0x5 0x1
|
||||
#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS 0x2f8 0x75c 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 0x2f8 0x75c 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_MDC__FEC_MDC 0x2fc 0x760 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_MDC__CAN2_TXCAN 0x2fc 0x760 0x000 0x1 0x0
|
||||
#define MX35_PAD_FEC_MDC__UART3_DCD 0x2fc 0x760 0x000 0x2 0x0
|
||||
#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 0x2fc 0x760 0x9dc 0x3 0x1
|
||||
#define MX35_PAD_FEC_MDC__GPIO3_13 0x2fc 0x760 0x8f8 0x5 0x1
|
||||
#define MX35_PAD_FEC_MDC__IPU_DISPB_WR 0x2fc 0x760 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 0x2fc 0x760 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_MDIO__FEC_MDIO 0x300 0x764 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_MDIO__CAN2_RXCAN 0x300 0x764 0x7cc 0x1 0x2
|
||||
#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 0x300 0x764 0x9e0 0x3 0x1
|
||||
#define MX35_PAD_FEC_MDIO__GPIO3_14 0x300 0x764 0x8fc 0x5 0x1
|
||||
#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD 0x300 0x764 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 0x300 0x764 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x304 0x768 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE 0x304 0x768 0x990 0x1 0x2
|
||||
#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK 0x304 0x768 0x994 0x2 0x4
|
||||
#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 0x304 0x768 0x9e4 0x3 0x1
|
||||
#define MX35_PAD_FEC_TX_ERR__GPIO3_15 0x304 0x768 0x900 0x5 0x1
|
||||
#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC 0x304 0x768 0x924 0x6 0x3
|
||||
#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 0x304 0x768 0x000 0x7 0x0
|
||||
#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x308 0x76c 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 0x308 0x76c 0x930 0x1 0x3
|
||||
#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 0x308 0x76c 0x9e8 0x3 0x1
|
||||
#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 0x308 0x76c 0x960 0x4 0x1
|
||||
#define MX35_PAD_FEC_RX_ERR__GPIO3_16 0x308 0x76c 0x000 0x5 0x0
|
||||
#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO 0x308 0x76c 0x92c 0x6 0x5
|
||||
#define MX35_PAD_FEC_CRS__FEC_CRS 0x30c 0x770 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 0x30c 0x770 0x934 0x1 0x3
|
||||
#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR 0x30c 0x770 0x000 0x3 0x0
|
||||
#define MX35_PAD_FEC_CRS__KPP_COL_5 0x30c 0x770 0x964 0x4 0x1
|
||||
#define MX35_PAD_FEC_CRS__GPIO3_17 0x30c 0x770 0x000 0x5 0x0
|
||||
#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE 0x30c 0x770 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x310 0x774 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 0x310 0x774 0x938 0x1 0x4
|
||||
#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC 0x310 0x774 0x000 0x2 0x0
|
||||
#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC 0x310 0x774 0x9f4 0x3 0x2
|
||||
#define MX35_PAD_FEC_RDATA1__KPP_COL_6 0x310 0x774 0x968 0x4 0x1
|
||||
#define MX35_PAD_FEC_RDATA1__GPIO3_18 0x310 0x774 0x000 0x5 0x0
|
||||
#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 0x310 0x774 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x314 0x778 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 0x314 0x778 0x93c 0x1 0x4
|
||||
#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS 0x314 0x778 0x7bc 0x2 0x1
|
||||
#define MX35_PAD_FEC_TDATA1__KPP_COL_7 0x314 0x778 0x96c 0x4 0x1
|
||||
#define MX35_PAD_FEC_TDATA1__GPIO3_19 0x314 0x778 0x000 0x5 0x0
|
||||
#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 0x314 0x778 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x318 0x77c 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 0x318 0x77c 0x940 0x1 0x3
|
||||
#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD 0x318 0x77c 0x7b4 0x2 0x1
|
||||
#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 0x318 0x77c 0x980 0x4 0x1
|
||||
#define MX35_PAD_FEC_RDATA2__GPIO3_20 0x318 0x77c 0x000 0x5 0x0
|
||||
#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x31c 0x780 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 0x31c 0x780 0x944 0x1 0x3
|
||||
#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD 0x31c 0x780 0x7b0 0x2 0x1
|
||||
#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 0x31c 0x780 0x984 0x4 0x1
|
||||
#define MX35_PAD_FEC_TDATA2__GPIO3_21 0x31c 0x780 0x000 0x5 0x0
|
||||
#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x320 0x784 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 0x320 0x784 0x948 0x1 0x3
|
||||
#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC 0x320 0x784 0x7c0 0x2 0x1
|
||||
#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 0x320 0x784 0x988 0x4 0x1
|
||||
#define MX35_PAD_FEC_RDATA3__GPIO3_22 0x320 0x784 0x000 0x6 0x0
|
||||
#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x324 0x788 0x000 0x0 0x0
|
||||
#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 0x324 0x788 0x94c 0x1 0x3
|
||||
#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS 0x324 0x788 0x7c4 0x2 0x1
|
||||
#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 0x324 0x788 0x98c 0x4 0x1
|
||||
#define MX35_PAD_FEC_TDATA3__GPIO3_23 0x324 0x788 0x000 0x5 0x0
|
||||
#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK 0x000 0x78c 0x000 0x0 0x0
|
||||
#define MX35_PAD_TEST_MODE__TCU_TEST_MODE 0x000 0x790 0x000 0x0 0x0
|
||||
|
||||
#endif /* __DTS_IMX35_PINFUNC_H */
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx51.dtsi"
|
||||
#include "imx51.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Armadeus Systems APF51 module";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Copyright 2013 Armadeus Systems - <support@armadeus.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/* APF51Dev is a docking board for the APF51 SOM */
|
||||
#include "imx51-apf51.dts"
|
||||
|
||||
/ {
|
||||
model = "Armadeus Systems APF51Dev docking/development board";
|
||||
compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
user-key {
|
||||
label = "user";
|
||||
gpios = <&gpio1 3 0>;
|
||||
linux,code = <256>; /* BTN_0 */
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio1 2 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio2 29 0>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2_1>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
|
||||
MX51_PAD_EIM_EB3__GPIO2_23 0x0C5
|
||||
MX51_PAD_EIM_CS4__GPIO2_29 0x100
|
||||
MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
|
||||
MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
|
||||
MX51_PAD_GPIO1_2__GPIO1_2 0x0C5
|
||||
MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx51.dtsi"
|
||||
#include "imx51.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX51 Babbage Board";
|
||||
|
|
@ -222,13 +222,13 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
|
||||
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
|
||||
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
|
||||
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
|
||||
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
|
||||
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
|
||||
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
|
||||
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
|
||||
MX51_PAD_GPIO1_1__SD1_WP 0x20d5
|
||||
MX51_PAD_GPIO1_5__GPIO1_5 0x100
|
||||
MX51_PAD_GPIO1_6__GPIO1_6 0x100
|
||||
MX51_PAD_EIM_A27__GPIO2_21 0x5
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
|
||||
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,773 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX51_PINFUNC_H
|
||||
#define __DTS_IMX51_PINFUNC_H
|
||||
|
||||
/*
|
||||
* The pin function ID is a tuple of
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
|
||||
#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
|
||||
#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
|
||||
#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
|
||||
#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
|
||||
#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
|
||||
#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0
|
||||
#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0
|
||||
#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
|
||||
#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
|
||||
#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0
|
||||
#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0
|
||||
#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0
|
||||
#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
|
||||
#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0
|
||||
#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0
|
||||
#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0
|
||||
#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
|
||||
#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0
|
||||
#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0
|
||||
#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0
|
||||
#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0
|
||||
#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0
|
||||
#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
|
||||
#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0
|
||||
#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0
|
||||
#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
|
||||
#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0
|
||||
#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
|
||||
#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
|
||||
#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0
|
||||
#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0
|
||||
#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
|
||||
#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0
|
||||
#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0
|
||||
#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0
|
||||
#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0
|
||||
#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0
|
||||
#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0
|
||||
#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0
|
||||
#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0
|
||||
#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0
|
||||
#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0
|
||||
#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0
|
||||
#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0
|
||||
#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0
|
||||
#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0
|
||||
#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0
|
||||
#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0
|
||||
#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0
|
||||
#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0
|
||||
#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0
|
||||
#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0
|
||||
#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1
|
||||
#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0
|
||||
#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0
|
||||
#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1
|
||||
#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0
|
||||
#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0
|
||||
#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1
|
||||
#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0
|
||||
#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0
|
||||
#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1
|
||||
#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0
|
||||
#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0
|
||||
#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0
|
||||
#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0
|
||||
#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0
|
||||
#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0
|
||||
#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0
|
||||
#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0
|
||||
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0
|
||||
#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0
|
||||
#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0
|
||||
#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0
|
||||
#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0
|
||||
#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0
|
||||
#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0
|
||||
#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0
|
||||
#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0
|
||||
#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0
|
||||
#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0
|
||||
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0
|
||||
#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0
|
||||
#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0
|
||||
#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0
|
||||
#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0
|
||||
#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0
|
||||
#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0
|
||||
#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0
|
||||
#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0
|
||||
#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0
|
||||
#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0
|
||||
#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0
|
||||
#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0
|
||||
#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0
|
||||
#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0
|
||||
#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1
|
||||
#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1
|
||||
#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1
|
||||
#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1
|
||||
#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1
|
||||
#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0
|
||||
#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0
|
||||
#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0
|
||||
#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0
|
||||
#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0
|
||||
#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0
|
||||
#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1
|
||||
#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0
|
||||
#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0
|
||||
#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0
|
||||
#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0
|
||||
#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0
|
||||
#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0
|
||||
#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0
|
||||
#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0
|
||||
#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0
|
||||
#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2
|
||||
#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0
|
||||
#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0
|
||||
#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0
|
||||
#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0
|
||||
#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0
|
||||
#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1
|
||||
#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1
|
||||
#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1
|
||||
#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1
|
||||
#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1
|
||||
#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0
|
||||
#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0
|
||||
#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1
|
||||
#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0
|
||||
#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0
|
||||
#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0
|
||||
#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0
|
||||
#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0
|
||||
#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0
|
||||
#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0
|
||||
#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0
|
||||
#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0
|
||||
#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0
|
||||
#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0
|
||||
#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2
|
||||
#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0
|
||||
#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0
|
||||
#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0
|
||||
#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0
|
||||
#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0
|
||||
#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0
|
||||
#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4
|
||||
#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0
|
||||
#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0
|
||||
#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0
|
||||
#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0
|
||||
#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0
|
||||
#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0
|
||||
#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0
|
||||
#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0
|
||||
#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0
|
||||
#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0
|
||||
#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1
|
||||
#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0
|
||||
#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0
|
||||
#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4
|
||||
#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1
|
||||
#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0
|
||||
#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0
|
||||
#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1
|
||||
#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2
|
||||
#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1
|
||||
#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2
|
||||
#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0
|
||||
#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6
|
||||
#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0
|
||||
#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0
|
||||
#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0
|
||||
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4
|
||||
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0
|
||||
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5
|
||||
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0
|
||||
#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0
|
||||
#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1
|
||||
#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0
|
||||
#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0
|
||||
#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1
|
||||
#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0
|
||||
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0
|
||||
#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0
|
||||
#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1
|
||||
#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1
|
||||
#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1
|
||||
#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0
|
||||
#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0
|
||||
#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1
|
||||
#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1
|
||||
#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0
|
||||
#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1
|
||||
#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0
|
||||
#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1
|
||||
#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1
|
||||
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0
|
||||
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0
|
||||
#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 0x2c8 0x6c8 0x000 0x2 0x0
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1
|
||||
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0
|
||||
#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0
|
||||
#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0
|
||||
#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0
|
||||
#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0
|
||||
#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0
|
||||
#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0
|
||||
#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1
|
||||
#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1
|
||||
#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0
|
||||
#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0
|
||||
#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1
|
||||
#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1
|
||||
#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0
|
||||
#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1
|
||||
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0
|
||||
#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1
|
||||
#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0
|
||||
#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1
|
||||
#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0
|
||||
#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1
|
||||
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1
|
||||
#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8
|
||||
#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1
|
||||
#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0
|
||||
#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0
|
||||
#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0
|
||||
#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0
|
||||
#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1
|
||||
#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1
|
||||
#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0
|
||||
#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1
|
||||
#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1
|
||||
#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1
|
||||
#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1
|
||||
#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1
|
||||
#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0
|
||||
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0
|
||||
#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0
|
||||
#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1
|
||||
#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1
|
||||
#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2
|
||||
#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1
|
||||
#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2
|
||||
#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2
|
||||
#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1
|
||||
#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2
|
||||
#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2
|
||||
#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2
|
||||
#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1
|
||||
#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0
|
||||
#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0
|
||||
#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2
|
||||
#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0
|
||||
#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3
|
||||
#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2
|
||||
#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3
|
||||
#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2
|
||||
#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3
|
||||
#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0
|
||||
#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0
|
||||
#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0
|
||||
#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0
|
||||
#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0
|
||||
#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0
|
||||
#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1
|
||||
#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0
|
||||
#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0
|
||||
#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3
|
||||
#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1
|
||||
#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0
|
||||
#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3
|
||||
#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1
|
||||
#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0
|
||||
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0
|
||||
#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0
|
||||
#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1
|
||||
#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1
|
||||
#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0
|
||||
#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0
|
||||
#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0
|
||||
#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0
|
||||
#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0
|
||||
#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0
|
||||
#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0
|
||||
#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0
|
||||
#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0
|
||||
#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2
|
||||
#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0
|
||||
#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0
|
||||
#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0
|
||||
#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0
|
||||
#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0
|
||||
#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0
|
||||
#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0
|
||||
#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0
|
||||
|
||||
#endif /* __DTS_IMX51_PINFUNC_H */
|
||||
|
|
@ -10,7 +10,8 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
#include "imx51-pinfunc.h"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -55,6 +56,24 @@
|
|||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks 24>;
|
||||
clock-names = "cpu";
|
||||
operating-points = <
|
||||
/* kHz uV (No regulator support) */
|
||||
160000 0
|
||||
800000 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -67,6 +86,9 @@
|
|||
compatible = "fsl,imx51-ipu";
|
||||
reg = <0x40000000 0x20000000>;
|
||||
interrupts = <11 10>;
|
||||
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
};
|
||||
|
||||
aips@70000000 { /* AIPS1 */
|
||||
|
|
@ -244,6 +266,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt: timer@73fa0000 {
|
||||
compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x73fa0000 0x4000>;
|
||||
interrupts = <39>;
|
||||
clocks = <&clks 36>, <&clks 41>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
|
|
@ -251,10 +281,10 @@
|
|||
audmux {
|
||||
pinctrl_audmux_1: audmuxgrp-1 {
|
||||
fsl,pins = <
|
||||
384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
|
||||
386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
|
||||
389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
|
||||
391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -262,46 +292,46 @@
|
|||
fec {
|
||||
pinctrl_fec_1: fecgrp-1 {
|
||||
fsl,pins = <
|
||||
128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
|
||||
134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
|
||||
146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
|
||||
152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
|
||||
158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
|
||||
165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
|
||||
206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
|
||||
213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
|
||||
293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
|
||||
298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
|
||||
225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
|
||||
231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
|
||||
237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
|
||||
243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
|
||||
250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
|
||||
255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
|
||||
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
|
||||
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
|
||||
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
|
||||
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
|
||||
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
|
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
|
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec_2: fecgrp-2 {
|
||||
fsl,pins = <
|
||||
589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
|
||||
592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
|
||||
594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
|
||||
596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
|
||||
598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
|
||||
602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
|
||||
604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
|
||||
609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
|
||||
618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
|
||||
623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
|
||||
628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
|
||||
634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
|
||||
639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
|
||||
644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
|
||||
649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
|
||||
653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
|
||||
657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
|
||||
662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -309,9 +339,19 @@
|
|||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
|
||||
394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
|
||||
409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi2 {
|
||||
pinctrl_ecspi2_1: ecspi2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
|
||||
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
|
||||
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -319,12 +359,12 @@
|
|||
esdhc1 {
|
||||
pinctrl_esdhc1_1: esdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
|
||||
669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
|
||||
672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
|
||||
678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
|
||||
684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
|
||||
691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -332,12 +372,12 @@
|
|||
esdhc2 {
|
||||
pinctrl_esdhc2_1: esdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
|
||||
707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
|
||||
710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
|
||||
712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
|
||||
715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
|
||||
719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -345,8 +385,15 @@
|
|||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
|
||||
454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
|
||||
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_2: i2c2grp-2 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -354,32 +401,32 @@
|
|||
ipu_disp1 {
|
||||
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
|
||||
fsl,pins = <
|
||||
528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
|
||||
529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
|
||||
530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
|
||||
531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
|
||||
532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
|
||||
533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
|
||||
535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
|
||||
537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
|
||||
539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
|
||||
541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
|
||||
543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
|
||||
545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
|
||||
547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
|
||||
549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
|
||||
551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
|
||||
553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
|
||||
555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
|
||||
557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
|
||||
559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
|
||||
563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
|
||||
567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
|
||||
571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
|
||||
575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
|
||||
579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
|
||||
584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
|
||||
583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -387,26 +434,62 @@
|
|||
ipu_disp2 {
|
||||
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
|
||||
fsl,pins = <
|
||||
603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
|
||||
608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
|
||||
613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
|
||||
614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
|
||||
615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
|
||||
616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
|
||||
617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
|
||||
622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
|
||||
627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
|
||||
633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
|
||||
637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
|
||||
643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
|
||||
648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
|
||||
652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
|
||||
656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
|
||||
661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
|
||||
593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
|
||||
595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
|
||||
597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
|
||||
599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
|
||||
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
|
||||
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
|
||||
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
|
||||
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
|
||||
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
|
||||
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
|
||||
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
|
||||
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
|
||||
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
|
||||
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
|
||||
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
|
||||
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
|
||||
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
|
||||
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
|
||||
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
|
||||
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
|
||||
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
|
||||
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
|
||||
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
|
||||
MX51_PAD_DI_GP4__DI2_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pata {
|
||||
pinctrl_pata_1: patagrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
|
||||
MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
|
||||
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
|
||||
MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
|
||||
MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
|
||||
MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
|
||||
MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
|
||||
MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
|
||||
MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
|
||||
MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
|
||||
MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
|
||||
MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
|
||||
MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
|
||||
MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
|
||||
MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
|
||||
MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
|
||||
MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
|
||||
MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
|
||||
MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
|
||||
MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
|
||||
MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
|
||||
MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
|
||||
MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
|
||||
MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
|
||||
MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
|
||||
MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
|
||||
MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
|
||||
MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
|
||||
MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -414,10 +497,10 @@
|
|||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
|
||||
416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
|
||||
418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
|
||||
420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
|
||||
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -425,8 +508,8 @@
|
|||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
|
||||
426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -434,17 +517,17 @@
|
|||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
|
||||
59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
|
||||
65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
|
||||
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
|
||||
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
|
||||
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
|
||||
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
|
||||
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_2: uart3grp-2 {
|
||||
fsl,pins = <
|
||||
434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */
|
||||
430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -452,14 +535,14 @@
|
|||
kpp {
|
||||
pinctrl_kpp_1: kppgrp-1 {
|
||||
fsl,pins = <
|
||||
438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
|
||||
439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
|
||||
440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
|
||||
441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
|
||||
442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */
|
||||
444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */
|
||||
446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */
|
||||
448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
|
||||
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
|
||||
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
|
||||
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
|
||||
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -501,6 +584,12 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
src: src@73fd0000 {
|
||||
compatible = "fsl,imx51-src";
|
||||
reg = <0x73fd0000 0x4000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@73fd4000{
|
||||
compatible = "fsl,imx51-ccm";
|
||||
reg = <0x73fd4000 0x4000>;
|
||||
|
|
@ -591,6 +680,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pata: pata@83fe0000 {
|
||||
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
|
||||
reg = <0x83fe0000 0x4000>;
|
||||
interrupts = <70>;
|
||||
clocks = <&clks 161>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi3: ssi@83fe8000 {
|
||||
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x83fe8000 0x4000>;
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53.dtsi"
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Automotive Reference Design Board";
|
||||
|
|
@ -112,40 +112,40 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
|
||||
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
|
||||
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
|
||||
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
|
||||
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
|
||||
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
|
||||
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
|
||||
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
|
||||
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
|
||||
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
|
||||
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
|
||||
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
|
||||
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
|
||||
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
|
||||
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
|
||||
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
|
||||
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
|
||||
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
|
||||
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
|
||||
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
|
||||
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
|
||||
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
|
||||
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
|
||||
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
|
||||
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
|
||||
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
|
||||
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
|
||||
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
|
||||
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
|
||||
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
|
||||
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
|
||||
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
|
||||
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
|
||||
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
|
||||
MX53_PAD_GPIO_1__GPIO1_1 0x80000000
|
||||
MX53_PAD_GPIO_9__GPIO1_9 0x80000000
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
|
||||
MX53_PAD_GPIO_10__GPIO4_0 0x80000000
|
||||
MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000
|
||||
MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000
|
||||
MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000
|
||||
MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000
|
||||
MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000
|
||||
MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000
|
||||
MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000
|
||||
MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000
|
||||
MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000
|
||||
MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000
|
||||
MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000
|
||||
MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000
|
||||
MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000
|
||||
MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000
|
||||
MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000
|
||||
MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000
|
||||
MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000
|
||||
MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000
|
||||
MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000
|
||||
MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000
|
||||
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000
|
||||
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000
|
||||
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000
|
||||
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000
|
||||
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000
|
||||
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000
|
||||
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000
|
||||
MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
|
||||
MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
|
||||
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53.dtsi"
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Evaluation Kit";
|
||||
|
|
@ -82,14 +82,14 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
|
||||
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
|
||||
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
|
||||
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
|
||||
MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
|
||||
MX53_PAD_EIM_D19__GPIO3_19 0x80000000
|
||||
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
|
||||
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
|
||||
MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53-tqma53.dtsi"
|
||||
#include "imx53-tqma53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ MBa53 starter kit";
|
||||
|
|
@ -21,51 +21,57 @@
|
|||
&iomuxc {
|
||||
lvds1 {
|
||||
pinctrl_lvds1_1: lvds1-grp1 {
|
||||
fsl,pins = <730 0x10000 /* LVDS0_TX3 */
|
||||
732 0x10000 /* LVDS0_CLK */
|
||||
734 0x10000 /* LVDS0_TX2 */
|
||||
736 0x10000 /* LVDS0_TX1 */
|
||||
738 0x10000>; /* LVDS0_TX0 */
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
|
||||
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
|
||||
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
|
||||
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
|
||||
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lvds1_2: lvds1-grp2 {
|
||||
fsl,pins = <720 0x10000 /* LVDS1_TX3 */
|
||||
722 0x10000 /* LVDS1_TX2 */
|
||||
724 0x10000 /* LVDS1_CLK */
|
||||
726 0x10000 /* LVDS1_TX1 */
|
||||
728 0x10000>; /* LVDS1_TX0 */
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
|
||||
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
|
||||
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
|
||||
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
|
||||
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
disp1 {
|
||||
pinctrl_disp1_1: disp1-grp1 {
|
||||
fsl,pins = <689 0x10000 /* DISP1_DRDY */
|
||||
482 0x10000 /* DISP1_HSYNC */
|
||||
489 0x10000 /* DISP1_VSYNC */
|
||||
515 0x10000 /* DISP1_DAT_22 */
|
||||
523 0x10000 /* DISP1_DAT_23 */
|
||||
545 0x10000 /* DISP1_DAT_21 */
|
||||
553 0x10000 /* DISP1_DAT_20 */
|
||||
558 0x10000 /* DISP1_DAT_19 */
|
||||
564 0x10000 /* DISP1_DAT_18 */
|
||||
570 0x10000 /* DISP1_DAT_17 */
|
||||
575 0x10000 /* DISP1_DAT_16 */
|
||||
580 0x10000 /* DISP1_DAT_15 */
|
||||
585 0x10000 /* DISP1_DAT_14 */
|
||||
590 0x10000 /* DISP1_DAT_13 */
|
||||
595 0x10000 /* DISP1_DAT_12 */
|
||||
628 0x10000 /* DISP1_DAT_11 */
|
||||
634 0x10000 /* DISP1_DAT_10 */
|
||||
639 0x10000 /* DISP1_DAT_9 */
|
||||
644 0x10000 /* DISP1_DAT_8 */
|
||||
649 0x10000 /* DISP1_DAT_7 */
|
||||
654 0x10000 /* DISP1_DAT_6 */
|
||||
659 0x10000 /* DISP1_DAT_5 */
|
||||
664 0x10000 /* DISP1_DAT_4 */
|
||||
669 0x10000 /* DISP1_DAT_3 */
|
||||
674 0x10000 /* DISP1_DAT_2 */
|
||||
679 0x10000 /* DISP1_DAT_1 */
|
||||
684 0x10000>; /* DISP1_DAT_0 */
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */
|
||||
MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */
|
||||
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */
|
||||
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
|
||||
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
|
||||
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
|
||||
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
|
||||
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
|
||||
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
|
||||
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
|
||||
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
|
||||
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
|
||||
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
|
||||
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
|
||||
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
|
||||
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
|
||||
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
|
||||
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000
|
||||
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000
|
||||
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000
|
||||
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000
|
||||
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000
|
||||
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000
|
||||
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000
|
||||
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000
|
||||
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000
|
||||
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53.dtsi"
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Quick Start Board";
|
||||
|
|
@ -110,21 +110,21 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
|
||||
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
|
||||
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
|
||||
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
|
||||
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
|
||||
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
|
||||
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
|
||||
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
|
||||
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
|
||||
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
|
||||
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
led_pin_gpio7_7: led_gpio7_7@0 {
|
||||
fsl,pins = <
|
||||
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
|
||||
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx53.dtsi"
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX53 Smart Mobile Reference Design Board";
|
||||
|
|
@ -107,13 +107,13 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
|
||||
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
|
||||
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
|
||||
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
|
||||
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
|
||||
MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
|
||||
MX53_PAD_EIM_D19__GPIO3_19 0x80000000
|
||||
MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "imx53.dtsi"
|
||||
#include "imx53.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ TQMa53";
|
||||
|
|
@ -72,11 +72,11 @@
|
|||
i2s {
|
||||
pinctrl_i2s_1: i2s-grp1 {
|
||||
fsl,pins = <
|
||||
1 0x10000 /* I2S_MCLK */
|
||||
10 0x10000 /* I2S_SCLK */
|
||||
17 0x10000 /* I2S_DOUT */
|
||||
23 0x10000 /* I2S_LRCLK*/
|
||||
30 0x10000 /* I2S_DIN */
|
||||
MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */
|
||||
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */
|
||||
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */
|
||||
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
|
||||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -84,16 +84,16 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
610 0x10000 /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/
|
||||
711 0x10000 /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/
|
||||
873 0x10000 /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/
|
||||
878 0x10000 /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/
|
||||
922 0x10000 /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/
|
||||
928 0x10000 /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/
|
||||
982 0x10000 /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/
|
||||
989 0x10000 /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/
|
||||
1069 0x10000 /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/
|
||||
1093 0x10000 /* MX53_PAD_GPIO_3__GPIO1_3 */
|
||||
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */
|
||||
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
|
||||
MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */
|
||||
MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */
|
||||
MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */
|
||||
MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */
|
||||
MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */
|
||||
MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */
|
||||
MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */
|
||||
MX53_PAD_GPIO_3__GPIO1_3 0x10000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,7 +10,8 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
#include "imx53-pinfunc.h"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -72,6 +73,9 @@
|
|||
compatible = "fsl,imx53-ipu";
|
||||
reg = <0x18000000 0x080000000>;
|
||||
interrupts = <11 10>;
|
||||
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
};
|
||||
|
||||
aips@50000000 { /* AIPS1 */
|
||||
|
|
@ -242,6 +246,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpt: timer@53fa0000 {
|
||||
compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x53fa0000 0x4000>;
|
||||
interrupts = <39>;
|
||||
clocks = <&clks 36>, <&clks 41>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
|
|
@ -249,10 +261,10 @@
|
|||
audmux {
|
||||
pinctrl_audmux_1: audmuxgrp-1 {
|
||||
fsl,pins = <
|
||||
10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
|
||||
17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
|
||||
23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
|
||||
30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
|
||||
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
|
||||
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
|
||||
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
|
||||
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -260,16 +272,16 @@
|
|||
fec {
|
||||
pinctrl_fec_1: fecgrp-1 {
|
||||
fsl,pins = <
|
||||
820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
|
||||
779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
|
||||
786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
|
||||
791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
|
||||
796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
|
||||
799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
|
||||
804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
|
||||
808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
|
||||
811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
|
||||
816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -277,27 +289,27 @@
|
|||
csi {
|
||||
pinctrl_csi_1: csigrp-1 {
|
||||
fsl,pins = <
|
||||
286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
|
||||
291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
|
||||
280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
|
||||
276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
|
||||
409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
|
||||
402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
|
||||
395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
|
||||
388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
|
||||
381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
|
||||
374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
|
||||
367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
|
||||
360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
|
||||
352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
|
||||
344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
|
||||
336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
|
||||
328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
|
||||
320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
|
||||
312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
|
||||
304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
|
||||
296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
|
||||
276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
|
||||
MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
|
||||
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
|
||||
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
|
||||
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
|
||||
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
|
||||
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
|
||||
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
|
||||
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
|
||||
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
|
||||
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
|
||||
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
|
||||
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
|
||||
MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
|
||||
MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
|
||||
MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
|
||||
MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
|
||||
MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
|
||||
MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
|
||||
MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
|
||||
MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
|
||||
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -305,9 +317,9 @@
|
|||
cspi {
|
||||
pinctrl_cspi_1: cspigrp-1 {
|
||||
fsl,pins = <
|
||||
998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */
|
||||
1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */
|
||||
1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */
|
||||
MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
|
||||
MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
|
||||
MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -315,9 +327,9 @@
|
|||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
|
||||
439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
|
||||
445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
|
||||
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
|
||||
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
|
||||
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -325,27 +337,27 @@
|
|||
esdhc1 {
|
||||
pinctrl_esdhc1_1: esdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
|
||||
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
|
||||
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
|
||||
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
|
||||
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
|
||||
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1_2: esdhc1grp-2 {
|
||||
fsl,pins = <
|
||||
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
|
||||
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
|
||||
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
|
||||
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
|
||||
941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
|
||||
948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
|
||||
955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
|
||||
962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
|
||||
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
|
||||
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
|
||||
MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
|
||||
MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
|
||||
MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -353,12 +365,12 @@
|
|||
esdhc2 {
|
||||
pinctrl_esdhc2_1: esdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
|
||||
1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
|
||||
1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
|
||||
1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
|
||||
1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
|
||||
1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
|
||||
MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
|
||||
MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
|
||||
MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
|
||||
MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
|
||||
MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
|
||||
MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -366,16 +378,16 @@
|
|||
esdhc3 {
|
||||
pinctrl_esdhc3_1: esdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
|
||||
950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
|
||||
957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
|
||||
964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
|
||||
893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
|
||||
900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
|
||||
906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
|
||||
912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
|
||||
857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
|
||||
863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
|
||||
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
|
||||
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
|
||||
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
|
||||
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
|
||||
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
|
||||
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
|
||||
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
|
||||
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
|
||||
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
|
||||
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -383,15 +395,15 @@
|
|||
can1 {
|
||||
pinctrl_can1_1: can1grp-1 {
|
||||
fsl,pins = <
|
||||
847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
|
||||
853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
|
||||
MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
|
||||
MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1_2: can1grp-2 {
|
||||
fsl,pins = <
|
||||
37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
|
||||
44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
|
||||
MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
|
||||
MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -399,8 +411,8 @@
|
|||
can2 {
|
||||
pinctrl_can2_1: can2grp-1 {
|
||||
fsl,pins = <
|
||||
67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
|
||||
74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
|
||||
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
|
||||
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -408,8 +420,8 @@
|
|||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
|
||||
341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
|
||||
MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
|
||||
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -417,8 +429,8 @@
|
|||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
|
||||
53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
|
||||
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
|
||||
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -426,8 +438,8 @@
|
|||
i2c3 {
|
||||
pinctrl_i2c3_1: i2c3grp-1 {
|
||||
fsl,pins = <
|
||||
1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
|
||||
1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
|
||||
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -435,7 +447,7 @@
|
|||
owire {
|
||||
pinctrl_owire_1: owiregrp-1 {
|
||||
fsl,pins = <
|
||||
1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
|
||||
MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -443,15 +455,15 @@
|
|||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
|
||||
354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
|
||||
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
|
||||
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_2: uart1grp-2 {
|
||||
fsl,pins = <
|
||||
828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
|
||||
832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -459,8 +471,8 @@
|
|||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
|
||||
836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -468,17 +480,17 @@
|
|||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
|
||||
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
|
||||
875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
|
||||
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
|
||||
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
|
||||
MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_2: uart3grp-2 {
|
||||
fsl,pins = <
|
||||
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
|
||||
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
|
||||
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
|
||||
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -487,8 +499,8 @@
|
|||
uart4 {
|
||||
pinctrl_uart4_1: uart4grp-1 {
|
||||
fsl,pins = <
|
||||
11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
|
||||
18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
|
||||
MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
|
||||
MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -496,14 +508,46 @@
|
|||
uart5 {
|
||||
pinctrl_uart5_1: uart5grp-1 {
|
||||
fsl,pins = <
|
||||
24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
|
||||
31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
|
||||
MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
|
||||
MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-gpr", "syscon";
|
||||
reg = <0x53fa8000 0xc>;
|
||||
};
|
||||
|
||||
ldb: ldb@53fa8008 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ldb";
|
||||
reg = <0x53fa8008 0x4>;
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks 122>, <&clks 120>,
|
||||
<&clks 115>, <&clks 116>,
|
||||
<&clks 123>, <&clks 85>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel",
|
||||
"di0", "di1";
|
||||
status = "disabled";
|
||||
|
||||
lvds-channel@0 {
|
||||
reg = <0>;
|
||||
crtcs = <&ipu 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
reg = <1>;
|
||||
crtcs = <&ipu 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pwm1: pwm@53fb4000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
|
|
@ -558,6 +602,12 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
src: src@53fd0000 {
|
||||
compatible = "fsl,imx53-src", "fsl,imx51-src";
|
||||
reg = <0x53fd0000 0x4000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-sabreauto.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
|
||||
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
|
||||
MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-sabresd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
|
||||
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000
|
||||
MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000
|
||||
MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
|
||||
MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
|
||||
MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
|
||||
MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Dual Lite Board";
|
||||
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
|
|
@ -7,7 +8,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/include/ "imx6qdl.dtsi"
|
||||
#include "imx6qdl.dtsi"
|
||||
#include "imx6dl-pinfunc.h"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
|
|
@ -29,6 +31,127 @@
|
|||
|
||||
soc {
|
||||
aips1: aips-bus@02000000 {
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
compatible = "fsl,imx6dl-iomuxc";
|
||||
reg = <0x020e0000 0x4000>;
|
||||
|
||||
enet {
|
||||
pinctrl_enet_1: enetgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_2: enetgrp-2 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
pinctrl_uart4_1: uart4grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg {
|
||||
pinctrl_usbotg_2: usbotggrp-2 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc2 {
|
||||
pinctrl_usdhc2_1: usdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
|
||||
MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
|
||||
MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
|
||||
MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_2: usdhc3grp_2 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
};
|
||||
|
||||
pxp: pxp@020f0000 {
|
||||
reg = <0x020f0000 0x4000>;
|
||||
interrupts = <0 98 0x04>;
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx6q.dtsi"
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad Armadillo2 Board";
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
|
||||
MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -65,8 +65,8 @@
|
|||
arm2 {
|
||||
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
|
||||
fsl,pins = <
|
||||
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
|
||||
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
|
||||
MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
|
||||
MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -11,15 +11,13 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx6q.dtsi"
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-sabreauto.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad SABRE Automotive Board";
|
||||
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
|
|
@ -29,30 +27,9 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
|
||||
13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
|
||||
MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
|
||||
MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_2>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_1>;
|
||||
cd-gpios = <&gpio6 15 0>;
|
||||
wp-gpios = <&gpio1 13 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx6q.dtsi"
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad SABRE Lite Board";
|
||||
|
|
@ -91,14 +91,14 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
|
||||
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
|
||||
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
|
||||
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
|
||||
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
|
||||
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
|
||||
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
|
||||
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
|
||||
MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
|
||||
MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
|
||||
MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||||
MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
|
||||
MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
|
||||
MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
|
||||
MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
|
||||
MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,37 +11,13 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx6q.dtsi"
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-sabresd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6Q SABRE Smart Device Board";
|
||||
model = "Freescale i.MX6 Quad SABRE Smart Device Board";
|
||||
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio1 4 0>;
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 5 0>;
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
|
|
@ -51,36 +27,13 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
|
||||
1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
|
||||
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
|
||||
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
|
||||
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
|
||||
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
|
||||
MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000
|
||||
MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000
|
||||
MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
|
||||
MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
|
||||
MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
|
||||
MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2_1>;
|
||||
cd-gpios = <&gpio2 2 0>;
|
||||
wp-gpios = <&gpio2 3 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_1>;
|
||||
cd-gpios = <&gpio2 0 0>;
|
||||
wp-gpios = <&gpio2 1 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright 2013 Pavel Machek <pavel@denx.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License V2.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MicroSys sbc6x board";
|
||||
compatible = "microsys,sbc6x", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg_1>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -8,7 +8,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/include/ "imx6qdl.dtsi"
|
||||
#include "imx6qdl.dtsi"
|
||||
#include "imx6q-pinfunc.h"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
|
|
@ -78,10 +79,19 @@
|
|||
audmux {
|
||||
pinctrl_audmux_1: audmux-1 {
|
||||
fsl,pins = <
|
||||
18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
|
||||
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
|
||||
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
|
||||
3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
|
||||
MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
|
||||
MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
|
||||
MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
|
||||
MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux_2: audmux-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
|
||||
MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
|
||||
MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
|
||||
MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -89,9 +99,19 @@
|
|||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
|
||||
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
|
||||
94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
|
||||
MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi3 {
|
||||
pinctrl_ecspi3_1: ecspi3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
|
||||
MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
|
||||
MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -99,42 +119,42 @@
|
|||
enet {
|
||||
pinctrl_enet_1: enetgrp-1 {
|
||||
fsl,pins = <
|
||||
695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
|
||||
756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
|
||||
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
|
||||
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
|
||||
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
|
||||
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
|
||||
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
|
||||
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
|
||||
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
|
||||
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
|
||||
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
|
||||
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
|
||||
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
|
||||
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
|
||||
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
|
||||
1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
|
||||
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_2: enetgrp-2 {
|
||||
fsl,pins = <
|
||||
890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
|
||||
909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
|
||||
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
|
||||
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
|
||||
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
|
||||
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
|
||||
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
|
||||
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
|
||||
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
|
||||
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
|
||||
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
|
||||
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
|
||||
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
|
||||
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
|
||||
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
|
||||
MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -142,25 +162,25 @@
|
|||
gpmi-nand {
|
||||
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
||||
fsl,pins = <
|
||||
1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
|
||||
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
|
||||
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
|
||||
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
|
||||
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
|
||||
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
|
||||
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
|
||||
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
|
||||
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
|
||||
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
|
||||
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
|
||||
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
|
||||
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
|
||||
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
|
||||
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
|
||||
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
|
||||
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
|
||||
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
|
||||
1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
|
||||
MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
|
||||
MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
|
||||
MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -168,8 +188,26 @@
|
|||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
|
||||
196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
|
||||
MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
pinctrl_i2c3_1: i2c3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
|
||||
MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -177,8 +215,8 @@
|
|||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
|
||||
1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
|
||||
MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -186,8 +224,8 @@
|
|||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
|
||||
191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
|
||||
MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -195,8 +233,8 @@
|
|||
uart4 {
|
||||
pinctrl_uart4_1: uart4grp-1 {
|
||||
fsl,pins = <
|
||||
877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
|
||||
885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
|
||||
MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -204,7 +242,13 @@
|
|||
usbotg {
|
||||
pinctrl_usbotg_1: usbotggrp-1 {
|
||||
fsl,pins = <
|
||||
1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
|
||||
MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg_2: usbotggrp-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -212,16 +256,16 @@
|
|||
usdhc2 {
|
||||
pinctrl_usdhc2_1: usdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
|
||||
1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
|
||||
16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
|
||||
0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
|
||||
8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
|
||||
1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
|
||||
1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
|
||||
1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
|
||||
1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
|
||||
1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
|
||||
MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
|
||||
MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
|
||||
MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
|
||||
MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -229,27 +273,27 @@
|
|||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
||||
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
||||
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
||||
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
||||
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
||||
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
||||
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
|
||||
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
|
||||
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
|
||||
1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
|
||||
MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_2: usdhc3grp-2 {
|
||||
fsl,pins = <
|
||||
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
||||
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
||||
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
||||
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
||||
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
||||
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
||||
MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -257,27 +301,27 @@
|
|||
usdhc4 {
|
||||
pinctrl_usdhc4_1: usdhc4grp-1 {
|
||||
fsl,pins = <
|
||||
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
||||
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
||||
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
||||
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
||||
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
||||
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
||||
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
|
||||
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
|
||||
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
|
||||
1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
|
||||
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
||||
MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
||||
MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
||||
MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_2: usdhc4grp-2 {
|
||||
fsl,pins = <
|
||||
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
||||
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
||||
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
||||
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
||||
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
||||
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
||||
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -291,6 +335,24 @@
|
|||
interrupts = <0 8 0x4 0 7 0x4>;
|
||||
clocks = <&clks 133>, <&clks 134>, <&clks 137>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
clocks = <&clks 33>, <&clks 34>,
|
||||
<&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
|
||||
<&clks 135>, <&clks 136>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
|
||||
"di0", "di1";
|
||||
|
||||
lvds-channel@0 {
|
||||
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_2>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_1>;
|
||||
cd-gpios = <&gpio6 15 0>;
|
||||
wp-gpios = <&gpio1 13 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_usb_otg_vbus: usb_otg_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio1 4 0>;
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 5 0>;
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg_2>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2_1>;
|
||||
cd-gpios = <&gpio2 2 0>;
|
||||
wp-gpios = <&gpio2 3 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_1>;
|
||||
cd-gpios = <&gpio2 0 0>;
|
||||
wp-gpios = <&gpio2 1 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -101,6 +101,11 @@
|
|||
cache-level = <2>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 94 0x04>;
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -277,6 +282,8 @@
|
|||
compatible = "fsl,imx6q-gpt";
|
||||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <0 55 0x04>;
|
||||
clocks = <&clks 119>, <&clks 120>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpio1: gpio@0209c000 {
|
||||
|
|
@ -513,9 +520,10 @@
|
|||
};
|
||||
|
||||
src: src@020d8000 {
|
||||
compatible = "fsl,imx6q-src";
|
||||
compatible = "fsl,imx6q-src", "fsl,imx51-src";
|
||||
reg = <0x020d8000 0x4000>;
|
||||
interrupts = <0 91 0x04 0 96 0x04>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpc: gpc@020dc000 {
|
||||
|
|
@ -529,6 +537,26 @@
|
|||
reg = <0x020e0000 0x38>;
|
||||
};
|
||||
|
||||
ldb: ldb@020e0008 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
|
||||
gpr = <&gpr>;
|
||||
status = "disabled";
|
||||
|
||||
lvds-channel@0 {
|
||||
reg = <0>;
|
||||
crtcs = <&ipu1 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
reg = <1>;
|
||||
crtcs = <&ipu1 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dcic1: dcic@020e4000 {
|
||||
reg = <0x020e4000 0x4000>;
|
||||
interrupts = <0 124 0x04>;
|
||||
|
|
@ -795,6 +823,7 @@
|
|||
interrupts = <0 6 0x4 0 5 0x4>;
|
||||
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1 @@
|
|||
../../../../../include/dt-bindings
|
||||
|
|
@ -385,7 +385,7 @@
|
|||
|
||||
spi@7000d800 {
|
||||
compatible = "nvidia,tegra20-slink";
|
||||
reg = <0x7000d480 0x200>;
|
||||
reg = <0x7000d800 0x200>;
|
||||
interrupts = <0 83 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 17>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -372,7 +372,7 @@
|
|||
|
||||
spi@7000d800 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000d480 0x200>;
|
||||
reg = <0x7000d800 0x200>;
|
||||
interrupts = <0 83 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 17>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -480,7 +480,7 @@ static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
|
|||
evt->features = CLOCK_EVT_FEAT_ONESHOT |
|
||||
CLOCK_EVT_FEAT_PERIODIC |
|
||||
CLOCK_EVT_FEAT_DUMMY;
|
||||
evt->rating = 400;
|
||||
evt->rating = 100;
|
||||
evt->mult = 1;
|
||||
evt->set_mode = broadcast_timer_set_mode;
|
||||
|
||||
|
|
|
|||
|
|
@ -14,31 +14,15 @@
|
|||
|
||||
.text
|
||||
.align 5
|
||||
.word 0
|
||||
|
||||
1: subs r2, r2, #4 @ 1 do we have enough
|
||||
blt 5f @ 1 bytes to align with?
|
||||
cmp r3, #2 @ 1
|
||||
strltb r1, [ip], #1 @ 1
|
||||
strleb r1, [ip], #1 @ 1
|
||||
strb r1, [ip], #1 @ 1
|
||||
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
|
||||
/*
|
||||
* The pointer is now aligned and the length is adjusted. Try doing the
|
||||
* memset again.
|
||||
*/
|
||||
|
||||
ENTRY(memset)
|
||||
/*
|
||||
* Preserve the contents of r0 for the return value.
|
||||
*/
|
||||
mov ip, r0
|
||||
ands r3, ip, #3 @ 1 unaligned?
|
||||
bne 1b @ 1
|
||||
ands r3, r0, #3 @ 1 unaligned?
|
||||
mov ip, r0 @ preserve r0 as return value
|
||||
bne 6f @ 1
|
||||
/*
|
||||
* we know that the pointer in ip is aligned to a word boundary.
|
||||
*/
|
||||
orr r1, r1, r1, lsl #8
|
||||
1: orr r1, r1, r1, lsl #8
|
||||
orr r1, r1, r1, lsl #16
|
||||
mov r3, r1
|
||||
cmp r2, #16
|
||||
|
|
@ -127,4 +111,13 @@ ENTRY(memset)
|
|||
tst r2, #1
|
||||
strneb r1, [ip], #1
|
||||
mov pc, lr
|
||||
|
||||
6: subs r2, r2, #4 @ 1 do we have enough
|
||||
blt 5b @ 1 bytes to align with?
|
||||
cmp r3, #2 @ 1
|
||||
strltb r1, [ip], #1 @ 1
|
||||
strleb r1, [ip], #1 @ 1
|
||||
strb r1, [ip], #1 @ 1
|
||||
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
|
||||
b 1b
|
||||
ENDPROC(memset)
|
||||
|
|
|
|||
|
|
@ -209,6 +209,14 @@ extern int at91_get_gpio_value(unsigned pin);
|
|||
extern void at91_gpio_suspend(void);
|
||||
extern void at91_gpio_resume(void);
|
||||
|
||||
#ifdef CONFIG_PINCTRL_AT91
|
||||
extern void at91_pinctrl_gpio_suspend(void);
|
||||
extern void at91_pinctrl_gpio_resume(void);
|
||||
#else
|
||||
static inline void at91_pinctrl_gpio_suspend(void) {}
|
||||
static inline void at91_pinctrl_gpio_resume(void) {}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -92,23 +92,21 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
|
|||
|
||||
void at91_irq_suspend(void)
|
||||
{
|
||||
int i = 0, bit;
|
||||
int bit = -1;
|
||||
|
||||
if (has_aic5()) {
|
||||
/* disable enabled irqs */
|
||||
while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
|
||||
while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
|
||||
at91_aic_write(AT91_AIC5_SSR,
|
||||
bit & AT91_AIC5_INTSEL_MSK);
|
||||
at91_aic_write(AT91_AIC5_IDCR, 1);
|
||||
i = bit;
|
||||
}
|
||||
/* enable wakeup irqs */
|
||||
i = 0;
|
||||
while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
|
||||
bit = -1;
|
||||
while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
|
||||
at91_aic_write(AT91_AIC5_SSR,
|
||||
bit & AT91_AIC5_INTSEL_MSK);
|
||||
at91_aic_write(AT91_AIC5_IECR, 1);
|
||||
i = bit;
|
||||
}
|
||||
} else {
|
||||
at91_aic_write(AT91_AIC_IDCR, *backups);
|
||||
|
|
@ -118,23 +116,21 @@ void at91_irq_suspend(void)
|
|||
|
||||
void at91_irq_resume(void)
|
||||
{
|
||||
int i = 0, bit;
|
||||
int bit = -1;
|
||||
|
||||
if (has_aic5()) {
|
||||
/* disable wakeup irqs */
|
||||
while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
|
||||
while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
|
||||
at91_aic_write(AT91_AIC5_SSR,
|
||||
bit & AT91_AIC5_INTSEL_MSK);
|
||||
at91_aic_write(AT91_AIC5_IDCR, 1);
|
||||
i = bit;
|
||||
}
|
||||
/* enable irqs disabled for suspend */
|
||||
i = 0;
|
||||
while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
|
||||
bit = -1;
|
||||
while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
|
||||
at91_aic_write(AT91_AIC5_SSR,
|
||||
bit & AT91_AIC5_INTSEL_MSK);
|
||||
at91_aic_write(AT91_AIC5_IECR, 1);
|
||||
i = bit;
|
||||
}
|
||||
} else {
|
||||
at91_aic_write(AT91_AIC_IDCR, *wakeups);
|
||||
|
|
|
|||
|
|
@ -201,7 +201,10 @@ extern u32 at91_slow_clock_sz;
|
|||
|
||||
static int at91_pm_enter(suspend_state_t state)
|
||||
{
|
||||
at91_gpio_suspend();
|
||||
if (of_have_populated_dt())
|
||||
at91_pinctrl_gpio_suspend();
|
||||
else
|
||||
at91_gpio_suspend();
|
||||
at91_irq_suspend();
|
||||
|
||||
pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
|
||||
|
|
@ -286,7 +289,10 @@ static int at91_pm_enter(suspend_state_t state)
|
|||
error:
|
||||
target_state = PM_SUSPEND_ON;
|
||||
at91_irq_resume();
|
||||
at91_gpio_resume();
|
||||
if (of_have_populated_dt())
|
||||
at91_pinctrl_gpio_resume();
|
||||
else
|
||||
at91_gpio_resume();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -743,6 +743,9 @@ EXPORT_SYMBOL(edma_free_channel);
|
|||
*/
|
||||
int edma_alloc_slot(unsigned ctlr, int slot)
|
||||
{
|
||||
if (!edma_cc[ctlr])
|
||||
return -EINVAL;
|
||||
|
||||
if (slot >= 0)
|
||||
slot = EDMA_CHAN_SLOT(slot);
|
||||
|
||||
|
|
|
|||
|
|
@ -67,6 +67,7 @@ config ARCH_NETWINDER
|
|||
select ISA
|
||||
select ISA_DMA
|
||||
select PCI
|
||||
select VIRT_TO_BUS
|
||||
help
|
||||
Say Y here if you intend to run this kernel on the Rebel.COM
|
||||
NetWinder. Information about this machine can be found at:
|
||||
|
|
|
|||
|
|
@ -83,24 +83,12 @@ config ARCH_MXC_IOMUX_V3
|
|||
config ARCH_MX1
|
||||
bool
|
||||
|
||||
config MACH_MX21
|
||||
bool
|
||||
|
||||
config ARCH_MX25
|
||||
bool
|
||||
|
||||
config MACH_MX27
|
||||
bool
|
||||
|
||||
config ARCH_MX5
|
||||
bool
|
||||
|
||||
config ARCH_MX51
|
||||
bool
|
||||
|
||||
config ARCH_MX53
|
||||
bool
|
||||
|
||||
config SOC_IMX1
|
||||
bool
|
||||
select ARCH_MX1
|
||||
|
|
@ -114,7 +102,6 @@ config SOC_IMX21
|
|||
select COMMON_CLK
|
||||
select CPU_ARM926T
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MACH_MX21
|
||||
select MXC_AVIC
|
||||
|
||||
config SOC_IMX25
|
||||
|
|
@ -155,7 +142,6 @@ config SOC_IMX35
|
|||
config SOC_IMX5
|
||||
bool
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select ARCH_MX5
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
|
|
@ -163,8 +149,7 @@ config SOC_IMX5
|
|||
|
||||
config SOC_IMX51
|
||||
bool
|
||||
select ARCH_MX5
|
||||
select ARCH_MX51
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX51
|
||||
select SOC_IMX5
|
||||
|
|
@ -789,9 +774,8 @@ comment "Device tree only"
|
|||
|
||||
config SOC_IMX53
|
||||
bool "i.MX53 support"
|
||||
select ARCH_MX5
|
||||
select ARCH_MX53
|
||||
select HAVE_CAN_FLEXCAN if CAN
|
||||
select HAVE_IMX_SRC
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX53
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
|
|||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
|
||||
|
||||
imx5-pm-$(CONFIG_PM) += pm-imx5.o
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
|
||||
clk-pfd.o clk-busy.o clk.o
|
||||
|
|
@ -27,7 +27,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
|
|||
obj-$(CONFIG_MXC_ULPI) += ulpi.o
|
||||
obj-$(CONFIG_MXC_USE_EPIT) += epit.o
|
||||
obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
|
||||
obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
|
||||
|
||||
ifeq ($(CONFIG_CPU_IDLE),y)
|
||||
obj-y += cpuidle.o
|
||||
|
|
|
|||
|
|
@ -1,35 +0,0 @@
|
|||
zreladdr-$(CONFIG_SOC_IMX1) += 0x08008000
|
||||
params_phys-$(CONFIG_SOC_IMX1) := 0x08000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX1) := 0x08800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX21) += 0xC0008000
|
||||
params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX25) += 0x80008000
|
||||
params_phys-$(CONFIG_SOC_IMX25) := 0x80000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX27) += 0xA0008000
|
||||
params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX31) += 0x80008000
|
||||
params_phys-$(CONFIG_SOC_IMX31) := 0x80000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
|
||||
params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
|
||||
params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000
|
||||
params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
|
||||
params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
|
||||
|
|
@ -54,8 +54,6 @@
|
|||
void __iomem *avic_base;
|
||||
static struct irq_domain *domain;
|
||||
|
||||
static u32 avic_saved_mask_reg[2];
|
||||
|
||||
#ifdef CONFIG_MXC_IRQ_PRIOR
|
||||
static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
|
||||
{
|
||||
|
|
@ -113,6 +111,8 @@ static struct mxc_extra_irq avic_extra_irq = {
|
|||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static u32 avic_saved_mask_reg[2];
|
||||
|
||||
static void avic_irq_suspend(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
|
|
|
|||
|
|
@ -86,10 +86,12 @@ enum mx27_clks {
|
|||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
int __init mx27_clocks_init(unsigned long fref)
|
||||
{
|
||||
int i;
|
||||
struct device_node *np;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[ckih] = imx_clk_fixed("ckih", fref);
|
||||
|
|
@ -198,6 +200,13 @@ int __init mx27_clocks_init(unsigned long fref)
|
|||
pr_err("i.MX27 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
|
||||
if (np) {
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
|
||||
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
|
||||
|
|
@ -276,10 +285,8 @@ int __init mx27_clocks_init(unsigned long fref)
|
|||
clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
|
||||
clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
|
||||
clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
|
||||
clk_register_clkdev(clk[cpu_div], "cpu", NULL);
|
||||
clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0");
|
||||
clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
|
||||
clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
|
||||
|
||||
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
|
||||
|
||||
|
|
|
|||
|
|
@ -264,6 +264,7 @@ int __init mx35_clocks_init(void)
|
|||
clk_prepare_enable(clk[gpio3_gate]);
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
clk_prepare_enable(clk[emi_gate]);
|
||||
clk_prepare_enable(clk[max_gate]);
|
||||
|
||||
/*
|
||||
* SCC is needed to boot via mmc after a watchdog reset. The clock code
|
||||
|
|
|
|||
|
|
@ -281,7 +281,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
|||
clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
|
||||
clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
|
||||
clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
|
||||
clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
|
||||
clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
|
||||
clk_register_clkdev(clk[iim_gate], "iim", NULL);
|
||||
clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
|
||||
|
|
@ -362,9 +362,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
|
||||
clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
|
||||
clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
|
||||
clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
|
||||
clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
|
||||
clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
|
||||
clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
|
||||
|
|
@ -471,10 +468,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
|
||||
clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
|
||||
clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
|
||||
clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
|
||||
clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
|
||||
clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
|
||||
clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
|
||||
|
|
|
|||
|
|
@ -111,7 +111,6 @@ void tzic_handle_irq(struct pt_regs *);
|
|||
extern void imx_enable_cpu(int cpu, bool enable);
|
||||
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
|
||||
extern void v7_cpu_resume(void);
|
||||
extern u32 *pl310_get_save_ptr(void);
|
||||
#ifdef CONFIG_SMP
|
||||
extern void v7_secondary_startup(void);
|
||||
extern void imx_scu_map_io(void);
|
||||
|
|
@ -122,8 +121,6 @@ static inline void imx_scu_map_io(void) {}
|
|||
static inline void imx_smp_prepare(void) {}
|
||||
static inline void imx_scu_standby_enable(void) {}
|
||||
#endif
|
||||
extern void imx_enable_cpu(int cpu, bool enable);
|
||||
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
|
||||
extern void imx_src_init(void);
|
||||
extern void imx_src_prepare_restart(void);
|
||||
extern void imx_gpc_init(void);
|
||||
|
|
|
|||
|
|
@ -1,31 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "hardware.h"
|
||||
|
||||
static struct cpu_op mx51_cpu_op[] = {
|
||||
{
|
||||
.cpu_rate = 160000000,},
|
||||
{
|
||||
.cpu_rate = 800000000,},
|
||||
};
|
||||
|
||||
struct cpu_op *mx51_get_cpu_op(int *op)
|
||||
{
|
||||
*op = ARRAY_SIZE(mx51_cpu_op);
|
||||
return mx51_cpu_op;
|
||||
}
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
extern struct cpu_op *mx51_get_cpu_op(int *op);
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/*
|
||||
* A driver for the Freescale Semiconductor i.MXC CPUfreq module.
|
||||
* The CPUFREQ driver is for controlling CPU frequency. It allows you to change
|
||||
* the CPU clock speed on the fly.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "hardware.h"
|
||||
|
||||
#define CLK32_FREQ 32768
|
||||
#define NANOSECOND (1000 * 1000 * 1000)
|
||||
|
||||
struct cpu_op *(*get_cpu_op)(int *op);
|
||||
|
||||
static int cpu_freq_khz_min;
|
||||
static int cpu_freq_khz_max;
|
||||
|
||||
static struct clk *cpu_clk;
|
||||
static struct cpufreq_frequency_table *imx_freq_table;
|
||||
|
||||
static int cpu_op_nr;
|
||||
static struct cpu_op *cpu_op_tbl;
|
||||
|
||||
static int set_cpu_freq(int freq)
|
||||
{
|
||||
int ret = 0;
|
||||
int org_cpu_rate;
|
||||
|
||||
org_cpu_rate = clk_get_rate(cpu_clk);
|
||||
if (org_cpu_rate == freq)
|
||||
return ret;
|
||||
|
||||
ret = clk_set_rate(cpu_clk, freq);
|
||||
if (ret != 0) {
|
||||
printk(KERN_DEBUG "cannot set CPU clock rate\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxc_verify_speed(struct cpufreq_policy *policy)
|
||||
{
|
||||
if (policy->cpu != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return cpufreq_frequency_table_verify(policy, imx_freq_table);
|
||||
}
|
||||
|
||||
static unsigned int mxc_get_speed(unsigned int cpu)
|
||||
{
|
||||
if (cpu)
|
||||
return 0;
|
||||
|
||||
return clk_get_rate(cpu_clk) / 1000;
|
||||
}
|
||||
|
||||
static int mxc_set_target(struct cpufreq_policy *policy,
|
||||
unsigned int target_freq, unsigned int relation)
|
||||
{
|
||||
struct cpufreq_freqs freqs;
|
||||
int freq_Hz;
|
||||
int ret = 0;
|
||||
unsigned int index;
|
||||
|
||||
cpufreq_frequency_table_target(policy, imx_freq_table,
|
||||
target_freq, relation, &index);
|
||||
freq_Hz = imx_freq_table[index].frequency * 1000;
|
||||
|
||||
freqs.old = clk_get_rate(cpu_clk) / 1000;
|
||||
freqs.new = freq_Hz / 1000;
|
||||
freqs.cpu = 0;
|
||||
freqs.flags = 0;
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
|
||||
ret = set_cpu_freq(freq_Hz);
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxc_cpufreq_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
printk(KERN_INFO "i.MXC CPU frequency driver\n");
|
||||
|
||||
if (policy->cpu != 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (!get_cpu_op)
|
||||
return -EINVAL;
|
||||
|
||||
cpu_clk = clk_get(NULL, "cpu_clk");
|
||||
if (IS_ERR(cpu_clk)) {
|
||||
printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
|
||||
return PTR_ERR(cpu_clk);
|
||||
}
|
||||
|
||||
cpu_op_tbl = get_cpu_op(&cpu_op_nr);
|
||||
|
||||
cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
|
||||
cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
|
||||
|
||||
imx_freq_table = kmalloc(
|
||||
sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
|
||||
GFP_KERNEL);
|
||||
if (!imx_freq_table) {
|
||||
ret = -ENOMEM;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
for (i = 0; i < cpu_op_nr; i++) {
|
||||
imx_freq_table[i].index = i;
|
||||
imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
|
||||
if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
|
||||
cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
|
||||
if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
|
||||
cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
}
|
||||
|
||||
imx_freq_table[i].index = i;
|
||||
imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
policy->cur = clk_get_rate(cpu_clk) / 1000;
|
||||
policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
|
||||
policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
|
||||
|
||||
/* Manual states, that PLL stabilizes in two CLK32 periods */
|
||||
policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
|
||||
|
||||
ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
|
||||
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n",
|
||||
__func__, ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
|
||||
return 0;
|
||||
err:
|
||||
kfree(imx_freq_table);
|
||||
err1:
|
||||
clk_put(cpu_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
|
||||
{
|
||||
cpufreq_frequency_table_put_attr(policy->cpu);
|
||||
|
||||
set_cpu_freq(cpu_freq_khz_max * 1000);
|
||||
clk_put(cpu_clk);
|
||||
kfree(imx_freq_table);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct cpufreq_driver mxc_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = mxc_verify_speed,
|
||||
.target = mxc_set_target,
|
||||
.get = mxc_get_speed,
|
||||
.init = mxc_cpufreq_init,
|
||||
.exit = mxc_cpufreq_exit,
|
||||
.name = "imx",
|
||||
};
|
||||
|
||||
static int mxc_cpufreq_driver_init(void)
|
||||
{
|
||||
return cpufreq_register_driver(&mxc_driver);
|
||||
}
|
||||
|
||||
static void mxc_cpufreq_driver_exit(void)
|
||||
{
|
||||
cpufreq_unregister_driver(&mxc_driver);
|
||||
}
|
||||
|
||||
module_init(mxc_cpufreq_driver_init);
|
||||
module_exit(mxc_cpufreq_driver_exit);
|
||||
|
||||
MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
|
||||
MODULE_DESCRIPTION("CPUfreq driver for i.MX");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -86,7 +86,3 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
|
|||
|
||||
config IMX_HAVE_PLATFORM_SPI_IMX
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_AHCI
|
||||
bool
|
||||
default y if ARCH_MX53
|
||||
|
|
|
|||
|
|
@ -29,5 +29,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
|
|||
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
|
||||
|
|
|
|||
|
|
@ -344,13 +344,3 @@ struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
|
|||
int irq, int irq_err);
|
||||
struct platform_device *imx_add_imx_sdma(char *name,
|
||||
resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
|
||||
|
||||
#include <linux/ahci_platform.h>
|
||||
struct imx_ahci_imx_data {
|
||||
const char *devid;
|
||||
resource_size_t iobase;
|
||||
resource_size_t irq;
|
||||
};
|
||||
struct platform_device *__init imx_add_ahci_imx(
|
||||
const struct imx_ahci_imx_data *data,
|
||||
const struct ahci_platform_data *pdata);
|
||||
|
|
|
|||
|
|
@ -1,157 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include "../hardware.h"
|
||||
#include "devices-common.h"
|
||||
|
||||
#define imx_ahci_imx_data_entry_single(soc, _devid) \
|
||||
{ \
|
||||
.devid = _devid, \
|
||||
.iobase = soc ## _SATA_BASE_ADDR, \
|
||||
.irq = soc ## _INT_SATA, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
|
||||
imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
|
||||
#endif
|
||||
|
||||
enum {
|
||||
HOST_CAP = 0x00,
|
||||
HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
|
||||
HOST_PORTS_IMPL = 0x0c,
|
||||
HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
|
||||
};
|
||||
|
||||
static struct clk *sata_clk, *sata_ref_clk;
|
||||
|
||||
/* AHCI module Initialization, if return 0, initialization is successful. */
|
||||
static int imx_sata_init(struct device *dev, void __iomem *addr)
|
||||
{
|
||||
u32 tmpdata;
|
||||
int ret = 0;
|
||||
struct clk *clk;
|
||||
|
||||
sata_clk = clk_get(dev, "ahci");
|
||||
if (IS_ERR(sata_clk)) {
|
||||
dev_err(dev, "no sata clock.\n");
|
||||
return PTR_ERR(sata_clk);
|
||||
}
|
||||
ret = clk_prepare_enable(sata_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't prepare/enable sata clock.\n");
|
||||
goto put_sata_clk;
|
||||
}
|
||||
|
||||
/* Get the AHCI SATA PHY CLK */
|
||||
sata_ref_clk = clk_get(dev, "ahci_phy");
|
||||
if (IS_ERR(sata_ref_clk)) {
|
||||
dev_err(dev, "no sata ref clock.\n");
|
||||
ret = PTR_ERR(sata_ref_clk);
|
||||
goto release_sata_clk;
|
||||
}
|
||||
ret = clk_prepare_enable(sata_ref_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't prepare/enable sata ref clock.\n");
|
||||
goto put_sata_ref_clk;
|
||||
}
|
||||
|
||||
/* Get the AHB clock rate, and configure the TIMER1MS reg later */
|
||||
clk = clk_get(dev, "ahci_dma");
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(dev, "no dma clock.\n");
|
||||
ret = PTR_ERR(clk);
|
||||
goto release_sata_ref_clk;
|
||||
}
|
||||
tmpdata = clk_get_rate(clk) / 1000;
|
||||
clk_put(clk);
|
||||
|
||||
writel(tmpdata, addr + HOST_TIMER1MS);
|
||||
|
||||
tmpdata = readl(addr + HOST_CAP);
|
||||
if (!(tmpdata & HOST_CAP_SSS)) {
|
||||
tmpdata |= HOST_CAP_SSS;
|
||||
writel(tmpdata, addr + HOST_CAP);
|
||||
}
|
||||
|
||||
if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
|
||||
writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
|
||||
addr + HOST_PORTS_IMPL);
|
||||
|
||||
return 0;
|
||||
|
||||
release_sata_ref_clk:
|
||||
clk_disable_unprepare(sata_ref_clk);
|
||||
put_sata_ref_clk:
|
||||
clk_put(sata_ref_clk);
|
||||
release_sata_clk:
|
||||
clk_disable_unprepare(sata_clk);
|
||||
put_sata_clk:
|
||||
clk_put(sata_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void imx_sata_exit(struct device *dev)
|
||||
{
|
||||
clk_disable_unprepare(sata_ref_clk);
|
||||
clk_put(sata_ref_clk);
|
||||
|
||||
clk_disable_unprepare(sata_clk);
|
||||
clk_put(sata_clk);
|
||||
|
||||
}
|
||||
struct platform_device *__init imx_add_ahci_imx(
|
||||
const struct imx_ahci_imx_data *data,
|
||||
const struct ahci_platform_data *pdata)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = data->iobase,
|
||||
.end = data->iobase + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = data->irq,
|
||||
.end = data->irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
return imx_add_platform_device_dmamask(data->devid, 0,
|
||||
res, ARRAY_SIZE(res),
|
||||
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
|
||||
}
|
||||
|
||||
struct platform_device *__init imx53_add_ahci_imx(void)
|
||||
{
|
||||
struct ahci_platform_data pdata = {
|
||||
.init = imx_sata_init,
|
||||
.exit = imx_sata_exit,
|
||||
};
|
||||
|
||||
return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
|
||||
}
|
||||
|
|
@ -102,7 +102,6 @@
|
|||
|
||||
#include "mxc.h"
|
||||
|
||||
#include "mx6q.h"
|
||||
#include "mx51.h"
|
||||
#include "mx53.h"
|
||||
#include "mx3x.h"
|
||||
|
|
|
|||
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Reference in New Issue