ARM: shmobile: r8a7790: Add JPU clock dt and CPG define.
Signed-off-by: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -836,17 +836,17 @@
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
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clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
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clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
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<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
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<&zs_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
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R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
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R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
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R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
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>;
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clock-output-names =
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"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
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"jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
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"vsp1-du0", "vsp1-rt", "vsp1-sy";
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};
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mstp2_clks: mstp2_clks@e6150138 {
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@ -26,6 +26,7 @@
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#define R8A7790_CLK_MSIOF0 0
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/* MSTP1 */
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#define R8A7790_CLK_JPU 6
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#define R8A7790_CLK_TMU1 11
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#define R8A7790_CLK_TMU3 21
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#define R8A7790_CLK_TMU2 22
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