[ARM] pxa: move GPIO register definitions into <mach/gpio.h>
This makes gpio.c fully independent of pxa-regs.h (except for the virtual address of the registers). Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.miao@marvell.com>
This commit is contained in:
Eric Miao
parent
0d9f768fce
commit
da065a0b36
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@ -26,8 +26,8 @@
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#include <asm/mach/map.h>
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#include <asm/mach-types.h>
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#include <mach/pxa-regs.h>
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#include <mach/reset.h>
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#include <mach/gpio.h>
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#include <mach/pxa2xx-gpio.h>
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#include "generic.h"
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@ -18,16 +18,12 @@
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#include <linux/sysdev.h>
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#include <linux/io.h>
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#include <asm/gpio.h>
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#include <mach/hardware.h>
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#include <mach/pxa-regs.h>
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#include <mach/gpio.h>
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#include "generic.h"
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#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
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#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
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#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
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#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
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#define GPIO0_BASE (GPIO_REGS_VIRT + 0x0000)
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#define GPIO1_BASE (GPIO_REGS_VIRT + 0x0004)
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#define GPIO2_BASE (GPIO_REGS_VIRT + 0x0008)
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#define GPIO3_BASE (GPIO_REGS_VIRT + 0x0100)
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#define GPLR_OFFSET 0x00
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#define GPDR_OFFSET 0x0C
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@ -24,12 +24,80 @@
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#ifndef __ASM_ARCH_PXA_GPIO_H
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#define __ASM_ARCH_PXA_GPIO_H
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#include <mach/pxa-regs.h>
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#include <asm/irq.h>
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <asm-generic/gpio.h>
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#define GPIO_REGS_VIRT io_p2v(0x40E00000)
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#define BANK_OFF(n) (((n) > 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
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#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
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/* GPIO Pin Level Registers */
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#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00)
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#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00)
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#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00)
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#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00)
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/* GPIO Pin Direction Registers */
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#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c)
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#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c)
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#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c)
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#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c)
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/* GPIO Pin Output Set Registers */
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#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18)
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#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18)
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#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18)
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#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18)
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/* GPIO Pin Output Clear Registers */
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#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24)
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#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24)
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#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24)
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#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24)
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/* GPIO Rising Edge Detect Registers */
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#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30)
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#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30)
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#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30)
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#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30)
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/* GPIO Falling Edge Detect Registers */
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#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c)
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#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c)
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#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c)
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#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c)
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/* GPIO Edge Detect Status Registers */
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#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48)
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#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48)
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#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48)
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#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48)
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/* GPIO Alternate Function Select Registers */
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#define GAFR0_L GPIO_REG(0x0054)
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#define GAFR0_U GPIO_REG(0x0058)
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#define GAFR1_L GPIO_REG(0x005C)
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#define GAFR1_U GPIO_REG(0x0060)
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#define GAFR2_L GPIO_REG(0x0064)
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#define GAFR2_U GPIO_REG(0x0068)
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#define GAFR3_L GPIO_REG(0x006C)
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#define GAFR3_U GPIO_REG(0x0070)
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/* More handy macros. The argument is a literal GPIO number. */
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#define GPIO_bit(x) (1 << ((x) & 0x1f))
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#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
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#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
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#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
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#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
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#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
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#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
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#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
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#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
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/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
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* Those cases currently cause holes in the GPIO number space.
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@ -129,76 +129,4 @@
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#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
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#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
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/*
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* General Purpose I/O
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*/
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#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
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#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
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#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
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#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
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#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
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#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
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#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
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#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
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#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
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#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
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#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
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#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
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#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
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#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
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#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
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#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
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#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
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#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
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#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
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#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
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#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
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#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
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#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
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#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
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#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
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#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
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#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
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#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
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#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
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#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
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#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
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#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
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#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
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#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
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#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
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#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
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/* More handy macros. The argument is a literal GPIO number. */
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#define GPIO_bit(x) (1 << ((x) & 0x1f))
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#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
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#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
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#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
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#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
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#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
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#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
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#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
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#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
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#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
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#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
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#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
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#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
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#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
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#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
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#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
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#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
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((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
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#endif
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@ -3,6 +3,8 @@
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#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
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#include <mach/gpio.h>
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/* GPIO alternate function assignments */
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#define GPIO1_RST 1 /* reset */
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@ -39,6 +39,7 @@
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#include <asm/mach/flash.h>
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#include <mach/pxa27x.h>
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#include <mach/gpio.h>
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#include <mach/lpd270.h>
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#include <mach/audio.h>
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#include <mach/pxafb.h>
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@ -42,6 +42,7 @@
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#include <asm/hardware/sa1111.h>
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#include <mach/pxa25x.h>
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#include <mach/gpio.h>
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#include <mach/audio.h>
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#include <mach/lubbock.h>
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#include <mach/udc.h>
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@ -42,6 +42,7 @@
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#include <asm/mach/flash.h>
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#include <mach/pxa27x.h>
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#include <mach/gpio.h>
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#include <mach/mainstone.h>
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#include <mach/audio.h>
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#include <mach/pxafb.h>
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@ -18,8 +18,7 @@
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#include <linux/init.h>
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#include <linux/sysdev.h>
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#include <mach/hardware.h>
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#include <mach/pxa-regs.h>
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#include <mach/gpio.h>
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#include <mach/pxa2xx-regs.h>
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#include <mach/mfp-pxa2xx.h>
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