[S390] __div64_32 for 31 bit.
The clocksource infrastructure introduced with commit
ad596171ed broke 31 bit s390.
The reason is that the do_div() primitive for 31 bit always
had a restriction: it could only divide an unsigned 64 bit
integer by an unsigned 31 bit integer. The clocksource code
now uses do_div() with a base value that has the most
significant bit set. The result is that clock->cycle_interval
has a funny value which causes the linux time to jump around
like mad.
The solution is "obvious": implement a proper __div64_32
function for 31 bit s390.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Martin Schwidefsky
parent
1fce518e8e
commit
d9f7a745d5
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@ -51,6 +51,10 @@ config 64BIT
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Select this option if you have a 64 bit IBM zSeries machine
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and want to use the 64 bit addressing mode.
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config 32BIT
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bool
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default y if !64BIT
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config SMP
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bool "Symmetric multi-processing support"
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---help---
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@ -5,5 +5,6 @@
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EXTRA_AFLAGS := -traditional
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lib-y += delay.o string.o uaccess_std.o
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lib-$(CONFIG_32BIT) += div64.o
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lib-$(CONFIG_64BIT) += uaccess_mvcos.o
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lib-$(CONFIG_SMP) += spinlock.o
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@ -0,0 +1,151 @@
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/*
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* arch/s390/lib/div64.c
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*
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* __div64_32 implementation for 31 bit.
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*
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* Copyright (C) IBM Corp. 2006
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#ifdef CONFIG_MARCH_G5
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/*
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* Function to divide an unsigned 64 bit integer by an unsigned
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* 31 bit integer using signed 64/32 bit division.
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*/
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static uint32_t __div64_31(uint64_t *n, uint32_t base)
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{
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register uint32_t reg2 asm("2");
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register uint32_t reg3 asm("3");
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uint32_t *words = (uint32_t *) n;
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uint32_t tmp;
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/* Special case base==1, remainder = 0, quotient = n */
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if (base == 1)
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return 0;
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/*
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* Special case base==0 will cause a fixed point divide exception
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* on the dr instruction and may not happen anyway. For the
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* following calculation we can assume base > 1. The first
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* signed 64 / 32 bit division with an upper half of 0 will
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* give the correct upper half of the 64 bit quotient.
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*/
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reg2 = 0UL;
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reg3 = words[0];
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asm volatile(
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" dr %0,%2\n"
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: "+d" (reg2), "+d" (reg3) : "d" (base) : "cc" );
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words[0] = reg3;
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reg3 = words[1];
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/*
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* To get the lower half of the 64 bit quotient and the 32 bit
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* remainder we have to use a little trick. Since we only have
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* a signed division the quotient can get too big. To avoid this
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* the 64 bit dividend is halved, then the signed division will
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* work. Afterwards the quotient and the remainder are doubled.
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* If the last bit of the dividend has been one the remainder
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* is increased by one then checked against the base. If the
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* remainder has overflown subtract base and increase the
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* quotient. Simple, no ?
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*/
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asm volatile(
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" nr %2,%1\n"
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" srdl %0,1\n"
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" dr %0,%3\n"
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" alr %0,%0\n"
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" alr %1,%1\n"
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" alr %0,%2\n"
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" clr %0,%3\n"
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" jl 0f\n"
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" slr %0,%3\n"
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" alr %1,%2\n"
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"0:\n"
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: "+d" (reg2), "+d" (reg3), "=d" (tmp)
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: "d" (base), "2" (1UL) : "cc" );
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words[1] = reg3;
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return reg2;
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}
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/*
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* Function to divide an unsigned 64 bit integer by an unsigned
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* 32 bit integer using the unsigned 64/31 bit division.
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*/
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uint32_t __div64_32(uint64_t *n, uint32_t base)
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{
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uint32_t r;
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/*
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* If the most significant bit of base is set, divide n by
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* (base/2). That allows to use 64/31 bit division and gives a
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* good approximation of the result: n = (base/2)*q + r. The
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* result needs to be corrected with two simple transformations.
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* If base is already < 2^31-1 __div64_31 can be used directly.
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*/
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r = __div64_31(n, ((signed) base < 0) ? (base/2) : base);
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if ((signed) base < 0) {
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uint64_t q = *n;
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/*
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* First transformation:
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* n = (base/2)*q + r
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* = ((base/2)*2)*(q/2) + ((q&1) ? (base/2) : 0) + r
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* Since r < (base/2), r + (base/2) < base.
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* With q1 = (q/2) and r1 = r + ((q&1) ? (base/2) : 0)
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* n = ((base/2)*2)*q1 + r1 with r1 < base.
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*/
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if (q & 1)
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r += base/2;
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q >>= 1;
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/*
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* Second transformation. ((base/2)*2) could have lost the
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* last bit.
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* n = ((base/2)*2)*q1 + r1
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* = base*q1 - ((base&1) ? q1 : 0) + r1
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*/
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if (base & 1) {
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int64_t rx = r - q;
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/*
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* base is >= 2^31. The worst case for the while
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* loop is n=2^64-1 base=2^31+1. That gives a
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* maximum for q=(2^64-1)/2^31 = 0x1ffffffff. Since
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* base >= 2^31 the loop is finished after a maximum
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* of three iterations.
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*/
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while (rx < 0) {
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rx += base;
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q--;
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}
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r = rx;
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}
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*n = q;
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}
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return r;
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}
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#else /* MARCH_G5 */
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uint32_t __div64_32(uint64_t *n, uint32_t base)
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{
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register uint32_t reg2 asm("2");
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register uint32_t reg3 asm("3");
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uint32_t *words = (uint32_t *) n;
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reg2 = 0UL;
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reg3 = words[0];
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asm volatile(
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" dlr %0,%2\n"
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: "+d" (reg2), "+d" (reg3) : "d" (base) : "cc" );
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words[0] = reg3;
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reg3 = words[1];
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asm volatile(
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" dlr %0,%2\n"
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: "+d" (reg2), "+d" (reg3) : "d" (base) : "cc" );
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words[1] = reg3;
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return reg2;
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}
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#endif /* MARCH_G5 */
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EXPORT_SYMBOL(__div64_32);
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@ -1,49 +1 @@
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#ifndef __S390_DIV64
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#define __S390_DIV64
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#ifndef __s390x__
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/* for do_div "base" needs to be smaller than 2^31-1 */
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#define do_div(n, base) ({ \
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unsigned long long __n = (n); \
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unsigned long __r; \
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\
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asm (" slr 0,0\n" \
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" l 1,%1\n" \
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" srdl 0,1\n" \
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" dr 0,%2\n" \
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" alr 1,1\n" \
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" alr 0,0\n" \
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" lhi 2,1\n" \
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" n 2,%1\n" \
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" alr 0,2\n" \
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" clr 0,%2\n" \
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" jl 0f\n" \
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" slr 0,%2\n" \
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" ahi 1,1\n" \
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"0: st 1,%1\n" \
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" l 1,4+%1\n" \
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" srdl 0,1\n" \
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" dr 0,%2\n" \
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" alr 1,1\n" \
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" alr 0,0\n" \
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" lhi 2,1\n" \
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" n 2,4+%1\n" \
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" alr 0,2\n" \
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" clr 0,%2\n" \
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" jl 1f\n" \
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" slr 0,%2\n" \
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" ahi 1,1\n" \
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"1: st 1,4+%1\n" \
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" lr %0,0" \
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: "=d" (__r), "=m" (__n) \
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: "d" (base), "m" (__n) : "0", "1", "2", "cc" ); \
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(n) = (__n); \
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__r; \
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})
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#else /* __s390x__ */
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#include <asm-generic/div64.h>
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#endif /* __s390x__ */
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#endif
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