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Merge branch 'net-phy-add-and-use-further-MMD-accessors' 

Heiner Kallweit says:

====================
net: phy: add and use further MMD accessors

Add MMD accessors for modifying MMD registers and clearing / setting
bits in MMD registers. Use these accessors in PHY drivers and phylib.

v2:
- fix SoB in patch 2
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-02-06 09:52:43 -08:00
parent 5661f29ade b52c018ddc
commit d9b5a67522
7 changed files with 267 additions and 145 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
drivers/net/phy/dp83867.c
View File

@ -127,17 +127,13 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
struct dp83867_private *dp83867 =
(struct dp83867_private *)phydev->priv;
u16 val;
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
val |= DP83867_CFG4_PORT_MIRROR_EN;
phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
DP83867_CFG4_PORT_MIRROR_EN);
else
val &= ~DP83867_CFG4_PORT_MIRROR_EN;
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
DP83867_CFG4_PORT_MIRROR_EN);
return 0;
}
@ -222,11 +218,9 @@ static int dp83867_config_init(struct phy_device *phydev)
}
/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
if (dp83867->rxctrl_strap_quirk) {
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
val &= ~BIT(7);
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
}
if (dp83867->rxctrl_strap_quirk)
phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
BIT(7));
if (phy_interface_is_rgmii(phydev)) {
val = phy_read(phydev, MII_DP83867_PHYCTRL);
@ -275,17 +269,11 @@ static int dp83867_config_init(struct phy_device *phydev)
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
delay);
if (dp83867->io_impedance >= 0) {
val = phy_read_mmd(phydev, DP83867_DEVADDR,
DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
val |= dp83867->io_impedance &
DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
phy_write_mmd(phydev, DP83867_DEVADDR,
DP83867_IO_MUX_CFG, val);
}
if (dp83867->io_impedance >= 0)
phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
dp83867->io_impedance &
DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
}
/* Enable Interrupt output INT_OE in CFG3 register */
@ -299,12 +287,11 @@ static int dp83867_config_init(struct phy_device *phydev)
dp83867_config_port_mirroring(phydev);
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
}
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)
phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,
dp83867->clk_output_sel <<
DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
return 0;
}

15
drivers/net/phy/dp83tc811.c
View File

@ -144,11 +144,8 @@ static int dp83811_set_wol(struct phy_device *phydev,
phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
value);
} else {
value = phy_read_mmd(phydev, DP83811_DEVADDR,
MII_DP83811_WOL_CFG);
value &= ~DP83811_WOL_EN;
phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
value);
phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
DP83811_WOL_EN);
}
return 0;
@ -328,14 +325,10 @@ static int dp83811_suspend(struct phy_device *phydev)
static int dp83811_resume(struct phy_device *phydev)
{
int value;
genphy_resume(phydev);
value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, value |
DP83811_WOL_CLR_INDICATION);
phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
DP83811_WOL_CLR_INDICATION);
return 0;
}

38
drivers/net/phy/marvell10g.c
View File

@ -58,24 +58,6 @@ struct mv3310_priv {
char *hwmon_name;
};
static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
u16 mask, u16 bits)
{
int old, val, ret;
old = phy_read_mmd(phydev, devad, reg);
if (old < 0)
return old;
val = (old & ~mask) | (bits & mask);
if (val == old)
return 0;
ret = phy_write_mmd(phydev, devad, reg, val);
return ret < 0 ? ret : 1;
}
#ifdef CONFIG_HWMON
static umode_t mv3310_hwmon_is_visible(const void *data,
enum hwmon_sensor_types type,
@ -159,8 +141,8 @@ static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
return ret;
val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
MV_V2_TEMP_CTRL_MASK, val);
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
MV_V2_TEMP_CTRL_MASK, val);
return ret < 0 ? ret : 0;
}
@ -363,18 +345,18 @@ static int mv3310_config_aneg(struct phy_device *phydev)
linkmode_and(phydev->advertising, phydev->advertising,
phydev->supported);
ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
ADVERTISE_ALL | ADVERTISE_100BASE4 |
ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
linkmode_adv_to_mii_adv_t(phydev->advertising));
ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
ADVERTISE_ALL | ADVERTISE_100BASE4 |
ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
linkmode_adv_to_mii_adv_t(phydev->advertising));
if (ret < 0)
return ret;
if (ret > 0)
changed = true;
reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
if (ret < 0)
return ret;
if (ret > 0)
@ -387,8 +369,8 @@ static int mv3310_config_aneg(struct phy_device *phydev)
else
reg = 0;
ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
MDIO_AN_10GBT_CTRL_ADV10G, reg);
ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
MDIO_AN_10GBT_CTRL_ADV10G, reg);
if (ret < 0)
return ret;
if (ret > 0)

21
drivers/net/phy/phy-c45.c
View File

@ -75,15 +75,9 @@ EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
*/
int genphy_c45_an_disable_aneg(struct phy_device *phydev)
{
int val;
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
if (val < 0)
return val;
val &= ~(MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);
return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
}
EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
@ -97,15 +91,8 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
*/
int genphy_c45_restart_aneg(struct phy_device *phydev)
{
int val;
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
if (val < 0)
return val;
val |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);
return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
}
EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);

146
drivers/net/phy/phy-core.c
View File

@ -414,15 +414,15 @@ static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
}
/**
* phy_read_mmd - Convenience function for reading a register
* __phy_read_mmd - Convenience function for reading a register
* from an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to read from (0..31)
* @regnum: The register on the MMD to read (0..65535)
*
* Same rules as for phy_read();
* Same rules as for __phy_read();
*/
int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
{
int val;
@ -434,22 +434,80 @@ int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
} else if (phydev->is_c45) {
u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff);
val = mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, addr);
val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, addr);
} else {
struct mii_bus *bus = phydev->mdio.bus;
int phy_addr = phydev->mdio.addr;
mutex_lock(&bus->mdio_lock);
mmd_phy_indirect(bus, phy_addr, devad, regnum);
/* Read the content of the MMD's selected register */
val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
mutex_unlock(&bus->mdio_lock);
}
return val;
}
EXPORT_SYMBOL(__phy_read_mmd);
/**
* phy_read_mmd - Convenience function for reading a register
* from an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to read from
* @regnum: The register on the MMD to read
*
* Same rules as for phy_read();
*/
int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
{
int ret;
mutex_lock(&phydev->mdio.bus->mdio_lock);
ret = __phy_read_mmd(phydev, devad, regnum);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
return ret;
}
EXPORT_SYMBOL(phy_read_mmd);
/**
* __phy_write_mmd - Convenience function for writing a register
* on an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to read from
* @regnum: The register on the MMD to read
* @val: value to write to @regnum
*
* Same rules as for __phy_write();
*/
int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
{
int ret;
if (regnum > (u16)~0 || devad > 32)
return -EINVAL;
if (phydev->drv->write_mmd) {
ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
} else if (phydev->is_c45) {
u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff);
ret = __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,
addr, val);
} else {
struct mii_bus *bus = phydev->mdio.bus;
int phy_addr = phydev->mdio.addr;
mmd_phy_indirect(bus, phy_addr, devad, regnum);
/* Write the data into MMD's selected register */
__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
ret = 0;
}
return ret;
}
EXPORT_SYMBOL(__phy_write_mmd);
/**
* phy_write_mmd - Convenience function for writing a register
* on an MMD on a given PHY.
@ -464,29 +522,10 @@ int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
{
int ret;
if (regnum > (u16)~0 || devad > 32)
return -EINVAL;
mutex_lock(&phydev->mdio.bus->mdio_lock);
ret = __phy_write_mmd(phydev, devad, regnum, val);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
if (phydev->drv->write_mmd) {
ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
} else if (phydev->is_c45) {
u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff);
ret = mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,
addr, val);
} else {
struct mii_bus *bus = phydev->mdio.bus;
int phy_addr = phydev->mdio.addr;
mutex_lock(&bus->mdio_lock);
mmd_phy_indirect(bus, phy_addr, devad, regnum);
/* Write the data into MMD's selected register */
__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
mutex_unlock(&bus->mdio_lock);
ret = 0;
}
return ret;
}
EXPORT_SYMBOL(phy_write_mmd);
@ -538,6 +577,57 @@ int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
}
EXPORT_SYMBOL_GPL(phy_modify);
/**
* __phy_modify_mmd - Convenience function for modifying a register on MMD
* @phydev: the phy_device struct
* @devad: the MMD containing register to modify
* @regnum: register number to modify
* @mask: bit mask of bits to clear
* @set: new value of bits set in mask to write to @regnum
*
* Unlocked helper function which allows a MMD register to be modified as
* new register value = (old register value & ~mask) | set
*/
int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
u16 mask, u16 set)
{
int ret;
ret = __phy_read_mmd(phydev, devad, regnum);
if (ret < 0)
return ret;
ret = __phy_write_mmd(phydev, devad, regnum, (ret & ~mask) | set);
return ret < 0 ? ret : 0;
}
EXPORT_SYMBOL_GPL(__phy_modify_mmd);
/**
* phy_modify_mmd - Convenience function for modifying a register on MMD
* @phydev: the phy_device struct
* @devad: the MMD containing register to modify
* @regnum: register number to modify
* @mask: bit mask of bits to clear
* @set: new value of bits set in mask to write to @regnum
*
* NOTE: MUST NOT be called from interrupt context,
* because the bus read/write functions may wait for an interrupt
* to conclude the operation.
*/
int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
u16 mask, u16 set)
{
int ret;
mutex_lock(&phydev->mdio.bus->mdio_lock);
ret = __phy_modify_mmd(phydev, devad, regnum, mask, set);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
return ret;
}
EXPORT_SYMBOL_GPL(phy_modify_mmd);
static int __phy_read_page(struct phy_device *phydev)
{
return phydev->drv->read_page(phydev);

11
drivers/net/phy/phy.c
View File

@ -1060,17 +1060,12 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
if (!phy_check_valid(phydev->speed, phydev->duplex, common))
goto eee_exit_err;
if (clk_stop_enable) {
if (clk_stop_enable)
/* Configure the PHY to stop receiving xMII
* clock while it is signaling LPI.
*/
int val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
if (val < 0)
return val;
val |= MDIO_PCS_CTRL1_CLKSTOP_EN;
phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, val);
}
phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
MDIO_PCS_CTRL1_CLKSTOP_EN);
return 0; /* EEE supported */
}

134
include/linux/phy.h
View File

@ -692,17 +692,6 @@ static inline bool phy_is_started(struct phy_device *phydev)
void phy_resolve_aneg_linkmode(struct phy_device *phydev);
/**
* phy_read_mmd - Convenience function for reading a register
* from an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to read from
* @regnum: The register on the MMD to read
*
* Same rules as for phy_read();
*/
int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
/**
* phy_read - Convenience function for reading a given PHY register
* @phydev: the phy_device struct
@ -758,9 +747,60 @@ static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
val);
}
/**
* phy_read_mmd - Convenience function for reading a register
* from an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to read from
* @regnum: The register on the MMD to read
*
* Same rules as for phy_read();
*/
int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
/**
* __phy_read_mmd - Convenience function for reading a register
* from an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to read from
* @regnum: The register on the MMD to read
*
* Same rules as for __phy_read();
*/
int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
/**
* phy_write_mmd - Convenience function for writing a register
* on an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to write to
* @regnum: The register on the MMD to read
* @val: value to write to @regnum
*
* Same rules as for phy_write();
*/
int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
/**
* __phy_write_mmd - Convenience function for writing a register
* on an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to write to
* @regnum: The register on the MMD to read
* @val: value to write to @regnum
*
* Same rules as for __phy_write();
*/
int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
u16 mask, u16 set);
int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
u16 mask, u16 set);
/**
* __phy_set_bits - Convenience function for setting bits in a PHY register
* @phydev: the phy_device struct
@ -810,6 +850,66 @@ static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val)
return phy_modify(phydev, regnum, val, 0);
}
/**
* __phy_set_bits_mmd - Convenience function for setting bits in a register
* on MMD
* @phydev: the phy_device struct
* @devad: the MMD containing register to modify
* @regnum: register number to modify
* @val: bits to set
*
* The caller must have taken the MDIO bus lock.
*/
static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad,
u32 regnum, u16 val)
{
return __phy_modify_mmd(phydev, devad, regnum, 0, val);
}
/**
* __phy_clear_bits_mmd - Convenience function for clearing bits in a register
* on MMD
* @phydev: the phy_device struct
* @devad: the MMD containing register to modify
* @regnum: register number to modify
* @val: bits to clear
*
* The caller must have taken the MDIO bus lock.
*/
static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad,
u32 regnum, u16 val)
{
return __phy_modify_mmd(phydev, devad, regnum, val, 0);
}
/**
* phy_set_bits_mmd - Convenience function for setting bits in a register
* on MMD
* @phydev: the phy_device struct
* @devad: the MMD containing register to modify
* @regnum: register number to modify
* @val: bits to set
*/
static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
u32 regnum, u16 val)
{
return phy_modify_mmd(phydev, devad, regnum, 0, val);
}
/**
* phy_clear_bits_mmd - Convenience function for clearing bits in a register
* on MMD
* @phydev: the phy_device struct
* @devad: the MMD containing register to modify
* @regnum: register number to modify
* @val: bits to clear
*/
static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
u32 regnum, u16 val)
{
return phy_modify_mmd(phydev, devad, regnum, val, 0);
}
/**
* phy_interrupt_is_valid - Convenience function for testing a given PHY irq
* @phydev: the phy_device struct
@ -886,18 +986,6 @@ static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev)
return phydev->is_pseudo_fixed_link;
}
/**
* phy_write_mmd - Convenience function for writing a register
* on an MMD on a given PHY.
* @phydev: The phy_device struct
* @devad: The MMD to read from
* @regnum: The register on the MMD to read
* @val: value to write to @regnum
*
* Same rules as for phy_write();
*/
int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
int phy_save_page(struct phy_device *phydev);
int phy_select_page(struct phy_device *phydev, int page);
int phy_restore_page(struct phy_device *phydev, int oldpage, int ret);