pinctrl: mediatek: Add EINT support to MTK pinctrl driver.
MTK SoC support external interrupt(EINT) from most SoC pins. Add EINT support to pinctrl driver. Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Maoguang Meng
Linus Walleij
parent
a6df410d42
commit
d9819eb9cd
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@ -314,6 +314,29 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
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.port_shf = 4,
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.port_mask = 0xf,
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.port_align = 4,
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.chip_type = MTK_CHIP_TYPE_BASE,
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.eint_offsets = {
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.name = "mt8135_eint",
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.stat = 0x000,
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.ack = 0x040,
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.mask = 0x080,
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.mask_set = 0x0c0,
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.mask_clr = 0x100,
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.sens = 0x140,
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.sens_set = 0x180,
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.sens_clr = 0x1c0,
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.pol = 0x300,
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.pol_set = 0x340,
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.pol_clr = 0x380,
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.dom_en = 0x400,
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.dbnc_ctrl = 0x500,
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.dbnc_set = 0x600,
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.dbnc_clr = 0x700,
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.port_mask = 7,
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.ports = 6,
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},
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.ap_num = 192,
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.db_cnt = 16,
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};
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static int mt8135_pinctrl_probe(struct platform_device *pdev)
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@ -31,6 +31,7 @@
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/delay.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include "../core.h"
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@ -560,6 +561,21 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
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reg_addr, mask, val);
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}
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static const struct mtk_desc_pin *
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mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
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{
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int i;
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const struct mtk_desc_pin *pin;
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for (i = 0; i < pctl->devdata->npins; i++) {
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pin = pctl->devdata->pins + i;
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if (pin->eint.eintnum == eint_num)
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return pin;
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}
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return NULL;
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}
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static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
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unsigned function,
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unsigned group)
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@ -647,6 +663,199 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
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return !!(read_val & bit);
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}
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static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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const struct mtk_desc_pin *pin;
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struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
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int irq;
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pin = pctl->devdata->pins + offset;
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if (pin->eint.eintnum == NO_EINT_SUPPORT)
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return -EINVAL;
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irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
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if (!irq)
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return -EINVAL;
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return irq;
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}
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static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
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{
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struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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const struct mtk_desc_pin *pin;
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int ret;
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pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
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if (!pin) {
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dev_err(pctl->dev, "Can not find pin\n");
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return -EINVAL;
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}
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ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
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if (ret) {
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dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
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irqd_to_hwirq(d));
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return ret;
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}
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/* set mux to INT mode */
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mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
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return 0;
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}
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static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
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{
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struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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const struct mtk_desc_pin *pin;
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pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
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if (!pin) {
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dev_err(pctl->dev, "Can not find pin\n");
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return;
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}
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gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
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}
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static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
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unsigned int eint_num, unsigned int offset)
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{
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unsigned int eint_base = 0;
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void __iomem *reg;
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if (eint_num >= pctl->devdata->ap_num)
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eint_base = pctl->devdata->ap_num;
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reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
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return reg;
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}
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/*
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* mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
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* @eint_num: the EINT number to setmtk_pinctrl
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*/
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static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
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unsigned int eint_num)
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{
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unsigned int sens;
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unsigned int bit = BIT(eint_num % 32);
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
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eint_offsets->sens);
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if (readl(reg) & bit)
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sens = MT_LEVEL_SENSITIVE;
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else
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sens = MT_EDGE_SENSITIVE;
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if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
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return 1;
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else
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return 0;
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}
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/*
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* mtk_eint_get_mask: To get the eint mask
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* @eint_num: the EINT number to get
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*/
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static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
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unsigned int eint_num)
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{
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unsigned int bit = BIT(eint_num % 32);
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
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eint_offsets->mask);
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return !!(readl(reg) & bit);
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}
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static void mtk_eint_mask(struct irq_data *d)
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{
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struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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u32 mask = BIT(d->hwirq & 0x1f);
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void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
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eint_offsets->mask_set);
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writel(mask, reg);
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}
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static void mtk_eint_unmask(struct irq_data *d)
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{
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struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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u32 mask = BIT(d->hwirq & 0x1f);
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void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
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eint_offsets->mask_clr);
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writel(mask, reg);
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}
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static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
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unsigned debounce)
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{
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struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
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int eint_num, virq, eint_offset;
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unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
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static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
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const struct mtk_desc_pin *pin;
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struct irq_data *d;
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pin = pctl->devdata->pins + offset;
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if (pin->eint.eintnum == NO_EINT_SUPPORT)
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return -EINVAL;
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eint_num = pin->eint.eintnum;
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virq = irq_find_mapping(pctl->domain, eint_num);
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eint_offset = (eint_num % 4) * 8;
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d = irq_get_irq_data(virq);
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set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
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clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
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if (!mtk_eint_can_en_debounce(pctl, eint_num))
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return -ENOSYS;
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dbnc = ARRAY_SIZE(dbnc_arr);
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for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
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if (debounce <= dbnc_arr[i]) {
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dbnc = i;
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break;
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}
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}
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if (!mtk_eint_get_mask(pctl, eint_num)) {
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mtk_eint_mask(d);
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unmask = 1;
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}
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clr_bit = 0xff << eint_offset;
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writel(clr_bit, pctl->eint_reg_base + clr_offset);
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bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
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eint_offset;
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rst = EINT_DBNC_RST_BIT << eint_offset;
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writel(rst | bit, pctl->eint_reg_base + set_offset);
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/* Delay a while (more than 2T) to wait for hw debounce counter reset
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work correctly */
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udelay(1);
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if (unmask == 1)
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mtk_eint_unmask(d);
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return 0;
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}
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static struct gpio_chip mtk_gpio_chip = {
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.owner = THIS_MODULE,
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.request = mtk_gpio_request,
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@ -655,9 +864,134 @@ static struct gpio_chip mtk_gpio_chip = {
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.direction_output = mtk_gpio_direction_output,
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.get = mtk_gpio_get,
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.set = mtk_gpio_set,
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.to_irq = mtk_gpio_to_irq,
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.set_debounce = mtk_gpio_set_debounce,
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.of_gpio_n_cells = 2,
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};
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static int mtk_eint_set_type(struct irq_data *d,
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unsigned int type)
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{
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struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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u32 mask = BIT(d->hwirq & 0x1f);
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void __iomem *reg;
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if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
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((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) ||
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((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
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dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
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d->irq, d->hwirq, type);
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return -EINVAL;
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}
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
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reg = mtk_eint_get_offset(pctl, d->hwirq,
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eint_offsets->pol_clr);
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writel(mask, reg);
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} else {
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reg = mtk_eint_get_offset(pctl, d->hwirq,
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eint_offsets->pol_set);
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writel(mask, reg);
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}
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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reg = mtk_eint_get_offset(pctl, d->hwirq,
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eint_offsets->sens_clr);
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writel(mask, reg);
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} else {
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reg = mtk_eint_get_offset(pctl, d->hwirq,
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eint_offsets->sens_set);
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writel(mask, reg);
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}
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return 0;
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}
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static void mtk_eint_ack(struct irq_data *d)
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{
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struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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u32 mask = BIT(d->hwirq & 0x1f);
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void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
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eint_offsets->ack);
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writel(mask, reg);
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}
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static struct irq_chip mtk_pinctrl_irq_chip = {
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.name = "mt-eint",
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.irq_mask = mtk_eint_mask,
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.irq_unmask = mtk_eint_unmask,
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.irq_ack = mtk_eint_ack,
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.irq_set_type = mtk_eint_set_type,
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.irq_request_resources = mtk_pinctrl_irq_request_resources,
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.irq_release_resources = mtk_pinctrl_irq_release_resources,
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};
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static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
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{
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
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unsigned int i;
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for (i = 0; i < pctl->devdata->ap_num; i += 32) {
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writel(0xffffffff, reg);
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reg += 4;
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}
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return 0;
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}
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static inline void
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mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
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{
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unsigned int rst, ctrl_offset;
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unsigned int bit, dbnc;
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
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dbnc = readl(pctl->eint_reg_base + ctrl_offset);
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bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
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if ((bit & dbnc) > 0) {
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ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
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rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
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writel(rst, pctl->eint_reg_base + ctrl_offset);
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}
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}
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static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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struct mtk_pinctrl *pctl = irq_get_handler_data(irq);
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unsigned int status, eint_num;
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int offset, index, virq;
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const struct mtk_eint_offsets *eint_offsets =
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&pctl->devdata->eint_offsets;
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void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
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chained_irq_enter(chip, desc);
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for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
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status = readl(reg);
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reg += 4;
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while (status) {
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offset = __ffs(status);
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index = eint_num + offset;
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virq = irq_find_mapping(pctl->domain, index);
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status &= ~BIT(offset);
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generic_handle_irq(virq);
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if (index < pctl->devdata->db_cnt)
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mtk_eint_debounce_process(pctl , index);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static int mtk_pctrl_build_state(struct platform_device *pdev)
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{
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struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
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@ -705,7 +1039,8 @@ int mtk_pctrl_init(struct platform_device *pdev,
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struct mtk_pinctrl *pctl;
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struct device_node *np = pdev->dev.of_node, *node;
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struct property *prop;
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int i, ret;
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struct resource *res;
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int i, ret, irq;
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pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
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if (!pctl)
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@ -786,6 +1121,48 @@ int mtk_pctrl_init(struct platform_device *pdev,
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goto chip_error;
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}
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/* Get EINT register base from dts. */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
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ret = -EINVAL;
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goto chip_error;
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}
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pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pctl->eint_reg_base)) {
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ret = -EINVAL;
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goto chip_error;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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dev_err(&pdev->dev, "couldn't parse and map irq\n");
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ret = -EINVAL;
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goto chip_error;
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||||
}
|
||||
|
||||
pctl->domain = irq_domain_add_linear(np,
|
||||
pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
|
||||
if (!pctl->domain) {
|
||||
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
|
||||
ret = -ENOMEM;
|
||||
goto chip_error;
|
||||
}
|
||||
|
||||
mtk_eint_init(pctl);
|
||||
for (i = 0; i < pctl->devdata->ap_num; i++) {
|
||||
int virq = irq_create_mapping(pctl->domain, i);
|
||||
|
||||
irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(virq, pctl);
|
||||
set_irq_flags(virq, IRQF_VALID);
|
||||
};
|
||||
|
||||
irq_set_chained_handler(irq, mtk_eint_irq_handler);
|
||||
irq_set_handler_data(irq, pctl);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
return 0;
|
||||
|
||||
chip_error:
|
||||
|
|
|
|||
|
|
@ -16,10 +16,16 @@
|
|||
#define __PINCTRL_MTK_COMMON_H
|
||||
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#define NO_EINT_SUPPORT 255
|
||||
#define MTK_CHIP_TYPE_BASE 0
|
||||
#define MTK_CHIP_TYPE_PMIC 1
|
||||
#define MT_EDGE_SENSITIVE 0
|
||||
#define MT_LEVEL_SENSITIVE 1
|
||||
#define EINT_DBNC_SET_DBNC_BITS 4
|
||||
#define EINT_DBNC_RST_BIT (0x1 << 1)
|
||||
#define EINT_DBNC_SET_EN (0x1 << 0)
|
||||
|
||||
struct mtk_desc_function {
|
||||
const char *name;
|
||||
|
|
@ -115,6 +121,27 @@ struct mtk_pin_drv_grp {
|
|||
.grp = _grp, \
|
||||
}
|
||||
|
||||
struct mtk_eint_offsets {
|
||||
const char *name;
|
||||
unsigned int stat;
|
||||
unsigned int ack;
|
||||
unsigned int mask;
|
||||
unsigned int mask_set;
|
||||
unsigned int mask_clr;
|
||||
unsigned int sens;
|
||||
unsigned int sens_set;
|
||||
unsigned int sens_clr;
|
||||
unsigned int pol;
|
||||
unsigned int pol_set;
|
||||
unsigned int pol_clr;
|
||||
unsigned int dom_en;
|
||||
unsigned int dbnc_ctrl;
|
||||
unsigned int dbnc_set;
|
||||
unsigned int dbnc_clr;
|
||||
u8 port_mask;
|
||||
u8 ports;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mtk_pinctrl_devdata - Provide HW GPIO related data.
|
||||
* @pins: An array describing all pins the pin controller affects.
|
||||
|
|
@ -165,6 +192,10 @@ struct mtk_pinctrl_devdata {
|
|||
unsigned char port_shf;
|
||||
unsigned char port_mask;
|
||||
unsigned char port_align;
|
||||
unsigned char chip_type;
|
||||
struct mtk_eint_offsets eint_offsets;
|
||||
unsigned int ap_num;
|
||||
unsigned int db_cnt;
|
||||
};
|
||||
|
||||
struct mtk_pinctrl {
|
||||
|
|
@ -177,6 +208,8 @@ struct mtk_pinctrl {
|
|||
const char **grp_names;
|
||||
struct pinctrl_dev *pctl_dev;
|
||||
const struct mtk_pinctrl_devdata *devdata;
|
||||
void __iomem *eint_reg_base;
|
||||
struct irq_domain *domain;
|
||||
};
|
||||
|
||||
int mtk_pctrl_init(struct platform_device *pdev,
|
||||
|
|
|
|||
Loading…
Reference in New Issue