Staging: MTD: Micron SPINAND Driver support
This patch adds support for Micron SPINAND via MTD. Signed-off-by: Mona Anonuevo <manonuevo@micron.com> Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Kamlakant Patel
Greg Kroah-Hartman
parent
77e73e8c90
commit
d974ce4f3b
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@ -136,6 +136,8 @@ source "drivers/staging/goldfish/Kconfig"
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source "drivers/staging/netlogic/Kconfig"
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source "drivers/staging/netlogic/Kconfig"
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source "drivers/staging/mt29f_spinand/Kconfig"
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source "drivers/staging/dwc2/Kconfig"
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source "drivers/staging/dwc2/Kconfig"
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source "drivers/staging/lustre/Kconfig"
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source "drivers/staging/lustre/Kconfig"
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@ -66,3 +66,4 @@ obj-$(CONFIG_USB_BTMTK) += btmtk_usb/
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obj-$(CONFIG_XILLYBUS) += xillybus/
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obj-$(CONFIG_XILLYBUS) += xillybus/
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obj-$(CONFIG_DGNC) += dgnc/
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obj-$(CONFIG_DGNC) += dgnc/
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obj-$(CONFIG_DGAP) += dgap/
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obj-$(CONFIG_DGAP) += dgap/
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obj-$(CONFIG_MTD_SPINAND_MT29F) += mt29f_spinand/
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@ -0,0 +1,16 @@
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config MTD_SPINAND_MT29F
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tristate "SPINAND Device Support for Micron"
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depends on MTD_NAND && SPI
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help
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This enables support for accessing Micron SPI NAND flash
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devices.
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If you have Micron SPI NAND chip say yes.
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If unsure, say no here.
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config MTD_SPINAND_ONDIEECC
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bool "Use SPINAND internal ECC"
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depends on MTD_SPINAND_MT29F
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help
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Internel ECC.
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Enables Hardware ECC support for Micron SPI NAND.
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@ -0,0 +1 @@
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obj-$(CONFIG_MTD_SPINAND_MT29F) += mt29f_spinand.o
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@ -0,0 +1,13 @@
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TODO:
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- Tested on XLP platform, needs to be tested on other platforms.
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- Checkpatch.pl cleanups
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- Sparce fixes.
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- Clean up coding style to meet kernel standard.
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Please send patches
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To:
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Kamlakant Patel <kamlakant.patel@broadcom.com>
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Cc:
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Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Mona Anonuevo <manonuevo@micron.com>
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linux-mtd@lists.infradead.org
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@ -0,0 +1,962 @@
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/*
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* Copyright (c) 2003-2013 Broadcom Corporation
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*
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* Copyright (c) 2009-2010 Micron Technology, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand.h>
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#include <linux/spi/spi.h>
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#include "mt29f_spinand.h"
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#define BUFSIZE (10 * 64 * 2048)
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#define CACHE_BUF 2112
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/*
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* OOB area specification layout: Total 32 available free bytes.
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*/
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#ifdef CONFIG_MTD_SPINAND_ONDIEECC
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static int enable_hw_ecc;
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static int enable_read_hw_ecc;
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static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
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{
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struct nand_chip *chip = (struct nand_chip *)mtd->priv;
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struct spinand_info *info = (struct spinand_info *)chip->priv;
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struct spinand_state *state = (struct spinand_state *)info->priv;
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return state;
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}
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static struct nand_ecclayout spinand_oob_64 = {
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.eccbytes = 24,
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.eccpos = {
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1, 2, 3, 4, 5, 6,
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17, 18, 19, 20, 21, 22,
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33, 34, 35, 36, 37, 38,
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49, 50, 51, 52, 53, 54, },
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.oobavail = 32,
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.oobfree = {
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{.offset = 8,
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.length = 8},
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{.offset = 24,
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.length = 8},
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{.offset = 40,
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.length = 8},
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{.offset = 56,
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.length = 8},
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}
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};
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#endif
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/*
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* spinand_cmd - to process a command to send to the SPI Nand
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* Description:
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* Set up the command buffer to send to the SPI controller.
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* The command buffer has to initialized to 0.
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*/
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static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
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{
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struct spi_message message;
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struct spi_transfer x[4];
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u8 dummy = 0xff;
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spi_message_init(&message);
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memset(x, 0, sizeof(x));
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x[0].len = 1;
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x[0].tx_buf = &cmd->cmd;
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spi_message_add_tail(&x[0], &message);
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if (cmd->n_addr) {
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x[1].len = cmd->n_addr;
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x[1].tx_buf = cmd->addr;
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spi_message_add_tail(&x[1], &message);
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}
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if (cmd->n_dummy) {
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x[2].len = cmd->n_dummy;
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x[2].tx_buf = &dummy;
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spi_message_add_tail(&x[2], &message);
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}
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if (cmd->n_tx) {
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x[3].len = cmd->n_tx;
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x[3].tx_buf = cmd->tx_buf;
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spi_message_add_tail(&x[3], &message);
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}
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if (cmd->n_rx) {
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x[3].len = cmd->n_rx;
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x[3].rx_buf = cmd->rx_buf;
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spi_message_add_tail(&x[3], &message);
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}
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return spi_sync(spi, &message);
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}
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/*
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* spinand_read_id- Read SPI Nand ID
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* Description:
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* Read ID: read two ID bytes from the SPI Nand device
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*/
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static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
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{
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int retval;
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u8 nand_id[3];
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struct spinand_cmd cmd = {0};
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cmd.cmd = CMD_READ_ID;
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cmd.n_rx = 3;
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cmd.rx_buf = &nand_id[0];
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retval = spinand_cmd(spi_nand, &cmd);
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if (retval < 0) {
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dev_err(&spi_nand->dev, "error %d reading id\n", retval);
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return retval;
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}
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id[0] = nand_id[1];
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id[1] = nand_id[2];
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return retval;
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}
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/*
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* spinand_read_status- send command 0xf to the SPI Nand status register
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* Description:
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* After read, write, or erase, the Nand device is expected to set the
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* busy status.
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* This function is to allow reading the status of the command: read,
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* write, and erase.
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* Once the status turns to be ready, the other status bits also are
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* valid status bits.
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*/
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static int spinand_read_status(struct spi_device *spi_nand, uint8_t *status)
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{
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struct spinand_cmd cmd = {0};
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int ret;
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cmd.cmd = CMD_READ_REG;
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cmd.n_addr = 1;
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cmd.addr[0] = REG_STATUS;
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cmd.n_rx = 1;
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cmd.rx_buf = status;
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ret = spinand_cmd(spi_nand, &cmd);
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if (ret < 0)
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dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
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return ret;
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}
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#define MAX_WAIT_JIFFIES (40 * HZ)
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static int wait_till_ready(struct spi_device *spi_nand)
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{
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unsigned long deadline;
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int retval;
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u8 stat = 0;
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deadline = jiffies + MAX_WAIT_JIFFIES;
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do {
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retval = spinand_read_status(spi_nand, &stat);
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if (retval < 0)
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return -1;
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else if (!(stat & 0x1))
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break;
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cond_resched();
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} while (!time_after_eq(jiffies, deadline));
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if ((stat & 0x1) == 0)
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return 0;
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return -1;
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}
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/**
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* spinand_get_otp- send command 0xf to read the SPI Nand OTP register
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* Description:
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* There is one bit( bit 0x10 ) to set or to clear the internal ECC.
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* Enable chip internal ECC, set the bit to 1
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* Disable chip internal ECC, clear the bit to 0
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*/
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static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
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{
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struct spinand_cmd cmd = {0};
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int retval;
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cmd.cmd = CMD_READ_REG;
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cmd.n_addr = 1;
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cmd.addr[0] = REG_OTP;
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cmd.n_rx = 1;
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cmd.rx_buf = otp;
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retval = spinand_cmd(spi_nand, &cmd);
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if (retval < 0)
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dev_err(&spi_nand->dev, "error %d get otp\n", retval);
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return retval;
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}
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/**
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* spinand_set_otp- send command 0x1f to write the SPI Nand OTP register
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* Description:
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* There is one bit( bit 0x10 ) to set or to clear the internal ECC.
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* Enable chip internal ECC, set the bit to 1
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* Disable chip internal ECC, clear the bit to 0
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*/
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static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
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{
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int retval;
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struct spinand_cmd cmd = {0};
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cmd.cmd = CMD_WRITE_REG,
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cmd.n_addr = 1,
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cmd.addr[0] = REG_OTP,
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cmd.n_tx = 1,
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cmd.tx_buf = otp,
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retval = spinand_cmd(spi_nand, &cmd);
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if (retval < 0)
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dev_err(&spi_nand->dev, "error %d set otp\n", retval);
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return retval;
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}
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#ifdef CONFIG_MTD_SPINAND_ONDIEECC
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/**
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* spinand_enable_ecc- send command 0x1f to write the SPI Nand OTP register
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* Description:
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* There is one bit( bit 0x10 ) to set or to clear the internal ECC.
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* Enable chip internal ECC, set the bit to 1
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* Disable chip internal ECC, clear the bit to 0
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*/
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static int spinand_enable_ecc(struct spi_device *spi_nand)
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{
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int retval;
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u8 otp = 0;
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retval = spinand_get_otp(spi_nand, &otp);
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if (retval < 0)
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return retval;
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if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
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return 0;
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} else {
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otp |= OTP_ECC_MASK;
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retval = spinand_set_otp(spi_nand, &otp);
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if (retval < 0)
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return retval;
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return spinand_get_otp(spi_nand, &otp);
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}
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}
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#endif
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static int spinand_disable_ecc(struct spi_device *spi_nand)
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{
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int retval;
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u8 otp = 0;
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retval = spinand_get_otp(spi_nand, &otp);
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if (retval < 0)
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return retval;
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if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
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otp &= ~OTP_ECC_MASK;
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retval = spinand_set_otp(spi_nand, &otp);
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if (retval < 0)
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return retval;
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return spinand_get_otp(spi_nand, &otp);
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} else
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return 0;
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}
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/**
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* spinand_write_enable- send command 0x06 to enable write or erase the
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* Nand cells
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* Description:
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* Before write and erase the Nand cells, the write enable has to be set.
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* After the write or erase, the write enable bit is automatically
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* cleared (status register bit 2)
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* Set the bit 2 of the status register has the same effect
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*/
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static int spinand_write_enable(struct spi_device *spi_nand)
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{
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struct spinand_cmd cmd = {0};
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cmd.cmd = CMD_WR_ENABLE;
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return spinand_cmd(spi_nand, &cmd);
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}
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static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
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{
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struct spinand_cmd cmd = {0};
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u16 row;
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row = page_id;
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cmd.cmd = CMD_READ;
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cmd.n_addr = 3;
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cmd.addr[1] = (u8)((row & 0xff00) >> 8);
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cmd.addr[2] = (u8)(row & 0x00ff);
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return spinand_cmd(spi_nand, &cmd);
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}
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/*
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* spinand_read_from_cache- send command 0x03 to read out the data from the
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* cache register(2112 bytes max)
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* Description:
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* The read can specify 1 to 2112 bytes of data read at the corresponding
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* locations.
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* No tRd delay.
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*/
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static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
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u16 byte_id, u16 len, u8 *rbuf)
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{
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struct spinand_cmd cmd = {0};
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u16 column;
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||||||
|
column = byte_id;
|
||||||
|
cmd.cmd = CMD_READ_RDM;
|
||||||
|
cmd.n_addr = 3;
|
||||||
|
cmd.addr[0] = (u8)((column & 0xff00) >> 8);
|
||||||
|
cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
|
||||||
|
cmd.addr[1] = (u8)(column & 0x00ff);
|
||||||
|
cmd.addr[2] = (u8)(0xff);
|
||||||
|
cmd.n_dummy = 0;
|
||||||
|
cmd.n_rx = len;
|
||||||
|
cmd.rx_buf = rbuf;
|
||||||
|
|
||||||
|
return spinand_cmd(spi_nand, &cmd);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* spinand_read_page-to read a page with:
|
||||||
|
* @page_id: the physical page number
|
||||||
|
* @offset: the location from 0 to 2111
|
||||||
|
* @len: number of bytes to read
|
||||||
|
* @rbuf: read buffer to hold @len bytes
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* The read includes two commands to the Nand: 0x13 and 0x03 commands
|
||||||
|
* Poll to read status to wait for tRD time.
|
||||||
|
*/
|
||||||
|
static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
|
||||||
|
u16 offset, u16 len, u8 *rbuf)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
u8 status = 0;
|
||||||
|
|
||||||
|
#ifdef CONFIG_MTD_SPINAND_ONDIEECC
|
||||||
|
if (enable_read_hw_ecc) {
|
||||||
|
if (spinand_enable_ecc(spi_nand) < 0)
|
||||||
|
dev_err(&spi_nand->dev, "enable HW ECC failed!");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
ret = spinand_read_page_to_cache(spi_nand, page_id);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (wait_till_ready(spi_nand))
|
||||||
|
dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
ret = spinand_read_status(spi_nand, &status);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(&spi_nand->dev,
|
||||||
|
"err %d read status register\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((status & STATUS_OIP_MASK) == STATUS_READY) {
|
||||||
|
if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
|
||||||
|
dev_err(&spi_nand->dev, "ecc error, page=%d\n",
|
||||||
|
page_id);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(&spi_nand->dev, "read from cache failed!!\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_MTD_SPINAND_ONDIEECC
|
||||||
|
if (enable_read_hw_ecc) {
|
||||||
|
ret = spinand_disable_ecc(spi_nand);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(&spi_nand->dev, "disable ecc failed!!\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
enable_read_hw_ecc = 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* spinand_program_data_to_cache--to write a page to cache with:
|
||||||
|
* @byte_id: the location to write to the cache
|
||||||
|
* @len: number of bytes to write
|
||||||
|
* @rbuf: read buffer to hold @len bytes
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* The write command used here is 0x84--indicating that the cache is
|
||||||
|
* not cleared first.
|
||||||
|
* Since it is writing the data to cache, there is no tPROG time.
|
||||||
|
*/
|
||||||
|
static int spinand_program_data_to_cache(struct spi_device *spi_nand,
|
||||||
|
u16 page_id, u16 byte_id, u16 len, u8 *wbuf)
|
||||||
|
{
|
||||||
|
struct spinand_cmd cmd = {0};
|
||||||
|
u16 column;
|
||||||
|
|
||||||
|
column = byte_id;
|
||||||
|
cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
|
||||||
|
cmd.n_addr = 2;
|
||||||
|
cmd.addr[0] = (u8)((column & 0xff00) >> 8);
|
||||||
|
cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
|
||||||
|
cmd.addr[1] = (u8)(column & 0x00ff);
|
||||||
|
cmd.n_tx = len;
|
||||||
|
cmd.tx_buf = wbuf;
|
||||||
|
|
||||||
|
return spinand_cmd(spi_nand, &cmd);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* spinand_program_execute--to write a page from cache to the Nand array with
|
||||||
|
* @page_id: the physical page location to write the page.
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* The write command used here is 0x10--indicating the cache is writing to
|
||||||
|
* the Nand array.
|
||||||
|
* Need to wait for tPROG time to finish the transaction.
|
||||||
|
*/
|
||||||
|
static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
|
||||||
|
{
|
||||||
|
struct spinand_cmd cmd = {0};
|
||||||
|
u16 row;
|
||||||
|
|
||||||
|
row = page_id;
|
||||||
|
cmd.cmd = CMD_PROG_PAGE_EXC;
|
||||||
|
cmd.n_addr = 3;
|
||||||
|
cmd.addr[1] = (u8)((row & 0xff00) >> 8);
|
||||||
|
cmd.addr[2] = (u8)(row & 0x00ff);
|
||||||
|
|
||||||
|
return spinand_cmd(spi_nand, &cmd);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* spinand_program_page--to write a page with:
|
||||||
|
* @page_id: the physical page location to write the page.
|
||||||
|
* @offset: the location from the cache starting from 0 to 2111
|
||||||
|
* @len: the number of bytes to write
|
||||||
|
* @wbuf: the buffer to hold the number of bytes
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* The commands used here are 0x06, 0x84, and 0x10--indicating that
|
||||||
|
* the write enable is first sent, the write cache command, and the
|
||||||
|
* write execute command.
|
||||||
|
* Poll to wait for the tPROG time to finish the transaction.
|
||||||
|
*/
|
||||||
|
static int spinand_program_page(struct spi_device *spi_nand,
|
||||||
|
u16 page_id, u16 offset, u16 len, u8 *buf)
|
||||||
|
{
|
||||||
|
int retval;
|
||||||
|
u8 status = 0;
|
||||||
|
uint8_t *wbuf;
|
||||||
|
#ifdef CONFIG_MTD_SPINAND_ONDIEECC
|
||||||
|
unsigned int i, j;
|
||||||
|
|
||||||
|
enable_read_hw_ecc = 0;
|
||||||
|
wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
|
||||||
|
spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
|
||||||
|
|
||||||
|
for (i = offset, j = 0; i < len; i++, j++)
|
||||||
|
wbuf[i] &= buf[j];
|
||||||
|
|
||||||
|
if (enable_hw_ecc) {
|
||||||
|
retval = spinand_enable_ecc(spi_nand);
|
||||||
|
if (retval < 0) {
|
||||||
|
dev_err(&spi_nand->dev, "enable ecc failed!!\n");
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
wbuf = buf;
|
||||||
|
#endif
|
||||||
|
retval = spinand_write_enable(spi_nand);
|
||||||
|
if (retval < 0) {
|
||||||
|
dev_err(&spi_nand->dev, "write enable failed!!\n");
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
if (wait_till_ready(spi_nand))
|
||||||
|
dev_err(&spi_nand->dev, "wait timedout!!!\n");
|
||||||
|
|
||||||
|
retval = spinand_program_data_to_cache(spi_nand, page_id,
|
||||||
|
offset, len, wbuf);
|
||||||
|
if (retval < 0)
|
||||||
|
return retval;
|
||||||
|
retval = spinand_program_execute(spi_nand, page_id);
|
||||||
|
if (retval < 0)
|
||||||
|
return retval;
|
||||||
|
while (1) {
|
||||||
|
retval = spinand_read_status(spi_nand, &status);
|
||||||
|
if (retval < 0) {
|
||||||
|
dev_err(&spi_nand->dev,
|
||||||
|
"error %d reading status register\n",
|
||||||
|
retval);
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((status & STATUS_OIP_MASK) == STATUS_READY) {
|
||||||
|
if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
|
||||||
|
dev_err(&spi_nand->dev,
|
||||||
|
"program error, page %d\n", page_id);
|
||||||
|
return -1;
|
||||||
|
} else
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#ifdef CONFIG_MTD_SPINAND_ONDIEECC
|
||||||
|
if (enable_hw_ecc) {
|
||||||
|
retval = spinand_disable_ecc(spi_nand);
|
||||||
|
if (retval < 0) {
|
||||||
|
dev_err(&spi_nand->dev, "disable ecc failed!!\n");
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
enable_hw_ecc = 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* spinand_erase_block_erase--to erase a page with:
|
||||||
|
* @block_id: the physical block location to erase.
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* The command used here is 0xd8--indicating an erase command to erase
|
||||||
|
* one block--64 pages
|
||||||
|
* Need to wait for tERS.
|
||||||
|
*/
|
||||||
|
static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
|
||||||
|
{
|
||||||
|
struct spinand_cmd cmd = {0};
|
||||||
|
u16 row;
|
||||||
|
|
||||||
|
row = block_id;
|
||||||
|
cmd.cmd = CMD_ERASE_BLK;
|
||||||
|
cmd.n_addr = 3;
|
||||||
|
cmd.addr[1] = (u8)((row & 0xff00) >> 8);
|
||||||
|
cmd.addr[2] = (u8)(row & 0x00ff);
|
||||||
|
|
||||||
|
return spinand_cmd(spi_nand, &cmd);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* spinand_erase_block--to erase a page with:
|
||||||
|
* @block_id: the physical block location to erase.
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* The commands used here are 0x06 and 0xd8--indicating an erase
|
||||||
|
* command to erase one block--64 pages
|
||||||
|
* It will first to enable the write enable bit (0x06 command),
|
||||||
|
* and then send the 0xd8 erase command
|
||||||
|
* Poll to wait for the tERS time to complete the tranaction.
|
||||||
|
*/
|
||||||
|
static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
|
||||||
|
{
|
||||||
|
int retval;
|
||||||
|
u8 status = 0;
|
||||||
|
|
||||||
|
retval = spinand_write_enable(spi_nand);
|
||||||
|
if (wait_till_ready(spi_nand))
|
||||||
|
dev_err(&spi_nand->dev, "wait timedout!!!\n");
|
||||||
|
|
||||||
|
retval = spinand_erase_block_erase(spi_nand, block_id);
|
||||||
|
while (1) {
|
||||||
|
retval = spinand_read_status(spi_nand, &status);
|
||||||
|
if (retval < 0) {
|
||||||
|
dev_err(&spi_nand->dev,
|
||||||
|
"error %d reading status register\n",
|
||||||
|
(int) retval);
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((status & STATUS_OIP_MASK) == STATUS_READY) {
|
||||||
|
if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
|
||||||
|
dev_err(&spi_nand->dev,
|
||||||
|
"erase error, block %d\n", block_id);
|
||||||
|
return -1;
|
||||||
|
} else
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_MTD_SPINAND_ONDIEECC
|
||||||
|
static int spinand_write_page_hwecc(struct mtd_info *mtd,
|
||||||
|
struct nand_chip *chip, const uint8_t *buf, int oob_required)
|
||||||
|
{
|
||||||
|
const uint8_t *p = buf;
|
||||||
|
int eccsize = chip->ecc.size;
|
||||||
|
int eccsteps = chip->ecc.steps;
|
||||||
|
|
||||||
|
enable_hw_ecc = 1;
|
||||||
|
chip->write_buf(mtd, p, eccsize * eccsteps);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
|
||||||
|
uint8_t *buf, int oob_required, int page)
|
||||||
|
{
|
||||||
|
u8 retval, status;
|
||||||
|
uint8_t *p = buf;
|
||||||
|
int eccsize = chip->ecc.size;
|
||||||
|
int eccsteps = chip->ecc.steps;
|
||||||
|
struct spinand_info *info = (struct spinand_info *)chip->priv;
|
||||||
|
|
||||||
|
enable_read_hw_ecc = 1;
|
||||||
|
|
||||||
|
chip->read_buf(mtd, p, eccsize * eccsteps);
|
||||||
|
if (oob_required)
|
||||||
|
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
retval = spinand_read_status(info->spi, &status);
|
||||||
|
if ((status & STATUS_OIP_MASK) == STATUS_READY) {
|
||||||
|
if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
|
||||||
|
pr_info("spinand: ECC error\n");
|
||||||
|
mtd->ecc_stats.failed++;
|
||||||
|
} else if ((status & STATUS_ECC_MASK) ==
|
||||||
|
STATUS_ECC_1BIT_CORRECTED)
|
||||||
|
mtd->ecc_stats.corrected++;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void spinand_select_chip(struct mtd_info *mtd, int dev)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint8_t spinand_read_byte(struct mtd_info *mtd)
|
||||||
|
{
|
||||||
|
struct spinand_state *state = mtd_to_state(mtd);
|
||||||
|
u8 data;
|
||||||
|
|
||||||
|
data = state->buf[state->buf_ptr];
|
||||||
|
state->buf_ptr++;
|
||||||
|
return data;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
||||||
|
{
|
||||||
|
struct spinand_info *info = (struct spinand_info *)chip->priv;
|
||||||
|
|
||||||
|
unsigned long timeo = jiffies;
|
||||||
|
int retval, state = chip->state;
|
||||||
|
u8 status;
|
||||||
|
|
||||||
|
if (state == FL_ERASING)
|
||||||
|
timeo += (HZ * 400) / 1000;
|
||||||
|
else
|
||||||
|
timeo += (HZ * 20) / 1000;
|
||||||
|
|
||||||
|
while (time_before(jiffies, timeo)) {
|
||||||
|
retval = spinand_read_status(info->spi, &status);
|
||||||
|
if ((status & STATUS_OIP_MASK) == STATUS_READY)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
cond_resched();
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void spinand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
|
||||||
|
{
|
||||||
|
|
||||||
|
struct spinand_state *state = mtd_to_state(mtd);
|
||||||
|
memcpy(state->buf + state->buf_ptr, buf, len);
|
||||||
|
state->buf_ptr += len;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void spinand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
||||||
|
{
|
||||||
|
struct spinand_state *state = mtd_to_state(mtd);
|
||||||
|
memcpy(buf, state->buf + state->buf_ptr, len);
|
||||||
|
state->buf_ptr += len;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* spinand_reset- send RESET command "0xff" to the Nand device.
|
||||||
|
*/
|
||||||
|
static void spinand_reset(struct spi_device *spi_nand)
|
||||||
|
{
|
||||||
|
struct spinand_cmd cmd = {0};
|
||||||
|
|
||||||
|
cmd.cmd = CMD_RESET;
|
||||||
|
|
||||||
|
if (spinand_cmd(spi_nand, &cmd) < 0)
|
||||||
|
pr_info("spinand reset failed!\n");
|
||||||
|
|
||||||
|
/* elapse 1ms before issuing any other command */
|
||||||
|
udelay(1000);
|
||||||
|
|
||||||
|
if (wait_till_ready(spi_nand))
|
||||||
|
dev_err(&spi_nand->dev, "wait timedout!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
|
||||||
|
int column, int page)
|
||||||
|
{
|
||||||
|
struct nand_chip *chip = (struct nand_chip *)mtd->priv;
|
||||||
|
struct spinand_info *info = (struct spinand_info *)chip->priv;
|
||||||
|
struct spinand_state *state = (struct spinand_state *)info->priv;
|
||||||
|
|
||||||
|
switch (command) {
|
||||||
|
/*
|
||||||
|
* READ0 - read in first 0x800 bytes
|
||||||
|
*/
|
||||||
|
case NAND_CMD_READ1:
|
||||||
|
case NAND_CMD_READ0:
|
||||||
|
state->buf_ptr = 0;
|
||||||
|
spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
|
||||||
|
break;
|
||||||
|
/* READOOB reads only the OOB because no ECC is performed. */
|
||||||
|
case NAND_CMD_READOOB:
|
||||||
|
state->buf_ptr = 0;
|
||||||
|
spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
|
||||||
|
break;
|
||||||
|
case NAND_CMD_RNDOUT:
|
||||||
|
state->buf_ptr = column;
|
||||||
|
break;
|
||||||
|
case NAND_CMD_READID:
|
||||||
|
state->buf_ptr = 0;
|
||||||
|
spinand_read_id(info->spi, (u8 *)state->buf);
|
||||||
|
break;
|
||||||
|
case NAND_CMD_PARAM:
|
||||||
|
state->buf_ptr = 0;
|
||||||
|
break;
|
||||||
|
/* ERASE1 stores the block and page address */
|
||||||
|
case NAND_CMD_ERASE1:
|
||||||
|
spinand_erase_block(info->spi, page);
|
||||||
|
break;
|
||||||
|
/* ERASE2 uses the block and page address from ERASE1 */
|
||||||
|
case NAND_CMD_ERASE2:
|
||||||
|
break;
|
||||||
|
/* SEQIN sets up the addr buffer and all registers except the length */
|
||||||
|
case NAND_CMD_SEQIN:
|
||||||
|
state->col = column;
|
||||||
|
state->row = page;
|
||||||
|
state->buf_ptr = 0;
|
||||||
|
break;
|
||||||
|
/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
|
||||||
|
case NAND_CMD_PAGEPROG:
|
||||||
|
spinand_program_page(info->spi, state->row, state->col,
|
||||||
|
state->buf_ptr, state->buf);
|
||||||
|
break;
|
||||||
|
case NAND_CMD_STATUS:
|
||||||
|
spinand_get_otp(info->spi, state->buf);
|
||||||
|
if (!(state->buf[0] & 0x80))
|
||||||
|
state->buf[0] = 0x80;
|
||||||
|
state->buf_ptr = 0;
|
||||||
|
break;
|
||||||
|
/* RESET command */
|
||||||
|
case NAND_CMD_RESET:
|
||||||
|
if (wait_till_ready(info->spi))
|
||||||
|
dev_err(&info->spi->dev, "WAIT timedout!!!\n");
|
||||||
|
/* a minimum of 250us must elapse before issuing RESET cmd*/
|
||||||
|
udelay(250);
|
||||||
|
spinand_reset(info->spi);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* spinand_lock_block- send write register 0x1f command to the Nand device
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* After power up, all the Nand blocks are locked. This function allows
|
||||||
|
* one to unlock the blocks, and so it can be written or erased.
|
||||||
|
*/
|
||||||
|
static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
|
||||||
|
{
|
||||||
|
struct spinand_cmd cmd = {0};
|
||||||
|
int ret;
|
||||||
|
u8 otp = 0;
|
||||||
|
|
||||||
|
ret = spinand_get_otp(spi_nand, &otp);
|
||||||
|
|
||||||
|
cmd.cmd = CMD_WRITE_REG;
|
||||||
|
cmd.n_addr = 1;
|
||||||
|
cmd.addr[0] = REG_BLOCK_LOCK;
|
||||||
|
cmd.n_tx = 1;
|
||||||
|
cmd.tx_buf = &lock;
|
||||||
|
|
||||||
|
ret = spinand_cmd(spi_nand, &cmd);
|
||||||
|
if (ret < 0)
|
||||||
|
dev_err(&spi_nand->dev, "error %d lock block\n", ret);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* spinand_probe - [spinand Interface]
|
||||||
|
* @spi_nand: registered device driver.
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* To set up the device driver parameters to make the device available.
|
||||||
|
*/
|
||||||
|
static int spinand_probe(struct spi_device *spi_nand)
|
||||||
|
{
|
||||||
|
struct mtd_info *mtd;
|
||||||
|
struct nand_chip *chip;
|
||||||
|
struct spinand_info *info;
|
||||||
|
struct spinand_state *state;
|
||||||
|
struct mtd_part_parser_data ppdata;
|
||||||
|
|
||||||
|
info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!info)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
info->spi = spi_nand;
|
||||||
|
|
||||||
|
spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
|
||||||
|
|
||||||
|
state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!state)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
info->priv = state;
|
||||||
|
state->buf_ptr = 0;
|
||||||
|
state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
|
||||||
|
if (!state->buf)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!chip)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
#ifdef CONFIG_MTD_SPINAND_ONDIEECC
|
||||||
|
chip->ecc.mode = NAND_ECC_HW;
|
||||||
|
chip->ecc.size = 0x200;
|
||||||
|
chip->ecc.bytes = 0x6;
|
||||||
|
chip->ecc.steps = 0x4;
|
||||||
|
|
||||||
|
chip->ecc.strength = 1;
|
||||||
|
chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
|
||||||
|
chip->ecc.layout = &spinand_oob_64;
|
||||||
|
chip->ecc.read_page = spinand_read_page_hwecc;
|
||||||
|
chip->ecc.write_page = spinand_write_page_hwecc;
|
||||||
|
#else
|
||||||
|
chip->ecc.mode = NAND_ECC_SOFT;
|
||||||
|
if (spinand_disable_ecc(spi_nand) < 0)
|
||||||
|
pr_info("%s: disable ecc failed!\n", __func__);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
chip->priv = info;
|
||||||
|
chip->read_buf = spinand_read_buf;
|
||||||
|
chip->write_buf = spinand_write_buf;
|
||||||
|
chip->read_byte = spinand_read_byte;
|
||||||
|
chip->cmdfunc = spinand_cmdfunc;
|
||||||
|
chip->waitfunc = spinand_wait;
|
||||||
|
chip->options |= NAND_CACHEPRG;
|
||||||
|
chip->select_chip = spinand_select_chip;
|
||||||
|
|
||||||
|
mtd = devm_kzalloc(&spi_nand->dev, sizeof(struct mtd_info), GFP_KERNEL);
|
||||||
|
if (!mtd)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
dev_set_drvdata(&spi_nand->dev, mtd);
|
||||||
|
|
||||||
|
mtd->priv = chip;
|
||||||
|
mtd->name = dev_name(&spi_nand->dev);
|
||||||
|
mtd->owner = THIS_MODULE;
|
||||||
|
mtd->oobsize = 64;
|
||||||
|
|
||||||
|
if (nand_scan(mtd, 1))
|
||||||
|
return -ENXIO;
|
||||||
|
|
||||||
|
ppdata.of_node = spi_nand->dev.of_node;
|
||||||
|
return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* spinand_remove: Remove the device driver
|
||||||
|
* @spi: the spi device.
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* To remove the device driver parameters and free up allocated memories.
|
||||||
|
*/
|
||||||
|
static int spinand_remove(struct spi_device *spi)
|
||||||
|
{
|
||||||
|
mtd_device_unregister(dev_get_drvdata(&spi->dev));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id spinand_dt[] = {
|
||||||
|
{ .compatible = "spinand,mt29f", },
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Device name structure description
|
||||||
|
*/
|
||||||
|
static struct spi_driver spinand_driver = {
|
||||||
|
.driver = {
|
||||||
|
.name = "mt29f",
|
||||||
|
.bus = &spi_bus_type,
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.of_match_table = spinand_dt,
|
||||||
|
},
|
||||||
|
.probe = spinand_probe,
|
||||||
|
.remove = spinand_remove,
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Device driver registration
|
||||||
|
*/
|
||||||
|
static int __init spinand_init(void)
|
||||||
|
{
|
||||||
|
return spi_register_driver(&spinand_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* unregister Device driver.
|
||||||
|
*/
|
||||||
|
static void __exit spinand_exit(void)
|
||||||
|
{
|
||||||
|
spi_unregister_driver(&spinand_driver);
|
||||||
|
}
|
||||||
|
module_init(spinand_init);
|
||||||
|
module_exit(spinand_exit);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("SPI NAND driver for Micron");
|
||||||
|
MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
|
|
@ -0,0 +1,107 @@
|
||||||
|
/*-
|
||||||
|
* Copyright 2013 Broadcom Corporation
|
||||||
|
*
|
||||||
|
* Copyright (c) 2009-2010 Micron Technology, Inc.
|
||||||
|
*
|
||||||
|
* This software is licensed under the terms of the GNU General Public
|
||||||
|
* License version 2, as published by the Free Software Foundation, and
|
||||||
|
* may be copied, distributed, and modified under those terms.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* Henry Pan <hspan@micron.com>
|
||||||
|
*
|
||||||
|
* based on nand.h
|
||||||
|
*/
|
||||||
|
#ifndef __LINUX_MTD_SPI_NAND_H
|
||||||
|
#define __LINUX_MTD_SPI_NAND_H
|
||||||
|
|
||||||
|
#include <linux/wait.h>
|
||||||
|
#include <linux/spinlock.h>
|
||||||
|
#include <linux/mtd/mtd.h>
|
||||||
|
|
||||||
|
/* cmd */
|
||||||
|
#define CMD_READ 0x13
|
||||||
|
#define CMD_READ_RDM 0x03
|
||||||
|
#define CMD_PROG_PAGE_CLRCACHE 0x02
|
||||||
|
#define CMD_PROG_PAGE 0x84
|
||||||
|
#define CMD_PROG_PAGE_EXC 0x10
|
||||||
|
#define CMD_ERASE_BLK 0xd8
|
||||||
|
#define CMD_WR_ENABLE 0x06
|
||||||
|
#define CMD_WR_DISABLE 0x04
|
||||||
|
#define CMD_READ_ID 0x9f
|
||||||
|
#define CMD_RESET 0xff
|
||||||
|
#define CMD_READ_REG 0x0f
|
||||||
|
#define CMD_WRITE_REG 0x1f
|
||||||
|
|
||||||
|
/* feature/ status reg */
|
||||||
|
#define REG_BLOCK_LOCK 0xa0
|
||||||
|
#define REG_OTP 0xb0
|
||||||
|
#define REG_STATUS 0xc0/* timing */
|
||||||
|
|
||||||
|
/* status */
|
||||||
|
#define STATUS_OIP_MASK 0x01
|
||||||
|
#define STATUS_READY (0 << 0)
|
||||||
|
#define STATUS_BUSY (1 << 0)
|
||||||
|
|
||||||
|
#define STATUS_E_FAIL_MASK 0x04
|
||||||
|
#define STATUS_E_FAIL (1 << 2)
|
||||||
|
|
||||||
|
#define STATUS_P_FAIL_MASK 0x08
|
||||||
|
#define STATUS_P_FAIL (1 << 3)
|
||||||
|
|
||||||
|
#define STATUS_ECC_MASK 0x30
|
||||||
|
#define STATUS_ECC_1BIT_CORRECTED (1 << 4)
|
||||||
|
#define STATUS_ECC_ERROR (2 << 4)
|
||||||
|
#define STATUS_ECC_RESERVED (3 << 4)
|
||||||
|
|
||||||
|
/*ECC enable defines*/
|
||||||
|
#define OTP_ECC_MASK 0x10
|
||||||
|
#define OTP_ECC_OFF 0
|
||||||
|
#define OTP_ECC_ON 1
|
||||||
|
|
||||||
|
#define ECC_DISABLED
|
||||||
|
#define ECC_IN_NAND
|
||||||
|
#define ECC_SOFT
|
||||||
|
|
||||||
|
/* block lock */
|
||||||
|
#define BL_ALL_LOCKED 0x38
|
||||||
|
#define BL_1_2_LOCKED 0x30
|
||||||
|
#define BL_1_4_LOCKED 0x28
|
||||||
|
#define BL_1_8_LOCKED 0x20
|
||||||
|
#define BL_1_16_LOCKED 0x18
|
||||||
|
#define BL_1_32_LOCKED 0x10
|
||||||
|
#define BL_1_64_LOCKED 0x08
|
||||||
|
#define BL_ALL_UNLOCKED 0
|
||||||
|
|
||||||
|
struct spinand_info {
|
||||||
|
struct nand_ecclayout *ecclayout;
|
||||||
|
struct spi_device *spi;
|
||||||
|
void *priv;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct spinand_state {
|
||||||
|
uint32_t col;
|
||||||
|
uint32_t row;
|
||||||
|
int buf_ptr;
|
||||||
|
u8 *buf;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct spinand_cmd {
|
||||||
|
u8 cmd;
|
||||||
|
u32 n_addr; /* Number of address */
|
||||||
|
u8 addr[3]; /* Reg Offset */
|
||||||
|
u32 n_dummy; /* Dummy use */
|
||||||
|
u32 n_tx; /* Number of tx bytes */
|
||||||
|
u8 *tx_buf; /* Tx buf */
|
||||||
|
u32 n_rx; /* Number of rx bytes */
|
||||||
|
u8 *rx_buf; /* Rx buf */
|
||||||
|
};
|
||||||
|
|
||||||
|
extern int spinand_mtd(struct mtd_info *mtd);
|
||||||
|
extern void spinand_mtd_release(struct mtd_info *mtd);
|
||||||
|
|
||||||
|
#endif /* __LINUX_MTD_SPI_NAND_H */
|
||||||
Loading…
Reference in New Issue