hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc 

* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
  pcmcia: pxa2xx/vpac270: free gpios on exist rather than requesting
  ARM: pxa/raumfeld: fix device name for codec ak4104
  ARM: pxa/raumfeld: display initialisation fixes
  ARM: pxa/raumfeld: adapt to upcoming hardware change
  ARM: pxa: fix gpio_to_chip() clash with gpiolib namespace
  genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd)
  arm: mach-vt8500: add forgotten irq_data conversion
  ARM: pxa168: correct nand pmu setting
  ARM: pxa910: correct nand pmu setting
  ARM: pxa: fix PGSR register address calculation
This commit is contained in:
Linus Torvalds 2011-07-12 14:19:51 -07:00
parent d1ca1a0048 24109afd17
commit d93a881dd7
12 changed files with 52 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-davinci/irq.c
View File

@ -53,7 +53,7 @@ davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq); gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
ct = gc->chip_types; ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit;

2
arch/arm/mach-mmp/pxa168.c
View File

@ -79,7 +79,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
static APBC_CLK(keypad, PXA168_KPC, 0, 32000); static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
static APMU_CLK(nand, NAND, 0x01db, 208000000); static APMU_CLK(nand, NAND, 0x19b, 156000000);
static APMU_CLK(lcd, LCD, 0x7f, 312000000); static APMU_CLK(lcd, LCD, 0x7f, 312000000);
/* device and clock bindings */ /* device and clock bindings */

2
arch/arm/mach-mmp/pxa910.c
View File

@ -110,7 +110,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
static APMU_CLK(nand, NAND, 0x01db, 208000000); static APMU_CLK(nand, NAND, 0x19b, 156000000);
static APMU_CLK(u2o, USB, 0x1b, 480000000); static APMU_CLK(u2o, USB, 0x1b, 480000000);
/* device and clock bindings */ /* device and clock bindings */

4
arch/arm/mach-pxa/mfp-pxa2xx.c
View File

@ -347,9 +347,9 @@ static int pxa2xx_mfp_suspend(void)
if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) && if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
(GPDR(i) & GPIO_bit(i))) { (GPDR(i) & GPIO_bit(i))) {
if (GPLR(i) & GPIO_bit(i)) if (GPLR(i) & GPIO_bit(i))
PGSR(i) |= GPIO_bit(i); PGSR(gpio_to_bank(i)) |= GPIO_bit(i);
else else
PGSR(i) &= ~GPIO_bit(i); PGSR(gpio_to_bank(i)) &= ~GPIO_bit(i);
} }
} }

36
arch/arm/mach-pxa/raumfeld.c
View File

@ -573,10 +573,10 @@ static struct pxafb_mode_info sharp_lq043t3dx02_mode = {
.xres = 480, .xres = 480,
.yres = 272, .yres = 272,
.bpp = 16, .bpp = 16,
.hsync_len = 4, .hsync_len = 41,
.left_margin = 2, .left_margin = 2,
.right_margin = 1, .right_margin = 1,
.vsync_len = 1, .vsync_len = 10,
.upper_margin = 3, .upper_margin = 3,
.lower_margin = 1, .lower_margin = 1,
.sync = 0, .sync = 0,
@ -596,29 +596,31 @@ static void __init raumfeld_lcd_init(void)
{ {
int ret; int ret;
pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info);
/* Earlier devices had the backlight regulator controlled
* via PWM, later versions use another controller for that */
if ((system_rev & 0xff) < 2) {
mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT;
pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1);
platform_device_register(&raumfeld_pwm_backlight_device);
} else
platform_device_register(&raumfeld_lt3593_device);
ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable"); ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable");
if (ret < 0) if (ret < 0)
pr_warning("Unable to request GPIO_TFT_VA_EN\n"); pr_warning("Unable to request GPIO_TFT_VA_EN\n");
else else
gpio_direction_output(GPIO_TFT_VA_EN, 1); gpio_direction_output(GPIO_TFT_VA_EN, 1);
msleep(100);
ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable"); ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable");
if (ret < 0) if (ret < 0)
pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n"); pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n");
else else
gpio_direction_output(GPIO_DISPLAY_ENABLE, 1); gpio_direction_output(GPIO_DISPLAY_ENABLE, 1);
/* Hardware revision 2 has the backlight regulator controlled
* by an LT3593, earlier and later devices use PWM for that. */
if ((system_rev & 0xff) == 2) {
platform_device_register(&raumfeld_lt3593_device);
} else {
mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT;
pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1);
platform_device_register(&raumfeld_pwm_backlight_device);
}
pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info);
platform_device_register(&pxa3xx_device_gcu); platform_device_register(&pxa3xx_device_gcu);
} }
@ -657,10 +659,10 @@ static struct lis3lv02d_platform_data lis3_pdata = {
#define SPI_AK4104 \ #define SPI_AK4104 \
{ \ { \
.modalias = "ak4104", \ .modalias = "ak4104-codec", \
.max_speed_hz = 10000, \ .max_speed_hz = 10000, \
.bus_num = 0, \ .bus_num = 0, \
.chip_select = 0, \ .chip_select = 0, \
.controller_data = (void *) GPIO_SPDIF_CS, \ .controller_data = (void *) GPIO_SPDIF_CS, \
} }

2
arch/arm/plat-orion/gpio.c
View File

@ -432,7 +432,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
ct->regs.ack = GPIO_EDGE_CAUSE_OFF; ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_ack = irq_gc_ack_clr_bit;
ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_set_type = gpio_irq_set_type; ct->chip.irq_set_type = gpio_irq_set_type;

10
arch/arm/plat-pxa/gpio.c
View File

@ -50,7 +50,7 @@ static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
return container_of(c, struct pxa_gpio_chip, chip)->regbase; return container_of(c, struct pxa_gpio_chip, chip)->regbase;
} }
static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio) static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
{ {
return &pxa_gpio_chips[gpio_to_bank(gpio)]; return &pxa_gpio_chips[gpio_to_bank(gpio)];
} }
@ -161,7 +161,7 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
int gpio = irq_to_gpio(d->irq); int gpio = irq_to_gpio(d->irq);
unsigned long gpdr, mask = GPIO_bit(gpio); unsigned long gpdr, mask = GPIO_bit(gpio);
c = gpio_to_chip(gpio); c = gpio_to_pxachip(gpio);
if (type == IRQ_TYPE_PROBE) { if (type == IRQ_TYPE_PROBE) {
/* Don't mess with enabled GPIOs using preconfigured edges or /* Don't mess with enabled GPIOs using preconfigured edges or
@ -230,7 +230,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
static void pxa_ack_muxed_gpio(struct irq_data *d) static void pxa_ack_muxed_gpio(struct irq_data *d)
{ {
int gpio = irq_to_gpio(d->irq); int gpio = irq_to_gpio(d->irq);
struct pxa_gpio_chip *c = gpio_to_chip(gpio); struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
__raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
} }
@ -238,7 +238,7 @@ static void pxa_ack_muxed_gpio(struct irq_data *d)
static void pxa_mask_muxed_gpio(struct irq_data *d) static void pxa_mask_muxed_gpio(struct irq_data *d)
{ {
int gpio = irq_to_gpio(d->irq); int gpio = irq_to_gpio(d->irq);
struct pxa_gpio_chip *c = gpio_to_chip(gpio); struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
uint32_t grer, gfer; uint32_t grer, gfer;
c->irq_mask &= ~GPIO_bit(gpio); c->irq_mask &= ~GPIO_bit(gpio);
@ -252,7 +252,7 @@ static void pxa_mask_muxed_gpio(struct irq_data *d)
static void pxa_unmask_muxed_gpio(struct irq_data *d) static void pxa_unmask_muxed_gpio(struct irq_data *d)
{ {
int gpio = irq_to_gpio(d->irq); int gpio = irq_to_gpio(d->irq);
struct pxa_gpio_chip *c = gpio_to_chip(gpio); struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
c->irq_mask |= GPIO_bit(gpio); c->irq_mask |= GPIO_bit(gpio);
update_edge_detect(c); update_edge_detect(c);

2
arch/arm/plat-s5p/irq-gpioint.c
View File

@ -152,7 +152,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
if (!gc) if (!gc)
return -ENOMEM; return -ENOMEM;
ct = gc->chip_types; ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = s5p_gpioint_set_type, ct->chip.irq_set_type = s5p_gpioint_set_type,

2
arch/arm/plat-samsung/irq-uart.c
View File

@ -55,7 +55,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
handle_level_irq); handle_level_irq);
ct = gc->chip_types; ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->regs.ack = S3C64XX_UINTP; ct->regs.ack = S3C64XX_UINTP;

4
drivers/pcmcia/pxa2xx_vpac270.c
View File

@ -76,10 +76,10 @@ static int vpac270_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
static void vpac270_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) static void vpac270_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
{ {
if (skt->nr == 0) if (skt->nr == 0)
gpio_request_array(vpac270_pcmcia_gpios, gpio_free_array(vpac270_pcmcia_gpios,
ARRAY_SIZE(vpac270_pcmcia_gpios)); ARRAY_SIZE(vpac270_pcmcia_gpios));
else else
gpio_request_array(vpac270_cf_gpios, gpio_free_array(vpac270_cf_gpios,
ARRAY_SIZE(vpac270_cf_gpios)); ARRAY_SIZE(vpac270_cf_gpios));
} }

3
include/linux/irq.h
View File

@ -676,7 +676,8 @@ void irq_gc_mask_disable_reg(struct irq_data *d);
void irq_gc_mask_set_bit(struct irq_data *d); void irq_gc_mask_set_bit(struct irq_data *d);
void irq_gc_mask_clr_bit(struct irq_data *d); void irq_gc_mask_clr_bit(struct irq_data *d);
void irq_gc_unmask_enable_reg(struct irq_data *d); void irq_gc_unmask_enable_reg(struct irq_data *d);
void irq_gc_ack(struct irq_data *d); void irq_gc_ack_set_bit(struct irq_data *d);
void irq_gc_ack_clr_bit(struct irq_data *d);
void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
void irq_gc_eoi(struct irq_data *d); void irq_gc_eoi(struct irq_data *d);
int irq_gc_set_wake(struct irq_data *d, unsigned int on); int irq_gc_set_wake(struct irq_data *d, unsigned int on);

18
kernel/irq/generic-chip.c
View File

@ -101,10 +101,10 @@ void irq_gc_unmask_enable_reg(struct irq_data *d)
} }
/** /**
* irq_gc_ack - Ack pending interrupt * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
* @d: irq_data * @d: irq_data
*/ */
void irq_gc_ack(struct irq_data *d) void irq_gc_ack_set_bit(struct irq_data *d)
{ {
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
u32 mask = 1 << (d->irq - gc->irq_base); u32 mask = 1 << (d->irq - gc->irq_base);
@ -114,6 +114,20 @@ void irq_gc_ack(struct irq_data *d)
irq_gc_unlock(gc); irq_gc_unlock(gc);
} }
/**
* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
* @d: irq_data
*/
void irq_gc_ack_clr_bit(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
u32 mask = ~(1 << (d->irq - gc->irq_base));
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
irq_gc_unlock(gc);
}
/** /**
* irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
* @d: irq_data * @d: irq_data