clk: qcom: pll: Add support for configuring SR PLLs
Some SR type PLLs need to be configured for a certain rate when linux boots. Add support for these types of PLLs so that we can program PLL15's rate on apq8064. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -166,7 +166,7 @@ const struct clk_ops clk_pll_vote_ops = {
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EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
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static void
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clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
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clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
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{
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u32 val;
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u32 mask;
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@ -175,7 +175,7 @@ clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
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regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
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/* Program bias count and lock count */
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val = 1 << PLL_BIAS_COUNT_SHIFT;
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val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT;
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mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
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mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
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regmap_update_bits(regmap, pll->mode_reg, mask, val);
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@ -212,11 +212,20 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
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regmap_update_bits(regmap, pll->config_reg, mask, val);
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}
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void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config, bool fsm_mode)
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{
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clk_pll_configure(pll, regmap, config);
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if (fsm_mode)
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clk_pll_set_fsm_mode(pll, regmap, 8);
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}
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EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
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void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config, bool fsm_mode)
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{
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clk_pll_configure(pll, regmap, config);
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if (fsm_mode)
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clk_pll_set_fsm_mode(pll, regmap);
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clk_pll_set_fsm_mode(pll, regmap, 0);
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}
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EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
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@ -60,6 +60,8 @@ struct pll_config {
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u32 aux_output_mask;
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};
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void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config, bool fsm_mode);
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void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config, bool fsm_mode);
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