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powerpc updates for 4.9 #2 

Freescale updates from Scott:
 
 "Highlights include qbman support (a prerequisite for datapath drivers
 such as ethernet), a PCI DMA fix+improvement, reset handler changes, more
 8xx optimizations, and some cleanups and fixes."
 
 Fixes:
  - selftests/powerpc: Add missing binaries to .gitignores (Michael Ellerman)
  - selftests/powerpc: Fix build break caused by EXPORT_SYMBOL changes (Michael Ellerman)
  - powerpc/pseries: Fix stack corruption in htpe code (Laurent Dufour)
  - powerpc/64s: Fix power4_fixup_nap placement (Nicholas Piggin)
  - powerpc/64: Fix incorrect return value from __copy_tofrom_user (Paul Mackerras)
  - powerpc/mm/hash64: Fix might_have_hea() check (Michael Ellerman)
 
 Other:
  - MAINTAINERS: Remove myself from PA Semi entries (Olof Johansson)
  - MAINTAINERS: Drop separate pseries entry (Michael Ellerman)
  - MAINTAINERS: Update powerpc website & add selftests (Michael Ellerman)
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Merge tag 'powerpc-4.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull more powerpc updates from Michael Ellerman:
 "Some more powerpc updates for 4.9:

  Freescale updates from Scott Wood:
   - qbman support (a prerequisite for datapath drivers such as ethernet)
   - a PCI DMA fix+improvement
   - reset handler changes
   - more 8xx optimizations
   - some cleanups and fixes.'

  Fixes:
   - selftests/powerpc: Add missing binaries to .gitignores (Michael Ellerman)
   - selftests/powerpc: Fix build break caused by EXPORT_SYMBOL changes (Michael Ellerman)
   - powerpc/pseries: Fix stack corruption in htpe code (Laurent Dufour)
   - powerpc/64s: Fix power4_fixup_nap placement (Nicholas Piggin)
   - powerpc/64: Fix incorrect return value from __copy_tofrom_user (Paul Mackerras)
   - powerpc/mm/hash64: Fix might_have_hea() check (Michael Ellerman)

  Other:
   - MAINTAINERS: Remove myself from PA Semi entries (Olof Johansson)
   - MAINTAINERS: Drop separate pseries entry (Michael Ellerman)
   - MAINTAINERS: Update powerpc website & add selftests (Michael Ellerman):

* tag 'powerpc-4.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (35 commits)
  powerpc/mm/hash64: Fix might_have_hea() check
  powerpc/64: Fix incorrect return value from __copy_tofrom_user
  powerpc/64s: Fix power4_fixup_nap placement
  powerpc/pseries: Fix stack corruption in htpe code
  selftests/powerpc: Fix build break caused by EXPORT_SYMBOL changes
  MAINTAINERS: Update powerpc website & add selftests
  MAINTAINERS: Drop separate pseries entry
  MAINTAINERS: Remove myself from PA Semi entries
  selftests/powerpc: Add missing binaries to .gitignores
  arch/powerpc: Add CONFIG_FSL_DPAA to corenetXX_smp_defconfig
  soc/qman: Add self-test for QMan driver
  soc/bman: Add self-test for BMan driver
  soc/fsl: Introduce DPAA 1.x QMan device driver
  soc/fsl: Introduce DPAA 1.x BMan device driver
  powerpc/8xx: make user addr DTLB miss the short path
  powerpc/8xx: Move additional DTLBMiss handlers out of exception area
  powerpc/8xx: use r3 to scratch CR in ITLBmiss
  soc/fsl/qe: fix gpio save_regs functions
  powerpc/8xx: add dedicated machine check handler
  powerpc/8xx: add system_reset_exception
  ...
This commit is contained in:
Linus Torvalds 2016-10-14 11:07:42 -07:00
parent 11ed3e0ef3 08bf75ba85
commit d8bfb96a2e
104 changed files with 8631 additions and 266 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
MAINTAINERS
View File

@ -7201,17 +7201,11 @@ F: drivers/lightnvm/
F: include/linux/lightnvm.h
F: include/uapi/linux/lightnvm.h
LINUX FOR IBM pSERIES (RS/6000)
M: Paul Mackerras <paulus@au.ibm.com>
W: http://www.ibm.com/linux/ltc/projects/ppc
S: Supported
F: arch/powerpc/boot/rs6000.h
LINUX FOR POWERPC (32-BIT AND 64-BIT)
M: Benjamin Herrenschmidt <benh@kernel.crashing.org>
M: Paul Mackerras <paulus@samba.org>
M: Michael Ellerman <mpe@ellerman.id.au>
W: http://www.penguinppc.org/
W: https://github.com/linuxppc/linux/wiki
L: linuxppc-dev@lists.ozlabs.org
Q: http://patchwork.ozlabs.org/project/linuxppc-dev/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
@ -7226,6 +7220,7 @@ F: drivers/net/ethernet/ibm/ibmvnic.*
F: drivers/pci/hotplug/pnv_php.c
F: drivers/pci/hotplug/rpa*
F: drivers/scsi/ibmvscsi/
F: tools/testing/selftests/powerpc
N: opal
N: /pmac
N: powermac
@ -7282,9 +7277,8 @@ F: arch/powerpc/platforms/83xx/
F: arch/powerpc/platforms/85xx/
LINUX FOR POWERPC PA SEMI PWRFICIENT
M: Olof Johansson <olof@lixom.net>
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
S: Orphan
F: arch/powerpc/platforms/pasemi/
F: drivers/*/*pasemi*
F: drivers/*/*/*pasemi*
@ -9019,15 +9013,13 @@ S: Maintained
F: drivers/net/wireless/intersil/p54/
PA SEMI ETHERNET DRIVER
M: Olof Johansson <olof@lixom.net>
L: netdev@vger.kernel.org
S: Maintained
S: Orphan
F: drivers/net/ethernet/pasemi/*
PA SEMI SMBUS DRIVER
M: Olof Johansson <olof@lixom.net>
L: linux-i2c@vger.kernel.org
S: Maintained
S: Orphan
F: drivers/i2c/busses/i2c-pasemi.c
PADATA PARALLEL EXECUTION MECHANISM

4
arch/powerpc/Makefile
View File

@ -318,12 +318,12 @@ mpc85xx_smp_defconfig:
PHONY += corenet32_smp_defconfig
corenet32_smp_defconfig:
$(call merge_into_defconfig,corenet_basic_defconfig,\
85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw)
85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw dpaa)
PHONY += corenet64_smp_defconfig
corenet64_smp_defconfig:
$(call merge_into_defconfig,corenet_basic_defconfig,\
85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw)
85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw dpaa)
PHONY += mpc86xx_defconfig
mpc86xx_defconfig:

1
arch/powerpc/configs/dpaa.config Normal file
View File

@ -0,0 +1 @@
CONFIG_FSL_DPAA=y

1
arch/powerpc/include/asm/cputable.h
View File

@ -43,6 +43,7 @@ extern int machine_check_e500mc(struct pt_regs *regs);
extern int machine_check_e500(struct pt_regs *regs);
extern int machine_check_e200(struct pt_regs *regs);
extern int machine_check_47x(struct pt_regs *regs);
int machine_check_8xx(struct pt_regs *regs);
extern void cpu_down_flush_e500v2(void);
extern void cpu_down_flush_e500mc(void);

6
arch/powerpc/include/asm/hw_irq.h
View File

@ -155,6 +155,8 @@ static inline unsigned long arch_local_irq_save(void)
unsigned long flags = arch_local_save_flags();
#ifdef CONFIG_BOOKE
asm volatile("wrteei 0" : : : "memory");
#elif defined(CONFIG_PPC_8xx)
wrtspr(SPRN_EID);
#else
SET_MSR_EE(flags & ~MSR_EE);
#endif
@ -165,6 +167,8 @@ static inline void arch_local_irq_disable(void)
{
#ifdef CONFIG_BOOKE
asm volatile("wrteei 0" : : : "memory");
#elif defined(CONFIG_PPC_8xx)
wrtspr(SPRN_EID);
#else
arch_local_irq_save();
#endif
@ -174,6 +178,8 @@ static inline void arch_local_irq_enable(void)
{
#ifdef CONFIG_BOOKE
asm volatile("wrteei 1" : : : "memory");
#elif defined(CONFIG_PPC_8xx)
wrtspr(SPRN_EIE);
#else
unsigned long msr = mfmsr();
SET_MSR_EE(msr | MSR_EE);

1
arch/powerpc/include/asm/ppc-opcode.h
View File

@ -152,6 +152,7 @@
#define PPC_INST_LWSYNC 0x7c2004ac
#define PPC_INST_SYNC 0x7c0004ac
#define PPC_INST_SYNC_MASK 0xfc0007fe
#define PPC_INST_ISYNC 0x4c00012c
#define PPC_INST_LXVD2X 0x7c000698
#define PPC_INST_MCRXR 0x7c000400
#define PPC_INST_MCRXR_MASK 0xfc0007fe

2
arch/powerpc/include/asm/reg.h
View File

@ -1250,6 +1250,8 @@ static inline void mtmsr_isync(unsigned long val)
: "r" ((unsigned long)(v)) \
: "memory")
#endif
#define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \
: : "memory")
extern unsigned long msr_check_and_set(unsigned long bits);
extern bool strict_msr_control;

4
arch/powerpc/include/asm/reg_8xx.h
View File

@ -25,6 +25,10 @@
#define SPRN_MD_RAM0 825
#define SPRN_MD_RAM1 826
/* Special MSR manipulation registers */
#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */
#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
/* Commands. Only the first few are available to the instruction cache.
*/
#define IDC_ENABLE 0x02000000 /* Cache enable */

1
arch/powerpc/kernel/cputable.c
View File

@ -1248,6 +1248,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.mmu_features = MMU_FTR_TYPE_8xx,
.icache_bsize = 16,
.dcache_bsize = 16,
.machine_check = machine_check_8xx,
.platform = "ppc823",
},
#endif /* CONFIG_8xx */

2
arch/powerpc/kernel/exceptions-64s.S
View File

@ -1377,7 +1377,7 @@ __end_interrupts:
DEFINE_FIXED_SYMBOL(__end_interrupts)
#ifdef CONFIG_PPC_970_NAP
TRAMP_REAL_BEGIN(power4_fixup_nap)
EXC_COMMON_BEGIN(power4_fixup_nap)
andc r9,r9,r10
std r9,TI_LOCAL_FLAGS(r11)
ld r10,_LINK(r1) /* make idle task do the */

136
arch/powerpc/kernel/head_8xx.S
View File

@ -226,7 +226,7 @@ i##n: \
ret_from_except)
/* System reset */
EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
/* Machine check */
. = 0x200
@ -321,7 +321,7 @@ SystemCall:
#endif
InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6
#if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
mtspr SPRN_SPRG_SCRATCH2, r3
#endif
EXCEPTION_PROLOG_0
@ -329,23 +329,20 @@ InstructionTLBMiss:
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
/* Only modules will cause ITLB Misses as we always
* pin the first 8MB of kernel memory */
mfspr r11, SPRN_SRR0 /* Get effective address of fault */
INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
mfcr r10
IS_KERNEL(r11, r11)
mfcr r3
IS_KERNEL(r11, r10)
#endif
mfspr r11, SPRN_M_TW /* Get level 1 table */
#if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
BRANCH_UNLESS_KERNEL(3f)
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
3:
mtcr r10
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
#else
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
mfspr r11, SPRN_M_TW /* Get level 1 table base address */
mtcr r3
#endif
/* Insert level 1 index */
rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
@ -377,58 +374,39 @@ InstructionTLBMiss:
MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
#if defined(CONFIG_8xx_CPU6) || defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
mfspr r3, SPRN_SPRG_SCRATCH2
#endif
EXCEPTION_EPILOG_0
rfi
/*
* Bottom part of DataStoreTLBMiss handler for IMMR area
* not enough space in the DataStoreTLBMiss area
*/
DTLBMissIMMR:
mtcr r10
/* Set 512k byte guarded page and mark it valid */
li r10, MD_PS512K | MD_GUARDED | MD_SVALID
MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
mfspr r10, SPRN_IMMR /* Get current IMMR */
rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
_PAGE_PRESENT | _PAGE_NO_CACHE
MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
li r11, RPN_PATTERN
mtspr SPRN_DAR, r11 /* Tag DAR */
EXCEPTION_EPILOG_0
rfi
. = 0x1200
DataStoreTLBMiss:
mtspr SPRN_SPRG_SCRATCH2, r3
EXCEPTION_PROLOG_0
mfcr r10
mfcr r3
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
mfspr r11, SPRN_MD_EPN
rlwinm r11, r11, 16, 0xfff8
mfspr r10, SPRN_MD_EPN
rlwinm r10, r10, 16, 0xfff8
cmpli cr0, r10, PAGE_OFFSET@h
mfspr r11, SPRN_M_TW /* Get level 1 table */
blt+ 3f
#ifndef CONFIG_PIN_TLB_IMMR
cmpli cr0, r11, VIRT_IMMR_BASE@h
cmpli cr0, r10, VIRT_IMMR_BASE@h
#endif
cmpli cr7, r11, PAGE_OFFSET@h
_ENTRY(DTLBMiss_cmp)
cmpli cr7, r10, (PAGE_OFFSET + 0x1800000)@h
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
#ifndef CONFIG_PIN_TLB_IMMR
_ENTRY(DTLBMiss_jmp)
beq- DTLBMissIMMR
#endif
bge- cr7, 4f
mfspr r11, SPRN_M_TW /* Get level 1 table */
blt cr7, DTLBMissLinear
3:
mtcr r10
#ifdef CONFIG_8xx_CPU6
mtspr SPRN_SPRG_SCRATCH2, r3
#endif
mtcr r3
mfspr r10, SPRN_MD_EPN
/* Insert level 1 index */
@ -481,30 +459,7 @@ _ENTRY(DTLBMiss_jmp)
MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
mfspr r3, SPRN_SPRG_SCRATCH2
#endif
mtspr SPRN_DAR, r11 /* Tag DAR */
EXCEPTION_EPILOG_0
rfi
4:
_ENTRY(DTLBMiss_cmp)
cmpli cr0, r11, (PAGE_OFFSET + 0x1800000)@h
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
bge- 3b
mtcr r10
/* Set 8M byte page and mark it valid */
li r10, MD_PS8MEG | MD_SVALID
MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
mfspr r10, SPRN_MD_EPN
rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
_PAGE_PRESENT
MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
li r11, RPN_PATTERN
mtspr SPRN_DAR, r11 /* Tag DAR */
EXCEPTION_EPILOG_0
rfi
@ -570,6 +525,43 @@ DARFixed:/* Return from dcbx instruction bug workaround */
. = 0x2000
/*
* Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.
* not enough space in the DataStoreTLBMiss area.
*/
DTLBMissIMMR:
mtcr r3
/* Set 512k byte guarded page and mark it valid */
li r10, MD_PS512K | MD_GUARDED | MD_SVALID
MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
mfspr r10, SPRN_IMMR /* Get current IMMR */
rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
_PAGE_PRESENT | _PAGE_NO_CACHE
MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
li r11, RPN_PATTERN
mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r3, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
rfi
DTLBMissLinear:
mtcr r3
/* Set 8M byte page and mark it valid */
li r11, MD_PS8MEG | MD_SVALID
MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
rlwinm r10, r10, 16, 0x0f800000 /* 8xx supports max 256Mb RAM */
ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
_PAGE_PRESENT
MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
li r11, RPN_PATTERN
mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r3, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
rfi
/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
* by decoding the registers used by the dcbx instruction and adding them.
* DAR is set to the calculated address.
@ -586,7 +578,9 @@ FixupDAR:/* Entry point for dcbx workaround. */
rlwinm r11, r10, 16, 0xfff8
_ENTRY(FixupDAR_cmp)
cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
blt- cr7, 200f
/* create physical page address from effective address */
tophys(r11, r10)
blt- cr7, 201f
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
/* Insert level 1 index */
3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
@ -616,10 +610,6 @@ _ENTRY(FixupDAR_cmp)
141: mfspr r10,SPRN_SPRG_SCRATCH2
b DARFixed /* Nope, go back to normal TLB processing */
/* create physical page address from effective address */
200: tophys(r11, r10)
b 201b
144: mfspr r10, SPRN_DSISR
rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
mtspr SPRN_DSISR, r10

27
arch/powerpc/kernel/setup-common.c
View File

@ -131,15 +131,26 @@ void machine_shutdown(void)
ppc_md.machine_shutdown();
}
static void machine_hang(void)
{
pr_emerg("System Halted, OK to turn off power\n");
local_irq_disable();
while (1)
;
}
void machine_restart(char *cmd)
{
machine_shutdown();
if (ppc_md.restart)
ppc_md.restart(cmd);
smp_send_stop();
printk(KERN_EMERG "System Halted, OK to turn off power\n");
local_irq_disable();
while (1) ;
do_kernel_restart(cmd);
mdelay(1000);
machine_hang();
}
void machine_power_off(void)
@ -147,10 +158,9 @@ void machine_power_off(void)
machine_shutdown();
if (pm_power_off)
pm_power_off();
smp_send_stop();
printk(KERN_EMERG "System Halted, OK to turn off power\n");
local_irq_disable();
while (1) ;
machine_hang();
}
/* Used by the G5 thermal driver */
EXPORT_SYMBOL_GPL(machine_power_off);
@ -163,10 +173,9 @@ void machine_halt(void)
machine_shutdown();
if (ppc_md.halt)
ppc_md.halt();
smp_send_stop();
printk(KERN_EMERG "System Halted, OK to turn off power\n");
local_irq_disable();
while (1) ;
machine_hang();
}

45
arch/powerpc/kernel/traps.c
View File

@ -273,7 +273,6 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
force_sig_info(signr, &info, current);
}
#ifdef CONFIG_PPC64
void system_reset_exception(struct pt_regs *regs)
{
/* See if any machine dependent calls */
@ -291,6 +290,7 @@ void system_reset_exception(struct pt_regs *regs)
/* What should we do here? We could issue a shutdown or hard reset. */
}
#ifdef CONFIG_PPC64
/*
* This function is called in real mode. Strictly no printk's please.
*
@ -352,12 +352,11 @@ static inline int check_io_access(struct pt_regs *regs)
* For the debug message, we look at the preceding
* load or store.
*/
if (*nip == 0x60000000) /* nop */
if (*nip == PPC_INST_NOP)
nip -= 2;
else if (*nip == 0x4c00012c) /* isync */
else if (*nip == PPC_INST_ISYNC)
--nip;
if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
/* sync or twi */
if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
unsigned int rb;
--nip;
@ -668,6 +667,31 @@ int machine_check_e200(struct pt_regs *regs)
return 0;
}
#elif defined(CONFIG_PPC_8xx)
int machine_check_8xx(struct pt_regs *regs)
{
unsigned long reason = get_mc_reason(regs);
pr_err("Machine check in kernel mode.\n");
pr_err("Caused by (from SRR1=%lx): ", reason);
if (reason & 0x40000000)
pr_err("Fetch error at address %lx\n", regs->nip);
else
pr_err("Data access error at address %lx\n", regs->dar);
#ifdef CONFIG_PCI
/* the qspan pci read routines can cause machine checks -- Cort
*
* yuck !!! that totally needs to go away ! There are better ways
* to deal with that than having a wart in the mcheck handler.
* -- BenH
*/
bad_page_fault(regs, regs->dar, SIGBUS);
return 1;
#else
return 0;
#endif
}
#else
int machine_check_generic(struct pt_regs *regs)
{
@ -727,17 +751,6 @@ void machine_check_exception(struct pt_regs *regs)
if (recover > 0)
goto bail;
#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
/* the qspan pci read routines can cause machine checks -- Cort
*
* yuck !!! that totally needs to go away ! There are better ways
* to deal with that than having a wart in the mcheck handler.
* -- BenH
*/
bad_page_fault(regs, regs->dar, SIGBUS);
goto bail;
#endif
if (debugger_fault_handler(regs))
goto bail;

2
arch/powerpc/lib/copyuser_64.S
View File

@ -359,6 +359,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
addi r3,r3,8
171:
177:
179:
addi r3,r3,8
370:
372:
@ -373,7 +374,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
173:
174:
175:
179:
181:
184:
186:

2
arch/powerpc/mm/hash_utils_64.c
View File

@ -529,7 +529,7 @@ static bool might_have_hea(void)
*/
#ifdef CONFIG_IBMEBUS
return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
!firmware_has_feature(FW_FEATURE_SPLPAR);
firmware_has_feature(FW_FEATURE_SPLPAR);
#else
return false;
#endif

4
arch/powerpc/platforms/82xx/Kconfig
View File

@ -30,8 +30,8 @@ config EP8248E
select 8272
select 8260
select FSL_SOC
select PHYLIB
select MDIO_BITBANG
select PHYLIB if NETDEVICES
select MDIO_BITBANG if PHYLIB
help
This enables support for the Embedded Planet EP8248E board.

4
arch/powerpc/platforms/82xx/ep8248e.c
View File

@ -298,7 +298,9 @@ static const struct of_device_id of_bus_ids[] __initconst = {
static int __init declare_of_platform_devices(void)
{
of_platform_bus_probe(NULL, of_bus_ids, NULL);
platform_driver_register(&ep8248e_mdio_driver);
if (IS_ENABLED(CONFIG_MDIO_BITBANG))
platform_driver_register(&ep8248e_mdio_driver);
return 0;
}

4
arch/powerpc/platforms/83xx/asp834x.c
View File

@ -30,9 +30,7 @@
*/
static void __init asp834x_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("asp834x_setup_arch()", 0);
mpc83xx_setup_arch();
mpc834x_usb_cfg();
}

5
arch/powerpc/platforms/83xx/km83xx.c
View File

@ -130,10 +130,7 @@ static void __init mpc83xx_km_setup_arch(void)
struct device_node *np;
#endif
if (ppc_md.progress)
ppc_md.progress("kmpbec83xx_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
#ifdef CONFIG_QUICC_ENGINE
np = of_find_node_by_name(NULL, "par_io");

8
arch/powerpc/platforms/83xx/misc.c
View File

@ -142,3 +142,11 @@ void __init mpc83xx_setup_pci(void)
mpc83xx_add_bridge(np);
}
#endif
void __init mpc83xx_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc83xx_setup_arch()", 0);
mpc83xx_setup_pci();
}

5
arch/powerpc/platforms/83xx/mpc830x_rdb.c
View File

@ -27,10 +27,7 @@
*/
static void __init mpc830x_rdb_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc830x_rdb_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
mpc831x_usb_cfg();
}

5
arch/powerpc/platforms/83xx/mpc831x_rdb.c
View File

@ -28,10 +28,7 @@
*/
static void __init mpc831x_rdb_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc831x_rdb_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
mpc831x_usb_cfg();
}

5
arch/powerpc/platforms/83xx/mpc832x_mds.c
View File

@ -58,8 +58,7 @@ static void __init mpc832x_sys_setup_arch(void)
struct device_node *np;
u8 __iomem *bcsr_regs = NULL;
if (ppc_md.progress)
ppc_md.progress("mpc832x_sys_setup_arch()", 0);
mpc83xx_setup_arch();
/* Map BCSR area */
np = of_find_node_by_name(NULL, "bcsr");
@ -71,8 +70,6 @@ static void __init mpc832x_sys_setup_arch(void)
of_node_put(np);
}
mpc83xx_setup_pci();
#ifdef CONFIG_QUICC_ENGINE
if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
par_io_init(np);

5
arch/powerpc/platforms/83xx/mpc832x_rdb.c
View File

@ -197,10 +197,7 @@ static void __init mpc832x_rdb_setup_arch(void)
struct device_node *np;
#endif
if (ppc_md.progress)
ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
#ifdef CONFIG_QUICC_ENGINE
if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {

5
arch/powerpc/platforms/83xx/mpc834x_itx.c
View File

@ -57,10 +57,7 @@ machine_device_initcall(mpc834x_itx, mpc834x_itx_declare_of_platform_devices);
*/
static void __init mpc834x_itx_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc834x_itx_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
mpc834x_usb_cfg();
}

5
arch/powerpc/platforms/83xx/mpc834x_mds.c
View File

@ -76,10 +76,7 @@ static int mpc834xemds_usb_cfg(void)
*/
static void __init mpc834x_mds_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc834x_mds_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
mpc834xemds_usb_cfg();
}

5
arch/powerpc/platforms/83xx/mpc836x_mds.c
View File

@ -66,8 +66,7 @@ static void __init mpc836x_mds_setup_arch(void)
struct device_node *np;
u8 __iomem *bcsr_regs = NULL;
if (ppc_md.progress)
ppc_md.progress("mpc836x_mds_setup_arch()", 0);
mpc83xx_setup_arch();
/* Map BCSR area */
np = of_find_node_by_name(NULL, "bcsr");
@ -79,8 +78,6 @@ static void __init mpc836x_mds_setup_arch(void)
of_node_put(np);
}
mpc83xx_setup_pci();
#ifdef CONFIG_QUICC_ENGINE
if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
par_io_init(np);

5
arch/powerpc/platforms/83xx/mpc836x_rdk.c
View File

@ -31,10 +31,7 @@ machine_device_initcall(mpc836x_rdk, mpc83xx_declare_of_platform_devices);
static void __init mpc836x_rdk_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc836x_rdk_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
}
/*

5
arch/powerpc/platforms/83xx/mpc837x_mds.c
View File

@ -79,10 +79,7 @@ out:
*/
static void __init mpc837x_mds_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc837x_mds_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
mpc837xmds_usb_cfg();
}

5
arch/powerpc/platforms/83xx/mpc837x_rdb.c
View File

@ -50,10 +50,7 @@ static void mpc837x_rdb_sd_cfg(void)
*/
static void __init mpc837x_rdb_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc837x_rdb_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
mpc837x_usb_cfg();
mpc837x_rdb_sd_cfg();
}

1
arch/powerpc/platforms/83xx/mpc83xx.h
View File

@ -86,5 +86,6 @@ extern void mpc83xx_setup_pci(void);
#endif
extern int mpc83xx_declare_of_platform_devices(void);
extern void mpc83xx_setup_arch(void);
#endif /* __MPC83XX_H__ */

5
arch/powerpc/platforms/83xx/sbc834x.c
View File

@ -47,10 +47,7 @@
*/
static void __init sbc834x_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("sbc834x_setup_arch()", 0);
mpc83xx_setup_pci();
mpc83xx_setup_arch();
}
machine_device_initcall(sbc834x, mpc83xx_declare_of_platform_devices);

2
arch/powerpc/platforms/85xx/Kconfig
View File

@ -72,7 +72,7 @@ config MPC85xx_CDS
config MPC85xx_MDS
bool "Freescale MPC85xx MDS"
select DEFAULT_UIMAGE
select PHYLIB
select PHYLIB if NETDEVICES
select HAS_RAPIDIO
select SWIOTLB
help

1
arch/powerpc/platforms/85xx/bsc913x_qds.c
View File

@ -72,7 +72,6 @@ define_machine(bsc9132_qds) {
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/bsc913x_rdb.c
View File

@ -59,7 +59,6 @@ define_machine(bsc9131_rdb) {
.setup_arch = bsc913x_rdb_setup_arch,
.init_IRQ = bsc913x_rdb_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/c293pcie.c
View File

@ -65,7 +65,6 @@ define_machine(c293_pcie) {
.setup_arch = c293_pcie_setup_arch,
.init_IRQ = c293_pcie_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/corenet_generic.c
View File

@ -225,7 +225,6 @@ define_machine(corenet_generic) {
#else
.get_irq = mpic_get_coreint_irq,
#endif
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PPC64

1
arch/powerpc/platforms/85xx/ge_imp3a.c
View File

@ -215,7 +215,6 @@ define_machine(ge_imp3a) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/mpc8536_ds.c
View File

@ -77,7 +77,6 @@ define_machine(mpc8536_ds) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/mpc85xx_ads.c
View File

@ -170,7 +170,6 @@ define_machine(mpc85xx_ads) {
.init_IRQ = mpc85xx_ads_pic_init,
.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

25
arch/powerpc/platforms/85xx/mpc85xx_cds.c
View File

@ -83,7 +83,8 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
return PCIBIOS_SUCCESSFUL;
}
static void __noreturn mpc85xx_cds_restart(char *cmd)
static int mpc85xx_cds_restart(struct notifier_block *this,
unsigned long mode, void *cmd)
{
struct pci_dev *dev;
u_char tmp;
@ -108,12 +109,25 @@ static void __noreturn mpc85xx_cds_restart(char *cmd)
}
/*
* If we can't find the VIA chip (maybe the P2P bridge is disabled)
* or the VIA chip reset didn't work, just use the default reset.
* If we can't find the VIA chip (maybe the P2P bridge is
* disabled) or the VIA chip reset didn't work, just return
* and let default reset sequence happen.
*/
fsl_rstcr_restart(NULL);
return NOTIFY_DONE;
}
static int mpc85xx_cds_restart_register(void)
{
static struct notifier_block restart_handler;
restart_handler.notifier_call = mpc85xx_cds_restart;
restart_handler.priority = 192;
return register_restart_handler(&restart_handler);
}
machine_arch_initcall(mpc85xx_cds, mpc85xx_cds_restart_register);
static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
{
u_char c;
@ -380,11 +394,8 @@ define_machine(mpc85xx_cds) {
.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
.get_irq = mpic_get_irq,
#ifdef CONFIG_PCI
.restart = mpc85xx_cds_restart,
.pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#else
.restart = fsl_rstcr_restart,
#endif
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,

3
arch/powerpc/platforms/85xx/mpc85xx_ds.c
View File

@ -204,7 +204,6 @@ define_machine(mpc8544_ds) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -219,7 +218,6 @@ define_machine(mpc8572_ds) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -234,7 +232,6 @@ define_machine(p2020_ds) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

12
arch/powerpc/platforms/85xx/mpc85xx_mds.c
View File

@ -63,6 +63,8 @@
#define DBG(fmt...)
#endif
#if IS_BUILTIN(CONFIG_PHYLIB)
#define MV88E1111_SCR 0x10
#define MV88E1111_SCR_125CLK 0x0010
static int mpc8568_fixup_125_clock(struct phy_device *phydev)
@ -152,6 +154,8 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
return err;
}
#endif
/* ************************************************************************
*
* Setup the architecture
@ -313,6 +317,7 @@ static void __init mpc85xx_mds_setup_arch(void)
swiotlb_detect_4g();
}
#if IS_BUILTIN(CONFIG_PHYLIB)
static int __init board_fixups(void)
{
@ -342,9 +347,12 @@ static int __init board_fixups(void)
return 0;
}
machine_arch_initcall(mpc8568_mds, board_fixups);
machine_arch_initcall(mpc8569_mds, board_fixups);
#endif
static int __init mpc85xx_publish_devices(void)
{
if (machine_is(mpc8568_mds))
@ -385,7 +393,6 @@ define_machine(mpc8568_mds) {
.setup_arch = mpc85xx_mds_setup_arch,
.init_IRQ = mpc85xx_mds_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI
@ -405,7 +412,6 @@ define_machine(mpc8569_mds) {
.setup_arch = mpc85xx_mds_setup_arch,
.init_IRQ = mpc85xx_mds_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI
@ -426,7 +432,6 @@ define_machine(p1021_mds) {
.setup_arch = mpc85xx_mds_setup_arch,
.init_IRQ = mpc85xx_mds_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI
@ -434,4 +439,3 @@ define_machine(p1021_mds) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
};

10
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
View File

@ -213,7 +213,6 @@ define_machine(p2020_rdb) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -228,7 +227,6 @@ define_machine(p1020_rdb) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -243,7 +241,6 @@ define_machine(p1021_rdb_pc) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -258,7 +255,6 @@ define_machine(p2020_rdb_pc) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -273,7 +269,6 @@ define_machine(p1025_rdb) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -288,7 +283,6 @@ define_machine(p1020_mbg_pc) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -303,7 +297,6 @@ define_machine(p1020_utm_pc) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -318,7 +311,6 @@ define_machine(p1020_rdb_pc) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -333,7 +325,6 @@ define_machine(p1020_rdb_pd) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -348,7 +339,6 @@ define_machine(p1024_rdb) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/mvme2500.c
View File

@ -66,7 +66,6 @@ define_machine(mvme2500) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/p1010rdb.c
View File

@ -79,7 +79,6 @@ define_machine(p1010_rdb) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/p1022_ds.c
View File

@ -568,7 +568,6 @@ define_machine(p1022_ds) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/p1022_rdk.c
View File

@ -148,7 +148,6 @@ define_machine(p1022_rdk) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/p1023_rdb.c
View File

@ -110,7 +110,6 @@ define_machine(p1023_rdb) {
.setup_arch = mpc85xx_rdb_setup_arch,
.init_IRQ = mpc85xx_rdb_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI

1
arch/powerpc/platforms/85xx/ppa8548.c
View File

@ -91,7 +91,6 @@ define_machine(ppa8548) {
.init_IRQ = ppa8548_pic_init,
.show_cpuinfo = ppa8548_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/qemu_e500.c
View File

@ -77,7 +77,6 @@ define_machine(qemu_e500) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_coreint_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/sbc8548.c
View File

@ -130,7 +130,6 @@ define_machine(sbc8548) {
.init_IRQ = sbc8548_pic_init,
.show_cpuinfo = sbc8548_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,

8
arch/powerpc/platforms/85xx/sgy_cts1000.c
View File

@ -38,18 +38,18 @@ static void gpio_halt_wfn(struct work_struct *work)
}
static DECLARE_WORK(gpio_halt_wq, gpio_halt_wfn);
static void gpio_halt_cb(void)
static void __noreturn gpio_halt_cb(void)
{
enum of_gpio_flags flags;
int trigger, gpio;
if (!halt_node)
return;
panic("No reset GPIO information was provided in DT\n");
gpio = of_get_gpio_flags(halt_node, 0, &flags);
if (!gpio_is_valid(gpio))
return;
panic("Provided GPIO is invalid\n");
trigger = (flags == OF_GPIO_ACTIVE_LOW);
@ -57,6 +57,8 @@ static void gpio_halt_cb(void)
/* Probably wont return */
gpio_set_value(gpio, trigger);
panic("Halt failed\n");
}
/* This IRQ means someone pressed the power button and it is waiting for us

1
arch/powerpc/platforms/85xx/socrates.c
View File

@ -91,7 +91,6 @@ define_machine(socrates) {
.setup_arch = socrates_setup_arch,
.init_IRQ = socrates_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/stx_gp3.c
View File

@ -103,7 +103,6 @@ define_machine(stx_gp3) {
.init_IRQ = stx_gp3_pic_init,
.show_cpuinfo = stx_gp3_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/tqm85xx.c
View File

@ -132,7 +132,6 @@ define_machine(tqm85xx) {
.init_IRQ = tqm85xx_pic_init,
.show_cpuinfo = tqm85xx_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/85xx/twr_p102x.c
View File

@ -140,7 +140,6 @@ define_machine(twr_p1025) {
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

3
arch/powerpc/platforms/85xx/xes_mpc85xx.c
View File

@ -167,7 +167,6 @@ define_machine(xes_mpc8572) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -182,7 +181,6 @@ define_machine(xes_mpc8548) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@ -197,7 +195,6 @@ define_machine(xes_mpc8540) {
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};

1
arch/powerpc/platforms/86xx/gef_ppc9a.c
View File

@ -204,7 +204,6 @@ define_machine(gef_ppc9a) {
.init_IRQ = gef_ppc9a_init_irq,
.show_cpuinfo = gef_ppc9a_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,

1
arch/powerpc/platforms/86xx/gef_sbc310.c
View File

@ -191,7 +191,6 @@ define_machine(gef_sbc310) {
.init_IRQ = gef_sbc310_init_irq,
.show_cpuinfo = gef_sbc310_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,

1
arch/powerpc/platforms/86xx/gef_sbc610.c
View File

@ -181,7 +181,6 @@ define_machine(gef_sbc610) {
.init_IRQ = gef_sbc610_init_irq,
.show_cpuinfo = gef_sbc610_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,

1
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
View File

@ -331,7 +331,6 @@ define_machine(mpc86xx_hpcd) {
.setup_arch = mpc86xx_hpcd_setup_arch,
.init_IRQ = mpc86xx_init_irq,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,

1
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
View File

@ -130,7 +130,6 @@ define_machine(mpc86xx_hpcn) {
.init_IRQ = mpc86xx_init_irq,
.show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,

1
arch/powerpc/platforms/86xx/mvme7100.c
View File

@ -111,7 +111,6 @@ define_machine(mvme7100) {
.setup_arch = mvme7100_setup_arch,
.init_IRQ = mpc86xx_init_irq,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,

1
arch/powerpc/platforms/86xx/sbc8641d.c
View File

@ -82,7 +82,6 @@ define_machine(sbc8641) {
.init_IRQ = mpc86xx_init_irq,
.show_cpuinfo = sbc8641_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,

4
arch/powerpc/platforms/pseries/lpar.c
View File

@ -393,7 +393,7 @@ static void __pSeries_lpar_hugepage_invalidate(unsigned long *slot,
unsigned long *vpn, int count,
int psize, int ssize)
{
unsigned long param[8];
unsigned long param[PLPAR_HCALL9_BUFSIZE];
int i = 0, pix = 0, rc;
unsigned long flags = 0;
int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
@ -522,7 +522,7 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
unsigned long flags = 0;
struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
unsigned long param[9];
unsigned long param[PLPAR_HCALL9_BUFSIZE];
unsigned long hash, index, shift, hidx, slot;
real_pte_t pte;
int psize, ssize;

2
arch/powerpc/sysdev/cpm1.c
View File

@ -233,8 +233,6 @@ void __init cpm_reset(void)
else
out_be32(&siu_conf->sc_sdcr, 1);
immr_unmap(siu_conf);
cpm_muram_init();
}
static DEFINE_SPINLOCK(cmd_lock);

4
arch/powerpc/sysdev/cpm2.c
View File

@ -66,10 +66,6 @@ void __init cpm2_reset(void)
cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
#endif
/* Reclaim the DP memory for our use.
*/
cpm_muram_init();
/* Tell everyone where the comm processor resides.
*/
cpmp = &cpm2_immr->im_cpm;

15
arch/powerpc/sysdev/cpm_common.c
View File

@ -37,6 +37,21 @@
#include <linux/of_gpio.h>
#endif
static int __init cpm_init(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
if (!np)
np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
if (!np)
return -ENODEV;
cpm_muram_init();
of_node_put(np);
return 0;
}
subsys_initcall(cpm_init);
#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
static u32 __iomem *cpm_udbg_txdesc;
static u8 __iomem *cpm_udbg_txbuf;

12
arch/powerpc/sysdev/fsl_pci.c
View File

@ -111,8 +111,7 @@ static struct pci_ops fsl_indirect_pcie_ops =
.write = indirect_write_config,
};
#define MAX_PHYS_ADDR_BITS 40
static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
static u64 pci64_dma_offset;
#ifdef CONFIG_SWIOTLB
static void setup_swiotlb_ops(struct pci_controller *hose)
@ -132,12 +131,10 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
return -EIO;
/*
* Fixup PCI devices that are able to DMA to above the physical
* address width of the SoC such that we can address any internal
* SoC address from across PCI if needed
* Fix up PCI devices that are able to DMA to the large inbound
* mapping that allows addressing any RAM address from across PCI.
*/
if ((dev_is_pci(dev)) &&
dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
set_dma_ops(dev, &dma_direct_ops);
set_dma_offset(dev, pci64_dma_offset);
}
@ -387,6 +384,7 @@ static void setup_pci_atmu(struct pci_controller *hose)
mem_log++;
piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
pci64_dma_offset = 1ULL << mem_log;
if (setup_inbound) {
/* Setup inbound memory window */

33
arch/powerpc/sysdev/fsl_soc.c
View File

@ -29,6 +29,7 @@
#include <linux/fsl_devices.h>
#include <linux/fs_enet_pd.h>
#include <linux/fs_uart_pd.h>
#include <linux/reboot.h>
#include <linux/atomic.h>
#include <asm/io.h>
@ -180,23 +181,38 @@ EXPORT_SYMBOL(get_baudrate);
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
static __be32 __iomem *rstcr;
static int fsl_rstcr_restart(struct notifier_block *this,
unsigned long mode, void *cmd)
{
local_irq_disable();
/* set reset control register */
out_be32(rstcr, 0x2); /* HRESET_REQ */
return NOTIFY_DONE;
}
static int __init setup_rstcr(void)
{
struct device_node *np;
static struct notifier_block restart_handler = {
.notifier_call = fsl_rstcr_restart,
.priority = 128,
};
for_each_node_by_name(np, "global-utilities") {
if ((of_get_property(np, "fsl,has-rstcr", NULL))) {
rstcr = of_iomap(np, 0) + 0xb0;
if (!rstcr)
if (!rstcr) {
printk (KERN_ERR "Error: reset control "
"register not mapped!\n");
} else {
register_restart_handler(&restart_handler);
}
break;
}
}
if (!rstcr && ppc_md.restart == fsl_rstcr_restart)
printk(KERN_ERR "No RSTCR register, warm reboot won't work\n");
of_node_put(np);
return 0;
@ -204,15 +220,6 @@ static int __init setup_rstcr(void)
arch_initcall(setup_rstcr);
void __noreturn fsl_rstcr_restart(char *cmd)
{
local_irq_disable();
if (rstcr)
/* set reset control register */
out_be32(rstcr, 0x2); /* HRESET_REQ */
while (1) ;
}
#endif
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)

2
arch/powerpc/sysdev/fsl_soc.h
View File

@ -19,8 +19,6 @@ extern u32 fsl_get_sys_freq(void);
struct spi_board_info;
struct device_node;
extern void __noreturn fsl_rstcr_restart(char *cmd);
/* The different ports that the DIU can be connected to */
enum fsl_diu_monitor_port {
FSL_DIU_PORT_DVI, /* DVI */

2
arch/powerpc/sysdev/mpic.c
View File

@ -1249,7 +1249,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
/* Pick the physical address from the device tree if unspecified */
if (!phys_addr) {
/* Check if it is DCR-based */
if (of_get_property(node, "dcr-reg", NULL)) {
if (of_property_read_bool(node, "dcr-reg")) {
flags |= MPIC_USES_DCR;
} else {
struct resource r;

1
drivers/soc/Kconfig
View File

@ -1,6 +1,7 @@
menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/bcm/Kconfig"
source "drivers/soc/fsl/qbman/Kconfig"
source "drivers/soc/fsl/qe/Kconfig"
source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig"

1
drivers/soc/fsl/Makefile
View File

@ -2,5 +2,6 @@
# Makefile for the Linux Kernel SOC fsl specific device drivers
#
obj-$(CONFIG_FSL_DPAA) += qbman/
obj-$(CONFIG_QUICC_ENGINE) += qe/
obj-$(CONFIG_CPM) += qe/

67
drivers/soc/fsl/qbman/Kconfig Normal file
View File

@ -0,0 +1,67 @@
menuconfig FSL_DPAA
bool "Freescale DPAA 1.x support"
depends on FSL_SOC_BOOKE
select GENERIC_ALLOCATOR
help
The Freescale Data Path Acceleration Architecture (DPAA) is a set of
hardware components on specific QorIQ multicore processors.
This architecture provides the infrastructure to support simplified
sharing of networking interfaces and accelerators by multiple CPUs.
The major h/w blocks composing DPAA are BMan and QMan.
The Buffer Manager (BMan) is a hardware buffer pool management block
that allows software and accelerators on the datapath to acquire and
release buffers in order to build frames.
The Queue Manager (QMan) is a hardware queue management block
that allows software and accelerators on the datapath to enqueue and
dequeue frames in order to communicate.
if FSL_DPAA
config FSL_DPAA_CHECKING
bool "Additional driver checking"
help
Compiles in additional checks, to sanity-check the drivers and
any use of the exported API. Not recommended for performance.
config FSL_BMAN_TEST
tristate "BMan self-tests"
help
Compile the BMan self-test code. These tests will
exercise the BMan APIs to confirm functionality
of both the software drivers and hardware device.
config FSL_BMAN_TEST_API
bool "High-level API self-test"
depends on FSL_BMAN_TEST
default y
help
This requires the presence of cpu-affine portals, and performs
high-level API testing with them (whichever portal(s) are affine
to the cpu(s) the test executes on).
config FSL_QMAN_TEST
tristate "QMan self-tests"
help
Compile self-test code for QMan.
config FSL_QMAN_TEST_API
bool "QMan high-level self-test"
depends on FSL_QMAN_TEST
default y
help
This requires the presence of cpu-affine portals, and performs
high-level API testing with them (whichever portal(s) are affine to
the cpu(s) the test executes on).
config FSL_QMAN_TEST_STASH
bool "QMan 'hot potato' data-stashing self-test"
depends on FSL_QMAN_TEST
default y
help
This performs a "hot potato" style test enqueuing/dequeuing a frame
across a series of FQs scheduled to different portals (and cpus), with
DQRR, data and context stashing always on.
endif # FSL_DPAA

12
drivers/soc/fsl/qbman/Makefile Normal file
View File

@ -0,0 +1,12 @@
obj-$(CONFIG_FSL_DPAA) += bman_ccsr.o qman_ccsr.o \
bman_portal.o qman_portal.o \
bman.o qman.o
obj-$(CONFIG_FSL_BMAN_TEST) += bman-test.o
bman-test-y = bman_test.o
bman-test-$(CONFIG_FSL_BMAN_TEST_API) += bman_test_api.o
obj-$(CONFIG_FSL_QMAN_TEST) += qman-test.o
qman-test-y = qman_test.o
qman-test-$(CONFIG_FSL_QMAN_TEST_API) += qman_test_api.o
qman-test-$(CONFIG_FSL_QMAN_TEST_STASH) += qman_test_stash.o

797
drivers/soc/fsl/qbman/bman.c Normal file
View File

@ -0,0 +1,797 @@
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bman_priv.h"
#define IRQNAME "BMan portal %d"
#define MAX_IRQNAME 16 /* big enough for "BMan portal %d" */
/* Portal register assists */
/* Cache-inhibited register offsets */
#define BM_REG_RCR_PI_CINH 0x0000
#define BM_REG_RCR_CI_CINH 0x0004
#define BM_REG_RCR_ITR 0x0008
#define BM_REG_CFG 0x0100
#define BM_REG_SCN(n) (0x0200 + ((n) << 2))
#define BM_REG_ISR 0x0e00
#define BM_REG_IER 0x0e04
#define BM_REG_ISDR 0x0e08
#define BM_REG_IIR 0x0e0c
/* Cache-enabled register offsets */
#define BM_CL_CR 0x0000
#define BM_CL_RR0 0x0100
#define BM_CL_RR1 0x0140
#define BM_CL_RCR 0x1000
#define BM_CL_RCR_PI_CENA 0x3000
#define BM_CL_RCR_CI_CENA 0x3100
/*
* Portal modes.
* Enum types;
* pmode == production mode
* cmode == consumption mode,
* Enum values use 3 letter codes. First letter matches the portal mode,
* remaining two letters indicate;
* ci == cache-inhibited portal register
* ce == cache-enabled portal register
* vb == in-band valid-bit (cache-enabled)
*/
enum bm_rcr_pmode { /* matches BCSP_CFG::RPM */
bm_rcr_pci = 0, /* PI index, cache-inhibited */
bm_rcr_pce = 1, /* PI index, cache-enabled */
bm_rcr_pvb = 2 /* valid-bit */
};
enum bm_rcr_cmode { /* s/w-only */
bm_rcr_cci, /* CI index, cache-inhibited */
bm_rcr_cce /* CI index, cache-enabled */
};
/* --- Portal structures --- */
#define BM_RCR_SIZE 8
/* Release Command */
struct bm_rcr_entry {
union {
struct {
u8 _ncw_verb; /* writes to this are non-coherent */
u8 bpid; /* used with BM_RCR_VERB_CMD_BPID_SINGLE */
u8 __reserved1[62];
};
struct bm_buffer bufs[8];
};
};
#define BM_RCR_VERB_VBIT 0x80
#define BM_RCR_VERB_CMD_MASK 0x70 /* one of two values; */
#define BM_RCR_VERB_CMD_BPID_SINGLE 0x20
#define BM_RCR_VERB_CMD_BPID_MULTI 0x30
#define BM_RCR_VERB_BUFCOUNT_MASK 0x0f /* values 1..8 */
struct bm_rcr {
struct bm_rcr_entry *ring, *cursor;
u8 ci, available, ithresh, vbit;
#ifdef CONFIG_FSL_DPAA_CHECKING
u32 busy;
enum bm_rcr_pmode pmode;
enum bm_rcr_cmode cmode;
#endif
};
/* MC (Management Command) command */
struct bm_mc_command {
u8 _ncw_verb; /* writes to this are non-coherent */
u8 bpid; /* used by acquire command */
u8 __reserved[62];
};
#define BM_MCC_VERB_VBIT 0x80
#define BM_MCC_VERB_CMD_MASK 0x70 /* where the verb contains; */
#define BM_MCC_VERB_CMD_ACQUIRE 0x10
#define BM_MCC_VERB_CMD_QUERY 0x40
#define BM_MCC_VERB_ACQUIRE_BUFCOUNT 0x0f /* values 1..8 go here */
/* MC result, Acquire and Query Response */
union bm_mc_result {
struct {
u8 verb;
u8 bpid;
u8 __reserved[62];
};
struct bm_buffer bufs[8];
};
#define BM_MCR_VERB_VBIT 0x80
#define BM_MCR_VERB_CMD_MASK BM_MCC_VERB_CMD_MASK
#define BM_MCR_VERB_CMD_ACQUIRE BM_MCC_VERB_CMD_ACQUIRE
#define BM_MCR_VERB_CMD_QUERY BM_MCC_VERB_CMD_QUERY
#define BM_MCR_VERB_CMD_ERR_INVALID 0x60
#define BM_MCR_VERB_CMD_ERR_ECC 0x70
#define BM_MCR_VERB_ACQUIRE_BUFCOUNT BM_MCC_VERB_ACQUIRE_BUFCOUNT /* 0..8 */
#define BM_MCR_TIMEOUT 10000 /* us */
struct bm_mc {
struct bm_mc_command *cr;
union bm_mc_result *rr;
u8 rridx, vbit;
#ifdef CONFIG_FSL_DPAA_CHECKING
enum {
/* Can only be _mc_start()ed */
mc_idle,
/* Can only be _mc_commit()ed or _mc_abort()ed */
mc_user,
/* Can only be _mc_retry()ed */
mc_hw
} state;
#endif
};
struct bm_addr {
void __iomem *ce; /* cache-enabled */
void __iomem *ci; /* cache-inhibited */
};
struct bm_portal {
struct bm_addr addr;
struct bm_rcr rcr;
struct bm_mc mc;
} ____cacheline_aligned;
/* Cache-inhibited register access. */
static inline u32 bm_in(struct bm_portal *p, u32 offset)
{
return __raw_readl(p->addr.ci + offset);
}
static inline void bm_out(struct bm_portal *p, u32 offset, u32 val)
{
__raw_writel(val, p->addr.ci + offset);
}
/* Cache Enabled Portal Access */
static inline void bm_cl_invalidate(struct bm_portal *p, u32 offset)
{
dpaa_invalidate(p->addr.ce + offset);
}
static inline void bm_cl_touch_ro(struct bm_portal *p, u32 offset)
{
dpaa_touch_ro(p->addr.ce + offset);
}
static inline u32 bm_ce_in(struct bm_portal *p, u32 offset)
{
return __raw_readl(p->addr.ce + offset);
}
struct bman_portal {
struct bm_portal p;
/* interrupt sources processed by portal_isr(), configurable */
unsigned long irq_sources;
/* probing time config params for cpu-affine portals */
const struct bm_portal_config *config;
char irqname[MAX_IRQNAME];
};
static cpumask_t affine_mask;
static DEFINE_SPINLOCK(affine_mask_lock);
static DEFINE_PER_CPU(struct bman_portal, bman_affine_portal);
static inline struct bman_portal *get_affine_portal(void)
{
return &get_cpu_var(bman_affine_portal);
}
static inline void put_affine_portal(void)
{
put_cpu_var(bman_affine_portal);
}
/*
* This object type refers to a pool, it isn't *the* pool. There may be
* more than one such object per BMan buffer pool, eg. if different users of the
* pool are operating via different portals.
*/
struct bman_pool {
/* index of the buffer pool to encapsulate (0-63) */
u32 bpid;
/* Used for hash-table admin when using depletion notifications. */
struct bman_portal *portal;
struct bman_pool *next;
};
static u32 poll_portal_slow(struct bman_portal *p, u32 is);
static irqreturn_t portal_isr(int irq, void *ptr)
{
struct bman_portal *p = ptr;
struct bm_portal *portal = &p->p;
u32 clear = p->irq_sources;
u32 is = bm_in(portal, BM_REG_ISR) & p->irq_sources;
if (unlikely(!is))
return IRQ_NONE;
clear |= poll_portal_slow(p, is);
bm_out(portal, BM_REG_ISR, clear);
return IRQ_HANDLED;
}
/* --- RCR API --- */
#define RCR_SHIFT ilog2(sizeof(struct bm_rcr_entry))
#define RCR_CARRY (uintptr_t)(BM_RCR_SIZE << RCR_SHIFT)
/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
static struct bm_rcr_entry *rcr_carryclear(struct bm_rcr_entry *p)
{
uintptr_t addr = (uintptr_t)p;
addr &= ~RCR_CARRY;
return (struct bm_rcr_entry *)addr;
}
#ifdef CONFIG_FSL_DPAA_CHECKING
/* Bit-wise logic to convert a ring pointer to a ring index */
static int rcr_ptr2idx(struct bm_rcr_entry *e)
{
return ((uintptr_t)e >> RCR_SHIFT) & (BM_RCR_SIZE - 1);
}
#endif
/* Increment the 'cursor' ring pointer, taking 'vbit' into account */
static inline void rcr_inc(struct bm_rcr *rcr)
{
/* increment to the next RCR pointer and handle overflow and 'vbit' */
struct bm_rcr_entry *partial = rcr->cursor + 1;
rcr->cursor = rcr_carryclear(partial);
if (partial != rcr->cursor)
rcr->vbit ^= BM_RCR_VERB_VBIT;
}
static int bm_rcr_get_avail(struct bm_portal *portal)
{
struct bm_rcr *rcr = &portal->rcr;
return rcr->available;
}
static int bm_rcr_get_fill(struct bm_portal *portal)
{
struct bm_rcr *rcr = &portal->rcr;
return BM_RCR_SIZE - 1 - rcr->available;
}
static void bm_rcr_set_ithresh(struct bm_portal *portal, u8 ithresh)
{
struct bm_rcr *rcr = &portal->rcr;
rcr->ithresh = ithresh;
bm_out(portal, BM_REG_RCR_ITR, ithresh);
}
static void bm_rcr_cce_prefetch(struct bm_portal *portal)
{
__maybe_unused struct bm_rcr *rcr = &portal->rcr;
DPAA_ASSERT(rcr->cmode == bm_rcr_cce);
bm_cl_touch_ro(portal, BM_CL_RCR_CI_CENA);
}
static u8 bm_rcr_cce_update(struct bm_portal *portal)
{
struct bm_rcr *rcr = &portal->rcr;
u8 diff, old_ci = rcr->ci;
DPAA_ASSERT(rcr->cmode == bm_rcr_cce);
rcr->ci = bm_ce_in(portal, BM_CL_RCR_CI_CENA) & (BM_RCR_SIZE - 1);
bm_cl_invalidate(portal, BM_CL_RCR_CI_CENA);
diff = dpaa_cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci);
rcr->available += diff;
return diff;
}
static inline struct bm_rcr_entry *bm_rcr_start(struct bm_portal *portal)
{
struct bm_rcr *rcr = &portal->rcr;
DPAA_ASSERT(!rcr->busy);
if (!rcr->available)
return NULL;
#ifdef CONFIG_FSL_DPAA_CHECKING
rcr->busy = 1;
#endif
dpaa_zero(rcr->cursor);
return rcr->cursor;
}
static inline void bm_rcr_pvb_commit(struct bm_portal *portal, u8 myverb)
{
struct bm_rcr *rcr = &portal->rcr;
struct bm_rcr_entry *rcursor;
DPAA_ASSERT(rcr->busy);
DPAA_ASSERT(rcr->pmode == bm_rcr_pvb);
DPAA_ASSERT(rcr->available >= 1);
dma_wmb();
rcursor = rcr->cursor;
rcursor->_ncw_verb = myverb | rcr->vbit;
dpaa_flush(rcursor);
rcr_inc(rcr);
rcr->available--;
#ifdef CONFIG_FSL_DPAA_CHECKING
rcr->busy = 0;
#endif
}
static int bm_rcr_init(struct bm_portal *portal, enum bm_rcr_pmode pmode,
enum bm_rcr_cmode cmode)
{
struct bm_rcr *rcr = &portal->rcr;
u32 cfg;
u8 pi;
rcr->ring = portal->addr.ce + BM_CL_RCR;
rcr->ci = bm_in(portal, BM_REG_RCR_CI_CINH) & (BM_RCR_SIZE - 1);
pi = bm_in(portal, BM_REG_RCR_PI_CINH) & (BM_RCR_SIZE - 1);
rcr->cursor = rcr->ring + pi;
rcr->vbit = (bm_in(portal, BM_REG_RCR_PI_CINH) & BM_RCR_SIZE) ?
BM_RCR_VERB_VBIT : 0;
rcr->available = BM_RCR_SIZE - 1
- dpaa_cyc_diff(BM_RCR_SIZE, rcr->ci, pi);
rcr->ithresh = bm_in(portal, BM_REG_RCR_ITR);
#ifdef CONFIG_FSL_DPAA_CHECKING
rcr->busy = 0;
rcr->pmode = pmode;
rcr->cmode = cmode;
#endif
cfg = (bm_in(portal, BM_REG_CFG) & 0xffffffe0)
| (pmode & 0x3); /* BCSP_CFG::RPM */
bm_out(portal, BM_REG_CFG, cfg);
return 0;
}
static void bm_rcr_finish(struct bm_portal *portal)
{
#ifdef CONFIG_FSL_DPAA_CHECKING
struct bm_rcr *rcr = &portal->rcr;
int i;
DPAA_ASSERT(!rcr->busy);
i = bm_in(portal, BM_REG_RCR_PI_CINH) & (BM_RCR_SIZE - 1);
if (i != rcr_ptr2idx(rcr->cursor))
pr_crit("losing uncommited RCR entries\n");
i = bm_in(portal, BM_REG_RCR_CI_CINH) & (BM_RCR_SIZE - 1);
if (i != rcr->ci)
pr_crit("missing existing RCR completions\n");
if (rcr->ci != rcr_ptr2idx(rcr->cursor))
pr_crit("RCR destroyed unquiesced\n");
#endif
}
/* --- Management command API --- */
static int bm_mc_init(struct bm_portal *portal)
{
struct bm_mc *mc = &portal->mc;
mc->cr = portal->addr.ce + BM_CL_CR;
mc->rr = portal->addr.ce + BM_CL_RR0;
mc->rridx = (__raw_readb(&mc->cr->_ncw_verb) & BM_MCC_VERB_VBIT) ?
0 : 1;
mc->vbit = mc->rridx ? BM_MCC_VERB_VBIT : 0;
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = mc_idle;
#endif
return 0;
}
static void bm_mc_finish(struct bm_portal *portal)
{
#ifdef CONFIG_FSL_DPAA_CHECKING
struct bm_mc *mc = &portal->mc;
DPAA_ASSERT(mc->state == mc_idle);
if (mc->state != mc_idle)
pr_crit("Losing incomplete MC command\n");
#endif
}
static inline struct bm_mc_command *bm_mc_start(struct bm_portal *portal)
{
struct bm_mc *mc = &portal->mc;
DPAA_ASSERT(mc->state == mc_idle);
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = mc_user;
#endif
dpaa_zero(mc->cr);
return mc->cr;
}
static inline void bm_mc_commit(struct bm_portal *portal, u8 myverb)
{
struct bm_mc *mc = &portal->mc;
union bm_mc_result *rr = mc->rr + mc->rridx;
DPAA_ASSERT(mc->state == mc_user);
dma_wmb();
mc->cr->_ncw_verb = myverb | mc->vbit;
dpaa_flush(mc->cr);
dpaa_invalidate_touch_ro(rr);
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = mc_hw;
#endif
}
static inline union bm_mc_result *bm_mc_result(struct bm_portal *portal)
{
struct bm_mc *mc = &portal->mc;
union bm_mc_result *rr = mc->rr + mc->rridx;
DPAA_ASSERT(mc->state == mc_hw);
/*
* The inactive response register's verb byte always returns zero until
* its command is submitted and completed. This includes the valid-bit,
* in case you were wondering...
*/
if (!__raw_readb(&rr->verb)) {
dpaa_invalidate_touch_ro(rr);
return NULL;
}
mc->rridx ^= 1;
mc->vbit ^= BM_MCC_VERB_VBIT;
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = mc_idle;
#endif
return rr;
}
static inline int bm_mc_result_timeout(struct bm_portal *portal,
union bm_mc_result **mcr)
{
int timeout = BM_MCR_TIMEOUT;
do {
*mcr = bm_mc_result(portal);
if (*mcr)
break;
udelay(1);
} while (--timeout);
return timeout;
}
/* Disable all BSCN interrupts for the portal */
static void bm_isr_bscn_disable(struct bm_portal *portal)
{
bm_out(portal, BM_REG_SCN(0), 0);
bm_out(portal, BM_REG_SCN(1), 0);
}
static int bman_create_portal(struct bman_portal *portal,
const struct bm_portal_config *c)
{
struct bm_portal *p;
int ret;
p = &portal->p;
/*
* prep the low-level portal struct with the mapped addresses from the
* config, everything that follows depends on it and "config" is more
* for (de)reference...
*/
p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
if (bm_rcr_init(p, bm_rcr_pvb, bm_rcr_cce)) {
dev_err(c->dev, "RCR initialisation failed\n");
goto fail_rcr;
}
if (bm_mc_init(p)) {
dev_err(c->dev, "MC initialisation failed\n");
goto fail_mc;
}
/*
* Default to all BPIDs disabled, we enable as required at
* run-time.
*/
bm_isr_bscn_disable(p);
/* Write-to-clear any stale interrupt status bits */
bm_out(p, BM_REG_ISDR, 0xffffffff);
portal->irq_sources = 0;
bm_out(p, BM_REG_IER, 0);
bm_out(p, BM_REG_ISR, 0xffffffff);
snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
dev_err(c->dev, "request_irq() failed\n");
goto fail_irq;
}
if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
dev_err(c->dev, "irq_set_affinity() failed\n");
goto fail_affinity;
}
/* Need RCR to be empty before continuing */
ret = bm_rcr_get_fill(p);
if (ret) {
dev_err(c->dev, "RCR unclean\n");
goto fail_rcr_empty;
}
/* Success */
portal->config = c;
bm_out(p, BM_REG_ISDR, 0);
bm_out(p, BM_REG_IIR, 0);
return 0;
fail_rcr_empty:
fail_affinity:
free_irq(c->irq, portal);
fail_irq:
bm_mc_finish(p);
fail_mc:
bm_rcr_finish(p);
fail_rcr:
return -EIO;
}
struct bman_portal *bman_create_affine_portal(const struct bm_portal_config *c)
{
struct bman_portal *portal;
int err;
portal = &per_cpu(bman_affine_portal, c->cpu);
err = bman_create_portal(portal, c);
if (err)
return NULL;
spin_lock(&affine_mask_lock);
cpumask_set_cpu(c->cpu, &affine_mask);
spin_unlock(&affine_mask_lock);
return portal;
}
static u32 poll_portal_slow(struct bman_portal *p, u32 is)
{
u32 ret = is;
if (is & BM_PIRQ_RCRI) {
bm_rcr_cce_update(&p->p);
bm_rcr_set_ithresh(&p->p, 0);
bm_out(&p->p, BM_REG_ISR, BM_PIRQ_RCRI);
is &= ~BM_PIRQ_RCRI;
}
/* There should be no status register bits left undefined */
DPAA_ASSERT(!is);
return ret;
}
int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
{
unsigned long irqflags;
local_irq_save(irqflags);
set_bits(bits & BM_PIRQ_VISIBLE, &p->irq_sources);
bm_out(&p->p, BM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
return 0;
}
static int bm_shutdown_pool(u32 bpid)
{
struct bm_mc_command *bm_cmd;
union bm_mc_result *bm_res;
while (1) {
struct bman_portal *p = get_affine_portal();
/* Acquire buffers until empty */
bm_cmd = bm_mc_start(&p->p);
bm_cmd->bpid = bpid;
bm_mc_commit(&p->p, BM_MCC_VERB_CMD_ACQUIRE | 1);
if (!bm_mc_result_timeout(&p->p, &bm_res)) {
put_affine_portal();
pr_crit("BMan Acquire Command timedout\n");
return -ETIMEDOUT;
}
if (!(bm_res->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT)) {
put_affine_portal();
/* Pool is empty */
return 0;
}
put_affine_portal();
}
return 0;
}
struct gen_pool *bm_bpalloc;
static int bm_alloc_bpid_range(u32 *result, u32 count)
{
unsigned long addr;
addr = gen_pool_alloc(bm_bpalloc, count);
if (!addr)
return -ENOMEM;
*result = addr & ~DPAA_GENALLOC_OFF;
return 0;
}
static int bm_release_bpid(u32 bpid)
{
int ret;
ret = bm_shutdown_pool(bpid);
if (ret) {
pr_debug("BPID %d leaked\n", bpid);
return ret;
}
gen_pool_free(bm_bpalloc, bpid | DPAA_GENALLOC_OFF, 1);
return 0;
}
struct bman_pool *bman_new_pool(void)
{
struct bman_pool *pool = NULL;
u32 bpid;
if (bm_alloc_bpid_range(&bpid, 1))
return NULL;
pool = kmalloc(sizeof(*pool), GFP_KERNEL);
if (!pool)
goto err;
pool->bpid = bpid;
return pool;
err:
bm_release_bpid(bpid);
kfree(pool);
return NULL;
}
EXPORT_SYMBOL(bman_new_pool);
void bman_free_pool(struct bman_pool *pool)
{
bm_release_bpid(pool->bpid);
kfree(pool);
}
EXPORT_SYMBOL(bman_free_pool);
int bman_get_bpid(const struct bman_pool *pool)
{
return pool->bpid;
}
EXPORT_SYMBOL(bman_get_bpid);
static void update_rcr_ci(struct bman_portal *p, int avail)
{
if (avail)
bm_rcr_cce_prefetch(&p->p);
else
bm_rcr_cce_update(&p->p);
}
int bman_release(struct bman_pool *pool, const struct bm_buffer *bufs, u8 num)
{
struct bman_portal *p;
struct bm_rcr_entry *r;
unsigned long irqflags;
int avail, timeout = 1000; /* 1ms */
int i = num - 1;
DPAA_ASSERT(num > 0 && num <= 8);
do {
p = get_affine_portal();
local_irq_save(irqflags);
avail = bm_rcr_get_avail(&p->p);
if (avail < 2)
update_rcr_ci(p, avail);
r = bm_rcr_start(&p->p);
local_irq_restore(irqflags);
put_affine_portal();
if (likely(r))
break;
udelay(1);
} while (--timeout);
if (unlikely(!timeout))
return -ETIMEDOUT;
p = get_affine_portal();
local_irq_save(irqflags);
/*
* we can copy all but the first entry, as this can trigger badness
* with the valid-bit
*/
bm_buffer_set64(r->bufs, bm_buffer_get64(bufs));
bm_buffer_set_bpid(r->bufs, pool->bpid);
if (i)
memcpy(&r->bufs[1], &bufs[1], i * sizeof(bufs[0]));
bm_rcr_pvb_commit(&p->p, BM_RCR_VERB_CMD_BPID_SINGLE |
(num & BM_RCR_VERB_BUFCOUNT_MASK));
local_irq_restore(irqflags);
put_affine_portal();
return 0;
}
EXPORT_SYMBOL(bman_release);
int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num)
{
struct bman_portal *p = get_affine_portal();
struct bm_mc_command *mcc;
union bm_mc_result *mcr;
int ret;
DPAA_ASSERT(num > 0 && num <= 8);
mcc = bm_mc_start(&p->p);
mcc->bpid = pool->bpid;
bm_mc_commit(&p->p, BM_MCC_VERB_CMD_ACQUIRE |
(num & BM_MCC_VERB_ACQUIRE_BUFCOUNT));
if (!bm_mc_result_timeout(&p->p, &mcr)) {
put_affine_portal();
pr_crit("BMan Acquire Timeout\n");
return -ETIMEDOUT;
}
ret = mcr->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT;
if (bufs)
memcpy(&bufs[0], &mcr->bufs[0], num * sizeof(bufs[0]));
put_affine_portal();
if (ret != num)
ret = -ENOMEM;
return ret;
}
EXPORT_SYMBOL(bman_acquire);
const struct bm_portal_config *
bman_get_bm_portal_config(const struct bman_portal *portal)
{
return portal->config;
}

263
drivers/soc/fsl/qbman/bman_ccsr.c Normal file
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@ -0,0 +1,263 @@
/* Copyright (c) 2009 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bman_priv.h"
u16 bman_ip_rev;
EXPORT_SYMBOL(bman_ip_rev);
/* Register offsets */
#define REG_FBPR_FPC 0x0800
#define REG_ECSR 0x0a00
#define REG_ECIR 0x0a04
#define REG_EADR 0x0a08
#define REG_EDATA(n) (0x0a10 + ((n) * 0x04))
#define REG_SBEC(n) (0x0a80 + ((n) * 0x04))
#define REG_IP_REV_1 0x0bf8
#define REG_IP_REV_2 0x0bfc
#define REG_FBPR_BARE 0x0c00
#define REG_FBPR_BAR 0x0c04
#define REG_FBPR_AR 0x0c10
#define REG_SRCIDR 0x0d04
#define REG_LIODNR 0x0d08
#define REG_ERR_ISR 0x0e00
#define REG_ERR_IER 0x0e04
#define REG_ERR_ISDR 0x0e08
/* Used by all error interrupt registers except 'inhibit' */
#define BM_EIRQ_IVCI 0x00000010 /* Invalid Command Verb */
#define BM_EIRQ_FLWI 0x00000008 /* FBPR Low Watermark */
#define BM_EIRQ_MBEI 0x00000004 /* Multi-bit ECC Error */
#define BM_EIRQ_SBEI 0x00000002 /* Single-bit ECC Error */
#define BM_EIRQ_BSCN 0x00000001 /* pool State Change Notification */
struct bman_hwerr_txt {
u32 mask;
const char *txt;
};
static const struct bman_hwerr_txt bman_hwerr_txts[] = {
{ BM_EIRQ_IVCI, "Invalid Command Verb" },
{ BM_EIRQ_FLWI, "FBPR Low Watermark" },
{ BM_EIRQ_MBEI, "Multi-bit ECC Error" },
{ BM_EIRQ_SBEI, "Single-bit ECC Error" },
{ BM_EIRQ_BSCN, "Pool State Change Notification" },
};
/* Only trigger low water mark interrupt once only */
#define BMAN_ERRS_TO_DISABLE BM_EIRQ_FLWI
/* Pointer to the start of the BMan's CCSR space */
static u32 __iomem *bm_ccsr_start;
static inline u32 bm_ccsr_in(u32 offset)
{
return ioread32be(bm_ccsr_start + offset/4);
}
static inline void bm_ccsr_out(u32 offset, u32 val)
{
iowrite32be(val, bm_ccsr_start + offset/4);
}
static void bm_get_version(u16 *id, u8 *major, u8 *minor)
{
u32 v = bm_ccsr_in(REG_IP_REV_1);
*id = (v >> 16);
*major = (v >> 8) & 0xff;
*minor = v & 0xff;
}
/* signal transactions for FBPRs with higher priority */
#define FBPR_AR_RPRIO_HI BIT(30)
static void bm_set_memory(u64 ba, u32 size)
{
u32 exp = ilog2(size);
/* choke if size isn't within range */
DPAA_ASSERT(size >= 4096 && size <= 1024*1024*1024 &&
is_power_of_2(size));
/* choke if '[e]ba' has lower-alignment than 'size' */
DPAA_ASSERT(!(ba & (size - 1)));
bm_ccsr_out(REG_FBPR_BARE, upper_32_bits(ba));
bm_ccsr_out(REG_FBPR_BAR, lower_32_bits(ba));
bm_ccsr_out(REG_FBPR_AR, exp - 1);
}
/*
* Location and size of BMan private memory
*
* Ideally we would use the DMA API to turn rmem->base into a DMA address
* (especially if iommu translations ever get involved). Unfortunately, the
* DMA API currently does not allow mapping anything that is not backed with
* a struct page.
*/
static dma_addr_t fbpr_a;
static size_t fbpr_sz;
static int bman_fbpr(struct reserved_mem *rmem)
{
fbpr_a = rmem->base;
fbpr_sz = rmem->size;
WARN_ON(!(fbpr_a && fbpr_sz));
return 0;
}
RESERVEDMEM_OF_DECLARE(bman_fbpr, "fsl,bman-fbpr", bman_fbpr);
static irqreturn_t bman_isr(int irq, void *ptr)
{
u32 isr_val, ier_val, ecsr_val, isr_mask, i;
struct device *dev = ptr;
ier_val = bm_ccsr_in(REG_ERR_IER);
isr_val = bm_ccsr_in(REG_ERR_ISR);
ecsr_val = bm_ccsr_in(REG_ECSR);
isr_mask = isr_val & ier_val;
if (!isr_mask)
return IRQ_NONE;
for (i = 0; i < ARRAY_SIZE(bman_hwerr_txts); i++) {
if (bman_hwerr_txts[i].mask & isr_mask) {
dev_err_ratelimited(dev, "ErrInt: %s\n",
bman_hwerr_txts[i].txt);
if (bman_hwerr_txts[i].mask & ecsr_val) {
/* Re-arm error capture registers */
bm_ccsr_out(REG_ECSR, ecsr_val);
}
if (bman_hwerr_txts[i].mask & BMAN_ERRS_TO_DISABLE) {
dev_dbg(dev, "Disabling error 0x%x\n",
bman_hwerr_txts[i].mask);
ier_val &= ~bman_hwerr_txts[i].mask;
bm_ccsr_out(REG_ERR_IER, ier_val);
}
}
}
bm_ccsr_out(REG_ERR_ISR, isr_val);
return IRQ_HANDLED;
}
static int fsl_bman_probe(struct platform_device *pdev)
{
int ret, err_irq;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct resource *res;
u16 id, bm_pool_cnt;
u8 major, minor;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "Can't get %s property 'IORESOURCE_MEM'\n",
node->full_name);
return -ENXIO;
}
bm_ccsr_start = devm_ioremap(dev, res->start,
res->end - res->start + 1);
if (!bm_ccsr_start)
return -ENXIO;
bm_get_version(&id, &major, &minor);
if (major == 1 && minor == 0) {
bman_ip_rev = BMAN_REV10;
bm_pool_cnt = BM_POOL_MAX;
} else if (major == 2 && minor == 0) {
bman_ip_rev = BMAN_REV20;
bm_pool_cnt = 8;
} else if (major == 2 && minor == 1) {
bman_ip_rev = BMAN_REV21;
bm_pool_cnt = BM_POOL_MAX;
} else {
dev_err(dev, "Unknown Bman version:%04x,%02x,%02x\n",
id, major, minor);
return -ENODEV;
}
bm_set_memory(fbpr_a, fbpr_sz);
err_irq = platform_get_irq(pdev, 0);
if (err_irq <= 0) {
dev_info(dev, "Can't get %s IRQ\n", node->full_name);
return -ENODEV;
}
ret = devm_request_irq(dev, err_irq, bman_isr, IRQF_SHARED, "bman-err",
dev);
if (ret) {
dev_err(dev, "devm_request_irq() failed %d for '%s'\n",
ret, node->full_name);
return ret;
}
/* Disable Buffer Pool State Change */
bm_ccsr_out(REG_ERR_ISDR, BM_EIRQ_BSCN);
/*
* Write-to-clear any stale bits, (eg. starvation being asserted prior
* to resource allocation during driver init).
*/
bm_ccsr_out(REG_ERR_ISR, 0xffffffff);
/* Enable Error Interrupts */
bm_ccsr_out(REG_ERR_IER, 0xffffffff);
bm_bpalloc = devm_gen_pool_create(dev, 0, -1, "bman-bpalloc");
if (IS_ERR(bm_bpalloc)) {
ret = PTR_ERR(bm_bpalloc);
dev_err(dev, "bman-bpalloc pool init failed (%d)\n", ret);
return ret;
}
/* seed BMan resource pool */
ret = gen_pool_add(bm_bpalloc, DPAA_GENALLOC_OFF, bm_pool_cnt, -1);
if (ret) {
dev_err(dev, "Failed to seed BPID range [%d..%d] (%d)\n",
0, bm_pool_cnt - 1, ret);
return ret;
}
return 0;
};
static const struct of_device_id fsl_bman_ids[] = {
{
.compatible = "fsl,bman",
},
{}
};
static struct platform_driver fsl_bman_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = fsl_bman_ids,
.suppress_bind_attrs = true,
},
.probe = fsl_bman_probe,
};
builtin_platform_driver(fsl_bman_driver);

219
drivers/soc/fsl/qbman/bman_portal.c Normal file
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/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bman_priv.h"
static struct bman_portal *affine_bportals[NR_CPUS];
static struct cpumask portal_cpus;
/* protect bman global registers and global data shared among portals */
static DEFINE_SPINLOCK(bman_lock);
static struct bman_portal *init_pcfg(struct bm_portal_config *pcfg)
{
struct bman_portal *p = bman_create_affine_portal(pcfg);
if (!p) {
dev_crit(pcfg->dev, "%s: Portal failure on cpu %d\n",
__func__, pcfg->cpu);
return NULL;
}
bman_p_irqsource_add(p, BM_PIRQ_RCRI);
affine_bportals[pcfg->cpu] = p;
dev_info(pcfg->dev, "Portal initialised, cpu %d\n", pcfg->cpu);
return p;
}
static void bman_offline_cpu(unsigned int cpu)
{
struct bman_portal *p = affine_bportals[cpu];
const struct bm_portal_config *pcfg;
if (!p)
return;
pcfg = bman_get_bm_portal_config(p);
if (!pcfg)
return;
irq_set_affinity(pcfg->irq, cpumask_of(0));
}
static void bman_online_cpu(unsigned int cpu)
{
struct bman_portal *p = affine_bportals[cpu];
const struct bm_portal_config *pcfg;
if (!p)
return;
pcfg = bman_get_bm_portal_config(p);
if (!pcfg)
return;
irq_set_affinity(pcfg->irq, cpumask_of(cpu));
}
static int bman_hotplug_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned long)hcpu;
switch (action) {
case CPU_ONLINE:
case CPU_ONLINE_FROZEN:
bman_online_cpu(cpu);
break;
case CPU_DOWN_PREPARE:
case CPU_DOWN_PREPARE_FROZEN:
bman_offline_cpu(cpu);
}
return NOTIFY_OK;
}
static struct notifier_block bman_hotplug_cpu_notifier = {
.notifier_call = bman_hotplug_cpu_callback,
};
static int bman_portal_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct bm_portal_config *pcfg;
struct resource *addr_phys[2];
void __iomem *va;
int irq, cpu;
pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
if (!pcfg)
return -ENOMEM;
pcfg->dev = dev;
addr_phys[0] = platform_get_resource(pdev, IORESOURCE_MEM,
DPAA_PORTAL_CE);
if (!addr_phys[0]) {
dev_err(dev, "Can't get %s property 'reg::CE'\n",
node->full_name);
return -ENXIO;
}
addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM,
DPAA_PORTAL_CI);
if (!addr_phys[1]) {
dev_err(dev, "Can't get %s property 'reg::CI'\n",
node->full_name);
return -ENXIO;
}
pcfg->cpu = -1;
irq = platform_get_irq(pdev, 0);
if (irq <= 0) {
dev_err(dev, "Can't get %s IRQ'\n", node->full_name);
return -ENXIO;
}
pcfg->irq = irq;
va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
if (!va)
goto err_ioremap1;
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
_PAGE_GUARDED | _PAGE_NO_CACHE);
if (!va)
goto err_ioremap2;
pcfg->addr_virt[DPAA_PORTAL_CI] = va;
spin_lock(&bman_lock);
cpu = cpumask_next_zero(-1, &portal_cpus);
if (cpu >= nr_cpu_ids) {
/* unassigned portal, skip init */
spin_unlock(&bman_lock);
return 0;
}
cpumask_set_cpu(cpu, &portal_cpus);
spin_unlock(&bman_lock);
pcfg->cpu = cpu;
if (!init_pcfg(pcfg))
goto err_ioremap2;
/* clear irq affinity if assigned cpu is offline */
if (!cpu_online(cpu))
bman_offline_cpu(cpu);
return 0;
err_ioremap2:
iounmap(pcfg->addr_virt[DPAA_PORTAL_CE]);
err_ioremap1:
dev_err(dev, "ioremap failed\n");
return -ENXIO;
}
static const struct of_device_id bman_portal_ids[] = {
{
.compatible = "fsl,bman-portal",
},
{}
};
MODULE_DEVICE_TABLE(of, bman_portal_ids);
static struct platform_driver bman_portal_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = bman_portal_ids,
},
.probe = bman_portal_probe,
};
static int __init bman_portal_driver_register(struct platform_driver *drv)
{
int ret;
ret = platform_driver_register(drv);
if (ret < 0)
return ret;
register_hotcpu_notifier(&bman_hotplug_cpu_notifier);
return 0;
}
module_driver(bman_portal_driver,
bman_portal_driver_register, platform_driver_unregister);

80
drivers/soc/fsl/qbman/bman_priv.h Normal file
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/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include "dpaa_sys.h"
#include <soc/fsl/bman.h>
/* Portal processing (interrupt) sources */
#define BM_PIRQ_RCRI 0x00000002 /* RCR Ring (below threshold) */
/* Revision info (for errata and feature handling) */
#define BMAN_REV10 0x0100
#define BMAN_REV20 0x0200
#define BMAN_REV21 0x0201
extern u16 bman_ip_rev; /* 0 if uninitialised, otherwise BMAN_REVx */
extern struct gen_pool *bm_bpalloc;
struct bm_portal_config {
/*
* Corenet portal addresses;
* [0]==cache-enabled, [1]==cache-inhibited.
*/
void __iomem *addr_virt[2];
/* Allow these to be joined in lists */
struct list_head list;
struct device *dev;
/* User-visible portal configuration settings */
/* portal is affined to this cpu */
int cpu;
/* portal interrupt line */
int irq;
};
struct bman_portal *bman_create_affine_portal(
const struct bm_portal_config *config);
/*
* The below bman_p_***() variant might be called in a situation that the cpu
* which the portal affine to is not online yet.
* @bman_portal specifies which portal the API will use.
*/
int bman_p_irqsource_add(struct bman_portal *p, u32 bits);
/*
* Used by all portal interrupt registers except 'inhibit'
* This mask contains all the "irqsource" bits visible to API users
*/
#define BM_PIRQ_VISIBLE BM_PIRQ_RCRI
const struct bm_portal_config *
bman_get_bm_portal_config(const struct bman_portal *portal);

53
drivers/soc/fsl/qbman/bman_test.c Normal file
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@ -0,0 +1,53 @@
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bman_test.h"
MODULE_AUTHOR("Geoff Thorpe");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("BMan testing");
static int test_init(void)
{
#ifdef CONFIG_FSL_BMAN_TEST_API
int loop = 1;
while (loop--)
bman_test_api();
#endif
return 0;
}
static void test_exit(void)
{
}
module_init(test_init);
module_exit(test_exit);

35
drivers/soc/fsl/qbman/bman_test.h Normal file
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@ -0,0 +1,35 @@
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bman_priv.h"
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
void bman_test_api(void);

151
drivers/soc/fsl/qbman/bman_test_api.c Normal file
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@ -0,0 +1,151 @@
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "bman_test.h"
#define NUM_BUFS 93
#define LOOPS 3
#define BMAN_TOKEN_MASK 0x00FFFFFFFFFFLLU
static struct bman_pool *pool;
static struct bm_buffer bufs_in[NUM_BUFS] ____cacheline_aligned;
static struct bm_buffer bufs_out[NUM_BUFS] ____cacheline_aligned;
static int bufs_received;
static void bufs_init(void)
{
int i;
for (i = 0; i < NUM_BUFS; i++)
bm_buffer_set64(&bufs_in[i], 0xfedc01234567LLU * i);
bufs_received = 0;
}
static inline int bufs_cmp(const struct bm_buffer *a, const struct bm_buffer *b)
{
if (bman_ip_rev == BMAN_REV20 || bman_ip_rev == BMAN_REV21) {
/*
* On SoCs with BMan revison 2.0, BMan only respects the 40
* LS-bits of buffer addresses, masking off the upper 8-bits on
* release commands. The API provides for 48-bit addresses
* because some SoCs support all 48-bits. When generating
* garbage addresses for testing, we either need to zero the
* upper 8-bits when releasing to BMan (otherwise we'll be
* disappointed when the buffers we acquire back from BMan
* don't match), or we need to mask the upper 8-bits off when
* comparing. We do the latter.
*/
if ((bm_buffer_get64(a) & BMAN_TOKEN_MASK) <
(bm_buffer_get64(b) & BMAN_TOKEN_MASK))
return -1;
if ((bm_buffer_get64(a) & BMAN_TOKEN_MASK) >
(bm_buffer_get64(b) & BMAN_TOKEN_MASK))
return 1;
} else {
if (bm_buffer_get64(a) < bm_buffer_get64(b))
return -1;
if (bm_buffer_get64(a) > bm_buffer_get64(b))
return 1;
}
return 0;
}
static void bufs_confirm(void)
{
int i, j;
for (i = 0; i < NUM_BUFS; i++) {
int matches = 0;
for (j = 0; j < NUM_BUFS; j++)
if (!bufs_cmp(&bufs_in[i], &bufs_out[j]))
matches++;
WARN_ON(matches != 1);
}
}
/* test */
void bman_test_api(void)
{
int i, loops = LOOPS;
bufs_init();
pr_info("%s(): Starting\n", __func__);
pool = bman_new_pool();
if (!pool) {
pr_crit("bman_new_pool() failed\n");
goto failed;
}
/* Release buffers */
do_loop:
i = 0;
while (i < NUM_BUFS) {
int num = 8;
if (i + num > NUM_BUFS)
num = NUM_BUFS - i;
if (bman_release(pool, bufs_in + i, num)) {
pr_crit("bman_release() failed\n");
goto failed;
}
i += num;
}
/* Acquire buffers */
while (i > 0) {
int tmp, num = 8;
if (num > i)
num = i;
tmp = bman_acquire(pool, bufs_out + i - num, num);
WARN_ON(tmp != num);
i -= num;
}
i = bman_acquire(pool, NULL, 1);
WARN_ON(i > 0);
bufs_confirm();
if (--loops)
goto do_loop;
/* Clean up */
bman_free_pool(pool);
pr_info("%s(): Finished\n", __func__);
return;
failed:
WARN_ON(1);
}

103
drivers/soc/fsl/qbman/dpaa_sys.h Normal file
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@ -0,0 +1,103 @@
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DPAA_SYS_H
#define __DPAA_SYS_H
#include <linux/cpu.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/kthread.h>
#include <linux/vmalloc.h>
#include <linux/platform_device.h>
#include <linux/of_reserved_mem.h>
#include <linux/prefetch.h>
#include <linux/genalloc.h>
#include <asm/cacheflush.h>
/* For 2-element tables related to cache-inhibited and cache-enabled mappings */
#define DPAA_PORTAL_CE 0
#define DPAA_PORTAL_CI 1
#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
#error "Unsupported Cacheline Size"
#endif
static inline void dpaa_flush(void *p)
{
#ifdef CONFIG_PPC
flush_dcache_range((unsigned long)p, (unsigned long)p+64);
#elif defined(CONFIG_ARM32)
__cpuc_flush_dcache_area(p, 64);
#elif defined(CONFIG_ARM64)
__flush_dcache_area(p, 64);
#endif
}
#define dpaa_invalidate(p) dpaa_flush(p)
#define dpaa_zero(p) memset(p, 0, 64)
static inline void dpaa_touch_ro(void *p)
{
#if (L1_CACHE_BYTES == 32)
prefetch(p+32);
#endif
prefetch(p);
}
/* Commonly used combo */
static inline void dpaa_invalidate_touch_ro(void *p)
{
dpaa_invalidate(p);
dpaa_touch_ro(p);
}
#ifdef CONFIG_FSL_DPAA_CHECKING
#define DPAA_ASSERT(x) WARN_ON(!(x))
#else
#define DPAA_ASSERT(x)
#endif
/* cyclic helper for rings */
static inline u8 dpaa_cyc_diff(u8 ringsize, u8 first, u8 last)
{
/* 'first' is included, 'last' is excluded */
if (first <= last)
return last - first;
return ringsize + last - first;
}
/* Offset applied to genalloc pools due to zero being an error return */
#define DPAA_GENALLOC_OFF 0x80000000
#endif /* __DPAA_SYS_H */

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/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qman_priv.h"
u16 qman_ip_rev;
EXPORT_SYMBOL(qman_ip_rev);
u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1;
EXPORT_SYMBOL(qm_channel_pool1);
/* Register offsets */
#define REG_QCSP_LIO_CFG(n) (0x0000 + ((n) * 0x10))
#define REG_QCSP_IO_CFG(n) (0x0004 + ((n) * 0x10))
#define REG_QCSP_DD_CFG(n) (0x000c + ((n) * 0x10))
#define REG_DD_CFG 0x0200
#define REG_DCP_CFG(n) (0x0300 + ((n) * 0x10))
#define REG_DCP_DD_CFG(n) (0x0304 + ((n) * 0x10))
#define REG_DCP_DLM_AVG(n) (0x030c + ((n) * 0x10))
#define REG_PFDR_FPC 0x0400
#define REG_PFDR_FP_HEAD 0x0404
#define REG_PFDR_FP_TAIL 0x0408
#define REG_PFDR_FP_LWIT 0x0410
#define REG_PFDR_CFG 0x0414
#define REG_SFDR_CFG 0x0500
#define REG_SFDR_IN_USE 0x0504
#define REG_WQ_CS_CFG(n) (0x0600 + ((n) * 0x04))
#define REG_WQ_DEF_ENC_WQID 0x0630
#define REG_WQ_SC_DD_CFG(n) (0x640 + ((n) * 0x04))
#define REG_WQ_PC_DD_CFG(n) (0x680 + ((n) * 0x04))
#define REG_WQ_DC0_DD_CFG(n) (0x6c0 + ((n) * 0x04))
#define REG_WQ_DC1_DD_CFG(n) (0x700 + ((n) * 0x04))
#define REG_WQ_DCn_DD_CFG(n) (0x6c0 + ((n) * 0x40)) /* n=2,3 */
#define REG_CM_CFG 0x0800
#define REG_ECSR 0x0a00
#define REG_ECIR 0x0a04
#define REG_EADR 0x0a08
#define REG_ECIR2 0x0a0c
#define REG_EDATA(n) (0x0a10 + ((n) * 0x04))
#define REG_SBEC(n) (0x0a80 + ((n) * 0x04))
#define REG_MCR 0x0b00
#define REG_MCP(n) (0x0b04 + ((n) * 0x04))
#define REG_MISC_CFG 0x0be0
#define REG_HID_CFG 0x0bf0
#define REG_IDLE_STAT 0x0bf4
#define REG_IP_REV_1 0x0bf8
#define REG_IP_REV_2 0x0bfc
#define REG_FQD_BARE 0x0c00
#define REG_PFDR_BARE 0x0c20
#define REG_offset_BAR 0x0004 /* relative to REG_[FQD|PFDR]_BARE */
#define REG_offset_AR 0x0010 /* relative to REG_[FQD|PFDR]_BARE */
#define REG_QCSP_BARE 0x0c80
#define REG_QCSP_BAR 0x0c84
#define REG_CI_SCHED_CFG 0x0d00
#define REG_SRCIDR 0x0d04
#define REG_LIODNR 0x0d08
#define REG_CI_RLM_AVG 0x0d14
#define REG_ERR_ISR 0x0e00
#define REG_ERR_IER 0x0e04
#define REG_REV3_QCSP_LIO_CFG(n) (0x1000 + ((n) * 0x10))
#define REG_REV3_QCSP_IO_CFG(n) (0x1004 + ((n) * 0x10))
#define REG_REV3_QCSP_DD_CFG(n) (0x100c + ((n) * 0x10))
/* Assists for QMAN_MCR */
#define MCR_INIT_PFDR 0x01000000
#define MCR_get_rslt(v) (u8)((v) >> 24)
#define MCR_rslt_idle(r) (!(r) || ((r) >= 0xf0))
#define MCR_rslt_ok(r) ((r) == 0xf0)
#define MCR_rslt_eaccess(r) ((r) == 0xf8)
#define MCR_rslt_inval(r) ((r) == 0xff)
/*
* Corenet initiator settings. Stash request queues are 4-deep to match cores
* ability to snarf. Stash priority is 3, other priorities are 2.
*/
#define QM_CI_SCHED_CFG_SRCCIV 4
#define QM_CI_SCHED_CFG_SRQ_W 3
#define QM_CI_SCHED_CFG_RW_W 2
#define QM_CI_SCHED_CFG_BMAN_W 2
/* write SRCCIV enable */
#define QM_CI_SCHED_CFG_SRCCIV_EN BIT(31)
/* Follows WQ_CS_CFG0-5 */
enum qm_wq_class {
qm_wq_portal = 0,
qm_wq_pool = 1,
qm_wq_fman0 = 2,
qm_wq_fman1 = 3,
qm_wq_caam = 4,
qm_wq_pme = 5,
qm_wq_first = qm_wq_portal,
qm_wq_last = qm_wq_pme
};
/* Follows FQD_[BARE|BAR|AR] and PFDR_[BARE|BAR|AR] */
enum qm_memory {
qm_memory_fqd,
qm_memory_pfdr
};
/* Used by all error interrupt registers except 'inhibit' */
#define QM_EIRQ_CIDE 0x20000000 /* Corenet Initiator Data Error */
#define QM_EIRQ_CTDE 0x10000000 /* Corenet Target Data Error */
#define QM_EIRQ_CITT 0x08000000 /* Corenet Invalid Target Transaction */
#define QM_EIRQ_PLWI 0x04000000 /* PFDR Low Watermark */
#define QM_EIRQ_MBEI 0x02000000 /* Multi-bit ECC Error */
#define QM_EIRQ_SBEI 0x01000000 /* Single-bit ECC Error */
#define QM_EIRQ_PEBI 0x00800000 /* PFDR Enqueues Blocked Interrupt */
#define QM_EIRQ_IFSI 0x00020000 /* Invalid FQ Flow Control State */
#define QM_EIRQ_ICVI 0x00010000 /* Invalid Command Verb */
#define QM_EIRQ_IDDI 0x00000800 /* Invalid Dequeue (Direct-connect) */
#define QM_EIRQ_IDFI 0x00000400 /* Invalid Dequeue FQ */
#define QM_EIRQ_IDSI 0x00000200 /* Invalid Dequeue Source */
#define QM_EIRQ_IDQI 0x00000100 /* Invalid Dequeue Queue */
#define QM_EIRQ_IECE 0x00000010 /* Invalid Enqueue Configuration */
#define QM_EIRQ_IEOI 0x00000008 /* Invalid Enqueue Overflow */
#define QM_EIRQ_IESI 0x00000004 /* Invalid Enqueue State */
#define QM_EIRQ_IECI 0x00000002 /* Invalid Enqueue Channel */
#define QM_EIRQ_IEQI 0x00000001 /* Invalid Enqueue Queue */
/* QMAN_ECIR valid error bit */
#define PORTAL_ECSR_ERR (QM_EIRQ_IEQI | QM_EIRQ_IESI | QM_EIRQ_IEOI | \
QM_EIRQ_IDQI | QM_EIRQ_IDSI | QM_EIRQ_IDFI | \
QM_EIRQ_IDDI | QM_EIRQ_ICVI | QM_EIRQ_IFSI)
#define FQID_ECSR_ERR (QM_EIRQ_IEQI | QM_EIRQ_IECI | QM_EIRQ_IESI | \
QM_EIRQ_IEOI | QM_EIRQ_IDQI | QM_EIRQ_IDFI | \
QM_EIRQ_IFSI)
struct qm_ecir {
u32 info; /* res[30-31], ptyp[29], pnum[24-28], fqid[0-23] */
};
static bool qm_ecir_is_dcp(const struct qm_ecir *p)
{
return p->info & BIT(29);
}
static int qm_ecir_get_pnum(const struct qm_ecir *p)
{
return (p->info >> 24) & 0x1f;
}
static int qm_ecir_get_fqid(const struct qm_ecir *p)
{
return p->info & (BIT(24) - 1);
}
struct qm_ecir2 {
u32 info; /* ptyp[31], res[10-30], pnum[0-9] */
};
static bool qm_ecir2_is_dcp(const struct qm_ecir2 *p)
{
return p->info & BIT(31);
}
static int qm_ecir2_get_pnum(const struct qm_ecir2 *p)
{
return p->info & (BIT(10) - 1);
}
struct qm_eadr {
u32 info; /* memid[24-27], eadr[0-11] */
/* v3: memid[24-28], eadr[0-15] */
};
static int qm_eadr_get_memid(const struct qm_eadr *p)
{
return (p->info >> 24) & 0xf;
}
static int qm_eadr_get_eadr(const struct qm_eadr *p)
{
return p->info & (BIT(12) - 1);
}
static int qm_eadr_v3_get_memid(const struct qm_eadr *p)
{
return (p->info >> 24) & 0x1f;
}
static int qm_eadr_v3_get_eadr(const struct qm_eadr *p)
{
return p->info & (BIT(16) - 1);
}
struct qman_hwerr_txt {
u32 mask;
const char *txt;
};
static const struct qman_hwerr_txt qman_hwerr_txts[] = {
{ QM_EIRQ_CIDE, "Corenet Initiator Data Error" },
{ QM_EIRQ_CTDE, "Corenet Target Data Error" },
{ QM_EIRQ_CITT, "Corenet Invalid Target Transaction" },
{ QM_EIRQ_PLWI, "PFDR Low Watermark" },
{ QM_EIRQ_MBEI, "Multi-bit ECC Error" },
{ QM_EIRQ_SBEI, "Single-bit ECC Error" },
{ QM_EIRQ_PEBI, "PFDR Enqueues Blocked Interrupt" },
{ QM_EIRQ_ICVI, "Invalid Command Verb" },
{ QM_EIRQ_IFSI, "Invalid Flow Control State" },
{ QM_EIRQ_IDDI, "Invalid Dequeue (Direct-connect)" },
{ QM_EIRQ_IDFI, "Invalid Dequeue FQ" },
{ QM_EIRQ_IDSI, "Invalid Dequeue Source" },
{ QM_EIRQ_IDQI, "Invalid Dequeue Queue" },
{ QM_EIRQ_IECE, "Invalid Enqueue Configuration" },
{ QM_EIRQ_IEOI, "Invalid Enqueue Overflow" },
{ QM_EIRQ_IESI, "Invalid Enqueue State" },
{ QM_EIRQ_IECI, "Invalid Enqueue Channel" },
{ QM_EIRQ_IEQI, "Invalid Enqueue Queue" },
};
struct qman_error_info_mdata {
u16 addr_mask;
u16 bits;
const char *txt;
};
static const struct qman_error_info_mdata error_mdata[] = {
{ 0x01FF, 24, "FQD cache tag memory 0" },
{ 0x01FF, 24, "FQD cache tag memory 1" },
{ 0x01FF, 24, "FQD cache tag memory 2" },
{ 0x01FF, 24, "FQD cache tag memory 3" },
{ 0x0FFF, 512, "FQD cache memory" },
{ 0x07FF, 128, "SFDR memory" },
{ 0x01FF, 72, "WQ context memory" },
{ 0x00FF, 240, "CGR memory" },
{ 0x00FF, 302, "Internal Order Restoration List memory" },
{ 0x01FF, 256, "SW portal ring memory" },
};
#define QMAN_ERRS_TO_DISABLE (QM_EIRQ_PLWI | QM_EIRQ_PEBI)
/*
* TODO: unimplemented registers
*
* Keeping a list here of QMan registers I have not yet covered;
* QCSP_DD_IHRSR, QCSP_DD_IHRFR, QCSP_DD_HASR,
* DCP_DD_IHRSR, DCP_DD_IHRFR, DCP_DD_HASR, CM_CFG,
* QMAN_EECC, QMAN_SBET, QMAN_EINJ, QMAN_SBEC0-12
*/
/* Pointer to the start of the QMan's CCSR space */
static u32 __iomem *qm_ccsr_start;
/* A SDQCR mask comprising all the available/visible pool channels */
static u32 qm_pools_sdqcr;
static inline u32 qm_ccsr_in(u32 offset)
{
return ioread32be(qm_ccsr_start + offset/4);
}
static inline void qm_ccsr_out(u32 offset, u32 val)
{
iowrite32be(val, qm_ccsr_start + offset/4);
}
u32 qm_get_pools_sdqcr(void)
{
return qm_pools_sdqcr;
}
enum qm_dc_portal {
qm_dc_portal_fman0 = 0,
qm_dc_portal_fman1 = 1
};
static void qm_set_dc(enum qm_dc_portal portal, int ed, u8 sernd)
{
DPAA_ASSERT(!ed || portal == qm_dc_portal_fman0 ||
portal == qm_dc_portal_fman1);
if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
qm_ccsr_out(REG_DCP_CFG(portal),
(ed ? 0x1000 : 0) | (sernd & 0x3ff));
else
qm_ccsr_out(REG_DCP_CFG(portal),
(ed ? 0x100 : 0) | (sernd & 0x1f));
}
static void qm_set_wq_scheduling(enum qm_wq_class wq_class,
u8 cs_elev, u8 csw2, u8 csw3, u8 csw4,
u8 csw5, u8 csw6, u8 csw7)
{
qm_ccsr_out(REG_WQ_CS_CFG(wq_class), ((cs_elev & 0xff) << 24) |
((csw2 & 0x7) << 20) | ((csw3 & 0x7) << 16) |
((csw4 & 0x7) << 12) | ((csw5 & 0x7) << 8) |
((csw6 & 0x7) << 4) | (csw7 & 0x7));
}
static void qm_set_hid(void)
{
qm_ccsr_out(REG_HID_CFG, 0);
}
static void qm_set_corenet_initiator(void)
{
qm_ccsr_out(REG_CI_SCHED_CFG, QM_CI_SCHED_CFG_SRCCIV_EN |
(QM_CI_SCHED_CFG_SRCCIV << 24) |
(QM_CI_SCHED_CFG_SRQ_W << 8) |
(QM_CI_SCHED_CFG_RW_W << 4) |
QM_CI_SCHED_CFG_BMAN_W);
}
static void qm_get_version(u16 *id, u8 *major, u8 *minor)
{
u32 v = qm_ccsr_in(REG_IP_REV_1);
*id = (v >> 16);
*major = (v >> 8) & 0xff;
*minor = v & 0xff;
}
#define PFDR_AR_EN BIT(31)
static void qm_set_memory(enum qm_memory memory, u64 ba, u32 size)
{
u32 offset = (memory == qm_memory_fqd) ? REG_FQD_BARE : REG_PFDR_BARE;
u32 exp = ilog2(size);
/* choke if size isn't within range */
DPAA_ASSERT((size >= 4096) && (size <= 1024*1024*1024) &&
is_power_of_2(size));
/* choke if 'ba' has lower-alignment than 'size' */
DPAA_ASSERT(!(ba & (size - 1)));
qm_ccsr_out(offset, upper_32_bits(ba));
qm_ccsr_out(offset + REG_offset_BAR, lower_32_bits(ba));
qm_ccsr_out(offset + REG_offset_AR, PFDR_AR_EN | (exp - 1));
}
static void qm_set_pfdr_threshold(u32 th, u8 k)
{
qm_ccsr_out(REG_PFDR_FP_LWIT, th & 0xffffff);
qm_ccsr_out(REG_PFDR_CFG, k);
}
static void qm_set_sfdr_threshold(u16 th)
{
qm_ccsr_out(REG_SFDR_CFG, th & 0x3ff);
}
static int qm_init_pfdr(struct device *dev, u32 pfdr_start, u32 num)
{
u8 rslt = MCR_get_rslt(qm_ccsr_in(REG_MCR));
DPAA_ASSERT(pfdr_start && !(pfdr_start & 7) && !(num & 7) && num);
/* Make sure the command interface is 'idle' */
if (!MCR_rslt_idle(rslt)) {
dev_crit(dev, "QMAN_MCR isn't idle");
WARN_ON(1);
}
/* Write the MCR command params then the verb */
qm_ccsr_out(REG_MCP(0), pfdr_start);
/*
* TODO: remove this - it's a workaround for a model bug that is
* corrected in more recent versions. We use the workaround until
* everyone has upgraded.
*/
qm_ccsr_out(REG_MCP(1), pfdr_start + num - 16);
dma_wmb();
qm_ccsr_out(REG_MCR, MCR_INIT_PFDR);
/* Poll for the result */
do {
rslt = MCR_get_rslt(qm_ccsr_in(REG_MCR));
} while (!MCR_rslt_idle(rslt));
if (MCR_rslt_ok(rslt))
return 0;
if (MCR_rslt_eaccess(rslt))
return -EACCES;
if (MCR_rslt_inval(rslt))
return -EINVAL;
dev_crit(dev, "Unexpected result from MCR_INIT_PFDR: %02x\n", rslt);
return -ENODEV;
}
/*
* Ideally we would use the DMA API to turn rmem->base into a DMA address
* (especially if iommu translations ever get involved). Unfortunately, the
* DMA API currently does not allow mapping anything that is not backed with
* a struct page.
*/
static dma_addr_t fqd_a, pfdr_a;
static size_t fqd_sz, pfdr_sz;
static int qman_fqd(struct reserved_mem *rmem)
{
fqd_a = rmem->base;
fqd_sz = rmem->size;
WARN_ON(!(fqd_a && fqd_sz));
return 0;
}
RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
static int qman_pfdr(struct reserved_mem *rmem)
{
pfdr_a = rmem->base;
pfdr_sz = rmem->size;
WARN_ON(!(pfdr_a && pfdr_sz));
return 0;
}
RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
static unsigned int qm_get_fqid_maxcnt(void)
{
return fqd_sz / 64;
}
/*
* Flush this memory range from data cache so that QMAN originated
* transactions for this memory region could be marked non-coherent.
*/
static int zero_priv_mem(struct device *dev, struct device_node *node,
phys_addr_t addr, size_t sz)
{
/* map as cacheable, non-guarded */
void __iomem *tmpp = ioremap_prot(addr, sz, 0);
memset_io(tmpp, 0, sz);
flush_dcache_range((unsigned long)tmpp,
(unsigned long)tmpp + sz);
iounmap(tmpp);
return 0;
}
static void log_edata_bits(struct device *dev, u32 bit_count)
{
u32 i, j, mask = 0xffffffff;
dev_warn(dev, "ErrInt, EDATA:\n");
i = bit_count / 32;
if (bit_count % 32) {
i++;
mask = ~(mask << bit_count % 32);
}
j = 16 - i;
dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j)) & mask);
j++;
for (; j < 16; j++)
dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j)));
}
static void log_additional_error_info(struct device *dev, u32 isr_val,
u32 ecsr_val)
{
struct qm_ecir ecir_val;
struct qm_eadr eadr_val;
int memid;
ecir_val.info = qm_ccsr_in(REG_ECIR);
/* Is portal info valid */
if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) {
struct qm_ecir2 ecir2_val;
ecir2_val.info = qm_ccsr_in(REG_ECIR2);
if (ecsr_val & PORTAL_ECSR_ERR) {
dev_warn(dev, "ErrInt: %s id %d\n",
qm_ecir2_is_dcp(&ecir2_val) ? "DCP" : "SWP",
qm_ecir2_get_pnum(&ecir2_val));
}
if (ecsr_val & (FQID_ECSR_ERR | QM_EIRQ_IECE))
dev_warn(dev, "ErrInt: ecir.fqid 0x%x\n",
qm_ecir_get_fqid(&ecir_val));
if (ecsr_val & (QM_EIRQ_SBEI|QM_EIRQ_MBEI)) {
eadr_val.info = qm_ccsr_in(REG_EADR);
memid = qm_eadr_v3_get_memid(&eadr_val);
dev_warn(dev, "ErrInt: EADR Memory: %s, 0x%x\n",
error_mdata[memid].txt,
error_mdata[memid].addr_mask
& qm_eadr_v3_get_eadr(&eadr_val));
log_edata_bits(dev, error_mdata[memid].bits);
}
} else {
if (ecsr_val & PORTAL_ECSR_ERR) {
dev_warn(dev, "ErrInt: %s id %d\n",
qm_ecir_is_dcp(&ecir_val) ? "DCP" : "SWP",
qm_ecir_get_pnum(&ecir_val));
}
if (ecsr_val & FQID_ECSR_ERR)
dev_warn(dev, "ErrInt: ecir.fqid 0x%x\n",
qm_ecir_get_fqid(&ecir_val));
if (ecsr_val & (QM_EIRQ_SBEI|QM_EIRQ_MBEI)) {
eadr_val.info = qm_ccsr_in(REG_EADR);
memid = qm_eadr_get_memid(&eadr_val);
dev_warn(dev, "ErrInt: EADR Memory: %s, 0x%x\n",
error_mdata[memid].txt,
error_mdata[memid].addr_mask
& qm_eadr_get_eadr(&eadr_val));
log_edata_bits(dev, error_mdata[memid].bits);
}
}
}
static irqreturn_t qman_isr(int irq, void *ptr)
{
u32 isr_val, ier_val, ecsr_val, isr_mask, i;
struct device *dev = ptr;
ier_val = qm_ccsr_in(REG_ERR_IER);
isr_val = qm_ccsr_in(REG_ERR_ISR);
ecsr_val = qm_ccsr_in(REG_ECSR);
isr_mask = isr_val & ier_val;
if (!isr_mask)
return IRQ_NONE;
for (i = 0; i < ARRAY_SIZE(qman_hwerr_txts); i++) {
if (qman_hwerr_txts[i].mask & isr_mask) {
dev_err_ratelimited(dev, "ErrInt: %s\n",
qman_hwerr_txts[i].txt);
if (qman_hwerr_txts[i].mask & ecsr_val) {
log_additional_error_info(dev, isr_mask,
ecsr_val);
/* Re-arm error capture registers */
qm_ccsr_out(REG_ECSR, ecsr_val);
}
if (qman_hwerr_txts[i].mask & QMAN_ERRS_TO_DISABLE) {
dev_dbg(dev, "Disabling error 0x%x\n",
qman_hwerr_txts[i].mask);
ier_val &= ~qman_hwerr_txts[i].mask;
qm_ccsr_out(REG_ERR_IER, ier_val);
}
}
}
qm_ccsr_out(REG_ERR_ISR, isr_val);
return IRQ_HANDLED;
}
static int qman_init_ccsr(struct device *dev)
{
int i, err;
/* FQD memory */
qm_set_memory(qm_memory_fqd, fqd_a, fqd_sz);
/* PFDR memory */
qm_set_memory(qm_memory_pfdr, pfdr_a, pfdr_sz);
err = qm_init_pfdr(dev, 8, pfdr_sz / 64 - 8);
if (err)
return err;
/* thresholds */
qm_set_pfdr_threshold(512, 64);
qm_set_sfdr_threshold(128);
/* clear stale PEBI bit from interrupt status register */
qm_ccsr_out(REG_ERR_ISR, QM_EIRQ_PEBI);
/* corenet initiator settings */
qm_set_corenet_initiator();
/* HID settings */
qm_set_hid();
/* Set scheduling weights to defaults */
for (i = qm_wq_first; i <= qm_wq_last; i++)
qm_set_wq_scheduling(i, 0, 0, 0, 0, 0, 0, 0);
/* We are not prepared to accept ERNs for hardware enqueues */
qm_set_dc(qm_dc_portal_fman0, 1, 0);
qm_set_dc(qm_dc_portal_fman1, 1, 0);
return 0;
}
#define LIO_CFG_LIODN_MASK 0x0fff0000
void qman_liodn_fixup(u16 channel)
{
static int done;
static u32 liodn_offset;
u32 before, after;
int idx = channel - QM_CHANNEL_SWPORTAL0;
if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
before = qm_ccsr_in(REG_REV3_QCSP_LIO_CFG(idx));
else
before = qm_ccsr_in(REG_QCSP_LIO_CFG(idx));
if (!done) {
liodn_offset = before & LIO_CFG_LIODN_MASK;
done = 1;
return;
}
after = (before & (~LIO_CFG_LIODN_MASK)) | liodn_offset;
if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
qm_ccsr_out(REG_REV3_QCSP_LIO_CFG(idx), after);
else
qm_ccsr_out(REG_QCSP_LIO_CFG(idx), after);
}
#define IO_CFG_SDEST_MASK 0x00ff0000
void qman_set_sdest(u16 channel, unsigned int cpu_idx)
{
int idx = channel - QM_CHANNEL_SWPORTAL0;
u32 before, after;
if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) {
before = qm_ccsr_in(REG_REV3_QCSP_IO_CFG(idx));
/* Each pair of vcpu share the same SRQ(SDEST) */
cpu_idx /= 2;
after = (before & (~IO_CFG_SDEST_MASK)) | (cpu_idx << 16);
qm_ccsr_out(REG_REV3_QCSP_IO_CFG(idx), after);
} else {
before = qm_ccsr_in(REG_QCSP_IO_CFG(idx));
after = (before & (~IO_CFG_SDEST_MASK)) | (cpu_idx << 16);
qm_ccsr_out(REG_QCSP_IO_CFG(idx), after);
}
}
static int qman_resource_init(struct device *dev)
{
int pool_chan_num, cgrid_num;
int ret, i;
switch (qman_ip_rev >> 8) {
case 1:
pool_chan_num = 15;
cgrid_num = 256;
break;
case 2:
pool_chan_num = 3;
cgrid_num = 64;
break;
case 3:
pool_chan_num = 15;
cgrid_num = 256;
break;
default:
return -ENODEV;
}
ret = gen_pool_add(qm_qpalloc, qm_channel_pool1 | DPAA_GENALLOC_OFF,
pool_chan_num, -1);
if (ret) {
dev_err(dev, "Failed to seed pool channels (%d)\n", ret);
return ret;
}
ret = gen_pool_add(qm_cgralloc, DPAA_GENALLOC_OFF, cgrid_num, -1);
if (ret) {
dev_err(dev, "Failed to seed CGRID range (%d)\n", ret);
return ret;
}
/* parse pool channels into the SDQCR mask */
for (i = 0; i < cgrid_num; i++)
qm_pools_sdqcr |= QM_SDQCR_CHANNELS_POOL_CONV(i);
ret = gen_pool_add(qm_fqalloc, QM_FQID_RANGE_START | DPAA_GENALLOC_OFF,
qm_get_fqid_maxcnt() - QM_FQID_RANGE_START, -1);
if (ret) {
dev_err(dev, "Failed to seed FQID range (%d)\n", ret);
return ret;
}
return 0;
}
static int fsl_qman_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct resource *res;
int ret, err_irq;
u16 id;
u8 major, minor;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "Can't get %s property 'IORESOURCE_MEM'\n",
node->full_name);
return -ENXIO;
}
qm_ccsr_start = devm_ioremap(dev, res->start, resource_size(res));
if (!qm_ccsr_start)
return -ENXIO;
qm_get_version(&id, &major, &minor);
if (major == 1 && minor == 0) {
dev_err(dev, "Rev1.0 on P4080 rev1 is not supported!\n");
return -ENODEV;
} else if (major == 1 && minor == 1)
qman_ip_rev = QMAN_REV11;
else if (major == 1 && minor == 2)
qman_ip_rev = QMAN_REV12;
else if (major == 2 && minor == 0)
qman_ip_rev = QMAN_REV20;
else if (major == 3 && minor == 0)
qman_ip_rev = QMAN_REV30;
else if (major == 3 && minor == 1)
qman_ip_rev = QMAN_REV31;
else {
dev_err(dev, "Unknown QMan version\n");
return -ENODEV;
}
if ((qman_ip_rev & 0xff00) >= QMAN_REV30)
qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3;
ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
WARN_ON(ret);
if (ret)
return -ENODEV;
ret = qman_init_ccsr(dev);
if (ret) {
dev_err(dev, "CCSR setup failed\n");
return ret;
}
err_irq = platform_get_irq(pdev, 0);
if (err_irq <= 0) {
dev_info(dev, "Can't get %s property 'interrupts'\n",
node->full_name);
return -ENODEV;
}
ret = devm_request_irq(dev, err_irq, qman_isr, IRQF_SHARED, "qman-err",
dev);
if (ret) {
dev_err(dev, "devm_request_irq() failed %d for '%s'\n",
ret, node->full_name);
return ret;
}
/*
* Write-to-clear any stale bits, (eg. starvation being asserted prior
* to resource allocation during driver init).
*/
qm_ccsr_out(REG_ERR_ISR, 0xffffffff);
/* Enable Error Interrupts */
qm_ccsr_out(REG_ERR_IER, 0xffffffff);
qm_fqalloc = devm_gen_pool_create(dev, 0, -1, "qman-fqalloc");
if (IS_ERR(qm_fqalloc)) {
ret = PTR_ERR(qm_fqalloc);
dev_err(dev, "qman-fqalloc pool init failed (%d)\n", ret);
return ret;
}
qm_qpalloc = devm_gen_pool_create(dev, 0, -1, "qman-qpalloc");
if (IS_ERR(qm_qpalloc)) {
ret = PTR_ERR(qm_qpalloc);
dev_err(dev, "qman-qpalloc pool init failed (%d)\n", ret);
return ret;
}
qm_cgralloc = devm_gen_pool_create(dev, 0, -1, "qman-cgralloc");
if (IS_ERR(qm_cgralloc)) {
ret = PTR_ERR(qm_cgralloc);
dev_err(dev, "qman-cgralloc pool init failed (%d)\n", ret);
return ret;
}
ret = qman_resource_init(dev);
if (ret)
return ret;
ret = qman_alloc_fq_table(qm_get_fqid_maxcnt());
if (ret)
return ret;
ret = qman_wq_alloc();
if (ret)
return ret;
return 0;
}
static const struct of_device_id fsl_qman_ids[] = {
{
.compatible = "fsl,qman",
},
{}
};
static struct platform_driver fsl_qman_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = fsl_qman_ids,
.suppress_bind_attrs = true,
},
.probe = fsl_qman_probe,
};
builtin_platform_driver(fsl_qman_driver);

355
drivers/soc/fsl/qbman/qman_portal.c Normal file
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@ -0,0 +1,355 @@
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qman_priv.h"
/* Enable portal interupts (as opposed to polling mode) */
#define CONFIG_FSL_DPA_PIRQ_SLOW 1
#define CONFIG_FSL_DPA_PIRQ_FAST 1
static struct cpumask portal_cpus;
/* protect qman global registers and global data shared among portals */
static DEFINE_SPINLOCK(qman_lock);
static void portal_set_cpu(struct qm_portal_config *pcfg, int cpu)
{
#ifdef CONFIG_FSL_PAMU
struct device *dev = pcfg->dev;
int window_count = 1;
struct iommu_domain_geometry geom_attr;
struct pamu_stash_attribute stash_attr;
int ret;
pcfg->iommu_domain = iommu_domain_alloc(&platform_bus_type);
if (!pcfg->iommu_domain) {
dev_err(dev, "%s(): iommu_domain_alloc() failed", __func__);
goto no_iommu;
}
geom_attr.aperture_start = 0;
geom_attr.aperture_end =
((dma_addr_t)1 << min(8 * sizeof(dma_addr_t), (size_t)36)) - 1;
geom_attr.force_aperture = true;
ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_GEOMETRY,
&geom_attr);
if (ret < 0) {
dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
ret);
goto out_domain_free;
}
ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_WINDOWS,
&window_count);
if (ret < 0) {
dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
ret);
goto out_domain_free;
}
stash_attr.cpu = cpu;
stash_attr.cache = PAMU_ATTR_CACHE_L1;
ret = iommu_domain_set_attr(pcfg->iommu_domain,
DOMAIN_ATTR_FSL_PAMU_STASH,
&stash_attr);
if (ret < 0) {
dev_err(dev, "%s(): iommu_domain_set_attr() = %d",
__func__, ret);
goto out_domain_free;
}
ret = iommu_domain_window_enable(pcfg->iommu_domain, 0, 0, 1ULL << 36,
IOMMU_READ | IOMMU_WRITE);
if (ret < 0) {
dev_err(dev, "%s(): iommu_domain_window_enable() = %d",
__func__, ret);
goto out_domain_free;
}
ret = iommu_attach_device(pcfg->iommu_domain, dev);
if (ret < 0) {
dev_err(dev, "%s(): iommu_device_attach() = %d", __func__,
ret);
goto out_domain_free;
}
ret = iommu_domain_set_attr(pcfg->iommu_domain,
DOMAIN_ATTR_FSL_PAMU_ENABLE,
&window_count);
if (ret < 0) {
dev_err(dev, "%s(): iommu_domain_set_attr() = %d", __func__,
ret);
goto out_detach_device;
}
no_iommu:
#endif
qman_set_sdest(pcfg->channel, cpu);
return;
#ifdef CONFIG_FSL_PAMU
out_detach_device:
iommu_detach_device(pcfg->iommu_domain, NULL);
out_domain_free:
iommu_domain_free(pcfg->iommu_domain);
pcfg->iommu_domain = NULL;
#endif
}
static struct qman_portal *init_pcfg(struct qm_portal_config *pcfg)
{
struct qman_portal *p;
u32 irq_sources = 0;
/* We need the same LIODN offset for all portals */
qman_liodn_fixup(pcfg->channel);
pcfg->iommu_domain = NULL;
portal_set_cpu(pcfg, pcfg->cpu);
p = qman_create_affine_portal(pcfg, NULL);
if (!p) {
dev_crit(pcfg->dev, "%s: Portal failure on cpu %d\n",
__func__, pcfg->cpu);
return NULL;
}
/* Determine what should be interrupt-vs-poll driven */
#ifdef CONFIG_FSL_DPA_PIRQ_SLOW
irq_sources |= QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI |
QM_PIRQ_CSCI;
#endif
#ifdef CONFIG_FSL_DPA_PIRQ_FAST
irq_sources |= QM_PIRQ_DQRI;
#endif
qman_p_irqsource_add(p, irq_sources);
spin_lock(&qman_lock);
if (cpumask_equal(&portal_cpus, cpu_possible_mask)) {
/* all assigned portals are initialized now */
qman_init_cgr_all();
}
spin_unlock(&qman_lock);
dev_info(pcfg->dev, "Portal initialised, cpu %d\n", pcfg->cpu);
return p;
}
static void qman_portal_update_sdest(const struct qm_portal_config *pcfg,
unsigned int cpu)
{
#ifdef CONFIG_FSL_PAMU /* TODO */
struct pamu_stash_attribute stash_attr;
int ret;
if (pcfg->iommu_domain) {
stash_attr.cpu = cpu;
stash_attr.cache = PAMU_ATTR_CACHE_L1;
ret = iommu_domain_set_attr(pcfg->iommu_domain,
DOMAIN_ATTR_FSL_PAMU_STASH, &stash_attr);
if (ret < 0) {
dev_err(pcfg->dev,
"Failed to update pamu stash setting\n");
return;
}
}
#endif
qman_set_sdest(pcfg->channel, cpu);
}
static void qman_offline_cpu(unsigned int cpu)
{
struct qman_portal *p;
const struct qm_portal_config *pcfg;
p = affine_portals[cpu];
if (p) {
pcfg = qman_get_qm_portal_config(p);
if (pcfg) {
irq_set_affinity(pcfg->irq, cpumask_of(0));
qman_portal_update_sdest(pcfg, 0);
}
}
}
static void qman_online_cpu(unsigned int cpu)
{
struct qman_portal *p;
const struct qm_portal_config *pcfg;
p = affine_portals[cpu];
if (p) {
pcfg = qman_get_qm_portal_config(p);
if (pcfg) {
irq_set_affinity(pcfg->irq, cpumask_of(cpu));
qman_portal_update_sdest(pcfg, cpu);
}
}
}
static int qman_hotplug_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned long)hcpu;
switch (action) {
case CPU_ONLINE:
case CPU_ONLINE_FROZEN:
qman_online_cpu(cpu);
break;
case CPU_DOWN_PREPARE:
case CPU_DOWN_PREPARE_FROZEN:
qman_offline_cpu(cpu);
default:
break;
}
return NOTIFY_OK;
}
static struct notifier_block qman_hotplug_cpu_notifier = {
.notifier_call = qman_hotplug_cpu_callback,
};
static int qman_portal_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct qm_portal_config *pcfg;
struct resource *addr_phys[2];
const u32 *channel;
void __iomem *va;
int irq, len, cpu;
pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
if (!pcfg)
return -ENOMEM;
pcfg->dev = dev;
addr_phys[0] = platform_get_resource(pdev, IORESOURCE_MEM,
DPAA_PORTAL_CE);
if (!addr_phys[0]) {
dev_err(dev, "Can't get %s property 'reg::CE'\n",
node->full_name);
return -ENXIO;
}
addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM,
DPAA_PORTAL_CI);
if (!addr_phys[1]) {
dev_err(dev, "Can't get %s property 'reg::CI'\n",
node->full_name);
return -ENXIO;
}
channel = of_get_property(node, "cell-index", &len);
if (!channel || (len != 4)) {
dev_err(dev, "Can't get %s property 'cell-index'\n",
node->full_name);
return -ENXIO;
}
pcfg->channel = *channel;
pcfg->cpu = -1;
irq = platform_get_irq(pdev, 0);
if (irq <= 0) {
dev_err(dev, "Can't get %s IRQ\n", node->full_name);
return -ENXIO;
}
pcfg->irq = irq;
va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
if (!va)
goto err_ioremap1;
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
_PAGE_GUARDED | _PAGE_NO_CACHE);
if (!va)
goto err_ioremap2;
pcfg->addr_virt[DPAA_PORTAL_CI] = va;
pcfg->pools = qm_get_pools_sdqcr();
spin_lock(&qman_lock);
cpu = cpumask_next_zero(-1, &portal_cpus);
if (cpu >= nr_cpu_ids) {
/* unassigned portal, skip init */
spin_unlock(&qman_lock);
return 0;
}
cpumask_set_cpu(cpu, &portal_cpus);
spin_unlock(&qman_lock);
pcfg->cpu = cpu;
if (!init_pcfg(pcfg))
goto err_ioremap2;
/* clear irq affinity if assigned cpu is offline */
if (!cpu_online(cpu))
qman_offline_cpu(cpu);
return 0;
err_ioremap2:
iounmap(pcfg->addr_virt[DPAA_PORTAL_CE]);
err_ioremap1:
dev_err(dev, "ioremap failed\n");
return -ENXIO;
}
static const struct of_device_id qman_portal_ids[] = {
{
.compatible = "fsl,qman-portal",
},
{}
};
MODULE_DEVICE_TABLE(of, qman_portal_ids);
static struct platform_driver qman_portal_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = qman_portal_ids,
},
.probe = qman_portal_probe,
};
static int __init qman_portal_driver_register(struct platform_driver *drv)
{
int ret;
ret = platform_driver_register(drv);
if (ret < 0)
return ret;
register_hotcpu_notifier(&qman_hotplug_cpu_notifier);
return 0;
}
module_driver(qman_portal_driver,
qman_portal_driver_register, platform_driver_unregister);

371
drivers/soc/fsl/qbman/qman_priv.h Normal file
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@ -0,0 +1,371 @@
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include "dpaa_sys.h"
#include <soc/fsl/qman.h>
#include <linux/iommu.h>
#if defined(CONFIG_FSL_PAMU)
#include <asm/fsl_pamu_stash.h>
#endif
struct qm_mcr_querywq {
u8 verb;
u8 result;
u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */
u8 __reserved[28];
u32 wq_len[8];
} __packed;
static inline u16 qm_mcr_querywq_get_chan(const struct qm_mcr_querywq *wq)
{
return wq->channel_wq >> 3;
}
struct __qm_mcr_querycongestion {
u32 state[8];
};
/* "Query Congestion Group State" */
struct qm_mcr_querycongestion {
u8 verb;
u8 result;
u8 __reserved[30];
/* Access this struct using qman_cgrs_get() */
struct __qm_mcr_querycongestion state;
} __packed;
/* "Query CGR" */
struct qm_mcr_querycgr {
u8 verb;
u8 result;
u16 __reserved1;
struct __qm_mc_cgr cgr; /* CGR fields */
u8 __reserved2[6];
u8 i_bcnt_hi; /* high 8-bits of 40-bit "Instant" */
u32 i_bcnt_lo; /* low 32-bits of 40-bit */
u8 __reserved3[3];
u8 a_bcnt_hi; /* high 8-bits of 40-bit "Average" */
u32 a_bcnt_lo; /* low 32-bits of 40-bit */
u32 cscn_targ_swp[4];
} __packed;
static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q)
{
return ((u64)q->i_bcnt_hi << 32) | (u64)q->i_bcnt_lo;
}
static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q)
{
return ((u64)q->a_bcnt_hi << 32) | (u64)q->a_bcnt_lo;
}
/* "Query FQ Non-Programmable Fields" */
struct qm_mcc_queryfq_np {
u8 _ncw_verb;
u8 __reserved1[3];
u32 fqid; /* 24-bit */
u8 __reserved2[56];
} __packed;
struct qm_mcr_queryfq_np {
u8 verb;
u8 result;
u8 __reserved1;
u8 state; /* QM_MCR_NP_STATE_*** */
u32 fqd_link; /* 24-bit, _res2[24-31] */
u16 odp_seq; /* 14-bit, _res3[14-15] */
u16 orp_nesn; /* 14-bit, _res4[14-15] */
u16 orp_ea_hseq; /* 15-bit, _res5[15] */
u16 orp_ea_tseq; /* 15-bit, _res6[15] */
u32 orp_ea_hptr; /* 24-bit, _res7[24-31] */
u32 orp_ea_tptr; /* 24-bit, _res8[24-31] */
u32 pfdr_hptr; /* 24-bit, _res9[24-31] */
u32 pfdr_tptr; /* 24-bit, _res10[24-31] */
u8 __reserved2[5];
u8 is; /* 1-bit, _res12[1-7] */
u16 ics_surp;
u32 byte_cnt;
u32 frm_cnt; /* 24-bit, _res13[24-31] */
u32 __reserved3;
u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */
u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */
u16 __reserved4;
u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */
u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */
u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */
} __packed;
#define QM_MCR_NP_STATE_FE 0x10
#define QM_MCR_NP_STATE_R 0x08
#define QM_MCR_NP_STATE_MASK 0x07 /* Reads FQD::STATE; */
#define QM_MCR_NP_STATE_OOS 0x00
#define QM_MCR_NP_STATE_RETIRED 0x01
#define QM_MCR_NP_STATE_TEN_SCHED 0x02
#define QM_MCR_NP_STATE_TRU_SCHED 0x03
#define QM_MCR_NP_STATE_PARKED 0x04
#define QM_MCR_NP_STATE_ACTIVE 0x05
#define QM_MCR_NP_PTR_MASK 0x07ff /* for RA[12] & OD[123] */
#define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */
#define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */
#define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */
#define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */
enum qm_mcr_queryfq_np_masks {
qm_mcr_fqd_link_mask = BIT(24)-1,
qm_mcr_odp_seq_mask = BIT(14)-1,
qm_mcr_orp_nesn_mask = BIT(14)-1,
qm_mcr_orp_ea_hseq_mask = BIT(15)-1,
qm_mcr_orp_ea_tseq_mask = BIT(15)-1,
qm_mcr_orp_ea_hptr_mask = BIT(24)-1,
qm_mcr_orp_ea_tptr_mask = BIT(24)-1,
qm_mcr_pfdr_hptr_mask = BIT(24)-1,
qm_mcr_pfdr_tptr_mask = BIT(24)-1,
qm_mcr_is_mask = BIT(1)-1,
qm_mcr_frm_cnt_mask = BIT(24)-1,
};
#define qm_mcr_np_get(np, field) \
((np)->field & (qm_mcr_##field##_mask))
/* Congestion Groups */
/*
* This wrapper represents a bit-array for the state of the 256 QMan congestion
* groups. Is also used as a *mask* for congestion groups, eg. so we ignore
* those that don't concern us. We harness the structure and accessor details
* already used in the management command to query congestion groups.
*/
#define CGR_BITS_PER_WORD 5
#define CGR_WORD(x) ((x) >> CGR_BITS_PER_WORD)
#define CGR_BIT(x) (BIT(31) >> ((x) & 0x1f))
#define CGR_NUM (sizeof(struct __qm_mcr_querycongestion) << 3)
struct qman_cgrs {
struct __qm_mcr_querycongestion q;
};
static inline void qman_cgrs_init(struct qman_cgrs *c)
{
memset(c, 0, sizeof(*c));
}
static inline void qman_cgrs_fill(struct qman_cgrs *c)
{
memset(c, 0xff, sizeof(*c));
}
static inline int qman_cgrs_get(struct qman_cgrs *c, u8 cgr)
{
return c->q.state[CGR_WORD(cgr)] & CGR_BIT(cgr);
}
static inline void qman_cgrs_cp(struct qman_cgrs *dest,
const struct qman_cgrs *src)
{
*dest = *src;
}
static inline void qman_cgrs_and(struct qman_cgrs *dest,
const struct qman_cgrs *a, const struct qman_cgrs *b)
{
int ret;
u32 *_d = dest->q.state;
const u32 *_a = a->q.state;
const u32 *_b = b->q.state;
for (ret = 0; ret < 8; ret++)
*_d++ = *_a++ & *_b++;
}
static inline void qman_cgrs_xor(struct qman_cgrs *dest,
const struct qman_cgrs *a, const struct qman_cgrs *b)
{
int ret;
u32 *_d = dest->q.state;
const u32 *_a = a->q.state;
const u32 *_b = b->q.state;
for (ret = 0; ret < 8; ret++)
*_d++ = *_a++ ^ *_b++;
}
void qman_init_cgr_all(void);
struct qm_portal_config {
/*
* Corenet portal addresses;
* [0]==cache-enabled, [1]==cache-inhibited.
*/
void __iomem *addr_virt[2];
struct device *dev;
struct iommu_domain *iommu_domain;
/* Allow these to be joined in lists */
struct list_head list;
/* User-visible portal configuration settings */
/* portal is affined to this cpu */
int cpu;
/* portal interrupt line */
int irq;
/*
* the portal's dedicated channel id, used initialising
* frame queues to target this portal when scheduled
*/
u16 channel;
/*
* mask of pool channels this portal has dequeue access to
* (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask)
*/
u32 pools;
};
/* Revision info (for errata and feature handling) */
#define QMAN_REV11 0x0101
#define QMAN_REV12 0x0102
#define QMAN_REV20 0x0200
#define QMAN_REV30 0x0300
#define QMAN_REV31 0x0301
extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
#define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
extern struct gen_pool *qm_fqalloc; /* FQID allocator */
extern struct gen_pool *qm_qpalloc; /* pool-channel allocator */
extern struct gen_pool *qm_cgralloc; /* CGR ID allocator */
u32 qm_get_pools_sdqcr(void);
int qman_wq_alloc(void);
void qman_liodn_fixup(u16 channel);
void qman_set_sdest(u16 channel, unsigned int cpu_idx);
struct qman_portal *qman_create_affine_portal(
const struct qm_portal_config *config,
const struct qman_cgrs *cgrs);
const struct qm_portal_config *qman_destroy_affine_portal(void);
/*
* qman_query_fq - Queries FQD fields (via h/w query command)
* @fq: the frame queue object to be queried
* @fqd: storage for the queried FQD fields
*/
int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd);
/*
* For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use
* NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
* FQID(n) to fill in the frame queue ID.
*/
#define QM_VDQCR_PRECEDENCE_VDQCR 0x0
#define QM_VDQCR_PRECEDENCE_SDQCR 0x80000000
#define QM_VDQCR_EXACT 0x40000000
#define QM_VDQCR_NUMFRAMES_MASK 0x3f000000
#define QM_VDQCR_NUMFRAMES_SET(n) (((n) & 0x3f) << 24)
#define QM_VDQCR_NUMFRAMES_GET(n) (((n) >> 24) & 0x3f)
#define QM_VDQCR_NUMFRAMES_TILLEMPTY QM_VDQCR_NUMFRAMES_SET(0)
#define QMAN_VOLATILE_FLAG_WAIT 0x00000001 /* wait if VDQCR is in use */
#define QMAN_VOLATILE_FLAG_WAIT_INT 0x00000002 /* if wait, interruptible? */
#define QMAN_VOLATILE_FLAG_FINISH 0x00000004 /* wait till VDQCR completes */
/*
* qman_volatile_dequeue - Issue a volatile dequeue command
* @fq: the frame queue object to dequeue from
* @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options
* @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set()
*
* Attempts to lock access to the portal's VDQCR volatile dequeue functionality.
* The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and
* the VDQCR is already in use, otherwise returns non-zero for failure. If
* QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once
* the VDQCR command has finished executing (ie. once the callback for the last
* DQRR entry resulting from the VDQCR command has been called). If not using
* the FINISH flag, completion can be determined either by detecting the
* presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits
* in the "stat" parameter passed to the FQ's dequeue callback, or by waiting
* for the QMAN_FQ_STATE_VDQCR bit to disappear.
*/
int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr);
int qman_alloc_fq_table(u32 num_fqids);
/* QMan s/w corenet portal, low-level i/face */
/*
* For qm_dqrr_sdqcr_set(); Choose one SOURCE. Choose one COUNT. Choose one
* dequeue TYPE. Choose TOKEN (8-bit).
* If SOURCE == CHANNELS,
* Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n).
* You can choose DEDICATED_PRECEDENCE if the portal channel should have
* priority.
* If SOURCE == SPECIFICWQ,
* Either select the work-queue ID with SPECIFICWQ_WQ(), or select the
* channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the
* work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the
* same value.
*/
#define QM_SDQCR_SOURCE_CHANNELS 0x0
#define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000
#define QM_SDQCR_COUNT_EXACT1 0x0
#define QM_SDQCR_COUNT_UPTO3 0x20000000
#define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000
#define QM_SDQCR_TYPE_MASK 0x03000000
#define QM_SDQCR_TYPE_NULL 0x0
#define QM_SDQCR_TYPE_PRIO_QOS 0x01000000
#define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000
#define QM_SDQCR_TYPE_ACTIVE 0x03000000
#define QM_SDQCR_TOKEN_MASK 0x00ff0000
#define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16)
#define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff)
#define QM_SDQCR_CHANNELS_DEDICATED 0x00008000
#define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7
#define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000
#define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
#define QM_SDQCR_SPECIFICWQ_WQ(n) (n)
/* For qm_dqrr_vdqcr_set(): use FQID(n) to fill in the frame queue ID */
#define QM_VDQCR_FQID_MASK 0x00ffffff
#define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK)
/*
* Used by all portal interrupt registers except 'inhibit'
* Channels with frame availability
*/
#define QM_PIRQ_DQAVAIL 0x0000ffff
/* The DQAVAIL interrupt fields break down into these bits; */
#define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */
#define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */
#define QM_DQAVAIL_MASK 0xffff
/* This mask contains all the "irqsource" bits visible to API users */
#define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI)
extern struct qman_portal *affine_portals[NR_CPUS];
const struct qm_portal_config *qman_get_qm_portal_config(
struct qman_portal *portal);

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/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qman_test.h"
MODULE_AUTHOR("Geoff Thorpe");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("QMan testing");
static int test_init(void)
{
int loop = 1;
int err = 0;
while (loop--) {
#ifdef CONFIG_FSL_QMAN_TEST_STASH
err = qman_test_stash();
if (err)
break;
#endif
#ifdef CONFIG_FSL_QMAN_TEST_API
err = qman_test_api();
if (err)
break;
#endif
}
return err;
}
static void test_exit(void)
{
}
module_init(test_init);
module_exit(test_exit);

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/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qman_priv.h"
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
int qman_test_stash(void);
int qman_test_api(void);

252
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/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qman_test.h"
#define CGR_ID 27
#define POOL_ID 2
#define FQ_FLAGS QMAN_FQ_FLAG_DYNAMIC_FQID
#define NUM_ENQUEUES 10
#define NUM_PARTIAL 4
#define PORTAL_SDQCR (QM_SDQCR_SOURCE_CHANNELS | \
QM_SDQCR_TYPE_PRIO_QOS | \
QM_SDQCR_TOKEN_SET(0x98) | \
QM_SDQCR_CHANNELS_DEDICATED | \
QM_SDQCR_CHANNELS_POOL(POOL_ID))
#define PORTAL_OPAQUE ((void *)0xf00dbeef)
#define VDQCR_FLAGS (QMAN_VOLATILE_FLAG_WAIT | QMAN_VOLATILE_FLAG_FINISH)
static enum qman_cb_dqrr_result cb_dqrr(struct qman_portal *,
struct qman_fq *,
const struct qm_dqrr_entry *);
static void cb_ern(struct qman_portal *, struct qman_fq *,
const union qm_mr_entry *);
static void cb_fqs(struct qman_portal *, struct qman_fq *,
const union qm_mr_entry *);
static struct qm_fd fd, fd_dq;
static struct qman_fq fq_base = {
.cb.dqrr = cb_dqrr,
.cb.ern = cb_ern,
.cb.fqs = cb_fqs
};
static DECLARE_WAIT_QUEUE_HEAD(waitqueue);
static int retire_complete, sdqcr_complete;
/* Helpers for initialising and "incrementing" a frame descriptor */
static void fd_init(struct qm_fd *fd)
{
qm_fd_addr_set64(fd, 0xabdeadbeefLLU);
qm_fd_set_contig_big(fd, 0x0000ffff);
fd->cmd = 0xfeedf00d;
}
static void fd_inc(struct qm_fd *fd)
{
u64 t = qm_fd_addr_get64(fd);
int z = t >> 40;
unsigned int len, off;
enum qm_fd_format fmt;
t <<= 1;
if (z)
t |= 1;
qm_fd_addr_set64(fd, t);
fmt = qm_fd_get_format(fd);
off = qm_fd_get_offset(fd);
len = qm_fd_get_length(fd);
len--;
qm_fd_set_param(fd, fmt, off, len);
fd->cmd++;
}
/* The only part of the 'fd' we can't memcmp() is the ppid */
static int fd_cmp(const struct qm_fd *a, const struct qm_fd *b)
{
int r = (qm_fd_addr_get64(a) == qm_fd_addr_get64(b)) ? 0 : -1;
if (!r) {
enum qm_fd_format fmt_a, fmt_b;
fmt_a = qm_fd_get_format(a);
fmt_b = qm_fd_get_format(b);
r = fmt_a - fmt_b;
}
if (!r)
r = a->cfg - b->cfg;
if (!r)
r = a->cmd - b->cmd;
return r;
}
/* test */
static int do_enqueues(struct qman_fq *fq)
{
unsigned int loop;
int err = 0;
for (loop = 0; loop < NUM_ENQUEUES; loop++) {
if (qman_enqueue(fq, &fd)) {
pr_crit("qman_enqueue() failed\n");
err = -EIO;
}
fd_inc(&fd);
}
return err;
}
int qman_test_api(void)
{
unsigned int flags, frmcnt;
int err;
struct qman_fq *fq = &fq_base;
pr_info("%s(): Starting\n", __func__);
fd_init(&fd);
fd_init(&fd_dq);
/* Initialise (parked) FQ */
err = qman_create_fq(0, FQ_FLAGS, fq);
if (err) {
pr_crit("qman_create_fq() failed\n");
goto failed;
}
err = qman_init_fq(fq, QMAN_INITFQ_FLAG_LOCAL, NULL);
if (err) {
pr_crit("qman_init_fq() failed\n");
goto failed;
}
/* Do enqueues + VDQCR, twice. (Parked FQ) */
err = do_enqueues(fq);
if (err)
goto failed;
pr_info("VDQCR (till-empty);\n");
frmcnt = QM_VDQCR_NUMFRAMES_TILLEMPTY;
err = qman_volatile_dequeue(fq, VDQCR_FLAGS, frmcnt);
if (err) {
pr_crit("qman_volatile_dequeue() failed\n");
goto failed;
}
err = do_enqueues(fq);
if (err)
goto failed;
pr_info("VDQCR (%d of %d);\n", NUM_PARTIAL, NUM_ENQUEUES);
frmcnt = QM_VDQCR_NUMFRAMES_SET(NUM_PARTIAL);
err = qman_volatile_dequeue(fq, VDQCR_FLAGS, frmcnt);
if (err) {
pr_crit("qman_volatile_dequeue() failed\n");
goto failed;
}
pr_info("VDQCR (%d of %d);\n", NUM_ENQUEUES - NUM_PARTIAL,
NUM_ENQUEUES);
frmcnt = QM_VDQCR_NUMFRAMES_SET(NUM_ENQUEUES - NUM_PARTIAL);
err = qman_volatile_dequeue(fq, VDQCR_FLAGS, frmcnt);
if (err) {
pr_err("qman_volatile_dequeue() failed\n");
goto failed;
}
err = do_enqueues(fq);
if (err)
goto failed;
pr_info("scheduled dequeue (till-empty)\n");
err = qman_schedule_fq(fq);
if (err) {
pr_crit("qman_schedule_fq() failed\n");
goto failed;
}
wait_event(waitqueue, sdqcr_complete);
/* Retire and OOS the FQ */
err = qman_retire_fq(fq, &flags);
if (err < 0) {
pr_crit("qman_retire_fq() failed\n");
goto failed;
}
wait_event(waitqueue, retire_complete);
if (flags & QMAN_FQ_STATE_BLOCKOOS) {
err = -EIO;
pr_crit("leaking frames\n");
goto failed;
}
err = qman_oos_fq(fq);
if (err) {
pr_crit("qman_oos_fq() failed\n");
goto failed;
}
qman_destroy_fq(fq);
pr_info("%s(): Finished\n", __func__);
return 0;
failed:
WARN_ON(1);
return err;
}
static enum qman_cb_dqrr_result cb_dqrr(struct qman_portal *p,
struct qman_fq *fq,
const struct qm_dqrr_entry *dq)
{
if (WARN_ON(fd_cmp(&fd_dq, &dq->fd))) {
pr_err("BADNESS: dequeued frame doesn't match;\n");
return qman_cb_dqrr_consume;
}
fd_inc(&fd_dq);
if (!(dq->stat & QM_DQRR_STAT_UNSCHEDULED) && !fd_cmp(&fd_dq, &fd)) {
sdqcr_complete = 1;
wake_up(&waitqueue);
}
return qman_cb_dqrr_consume;
}
static void cb_ern(struct qman_portal *p, struct qman_fq *fq,
const union qm_mr_entry *msg)
{
pr_crit("cb_ern() unimplemented");
WARN_ON(1);
}
static void cb_fqs(struct qman_portal *p, struct qman_fq *fq,
const union qm_mr_entry *msg)
{
u8 verb = (msg->verb & QM_MR_VERB_TYPE_MASK);
if ((verb != QM_MR_VERB_FQRN) && (verb != QM_MR_VERB_FQRNI)) {
pr_crit("unexpected FQS message");
WARN_ON(1);
return;
}
pr_info("Retirement message received\n");
retire_complete = 1;
wake_up(&waitqueue);
}

617
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/* Copyright 2009 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qman_test.h"
#include <linux/dma-mapping.h>
#include <linux/delay.h>
/*
* Algorithm:
*
* Each cpu will have HP_PER_CPU "handlers" set up, each of which incorporates
* an rx/tx pair of FQ objects (both of which are stashed on dequeue). The
* organisation of FQIDs is such that the HP_PER_CPU*NUM_CPUS handlers will
* shuttle a "hot potato" frame around them such that every forwarding action
* moves it from one cpu to another. (The use of more than one handler per cpu
* is to allow enough handlers/FQs to truly test the significance of caching -
* ie. when cache-expiries are occurring.)
*
* The "hot potato" frame content will be HP_NUM_WORDS*4 bytes in size, and the
* first and last words of the frame data will undergo a transformation step on
* each forwarding action. To achieve this, each handler will be assigned a
* 32-bit "mixer", that is produced using a 32-bit LFSR. When a frame is
* received by a handler, the mixer of the expected sender is XOR'd into all
* words of the entire frame, which is then validated against the original
* values. Then, before forwarding, the entire frame is XOR'd with the mixer of
* the current handler. Apart from validating that the frame is taking the
* expected path, this also provides some quasi-realistic overheads to each
* forwarding action - dereferencing *all* the frame data, computation, and
* conditional branching. There is a "special" handler designated to act as the
* instigator of the test by creating an enqueuing the "hot potato" frame, and
* to determine when the test has completed by counting HP_LOOPS iterations.
*
* Init phases:
*
* 1. prepare each cpu's 'hp_cpu' struct using on_each_cpu(,,1) and link them
* into 'hp_cpu_list'. Specifically, set processor_id, allocate HP_PER_CPU
* handlers and link-list them (but do no other handler setup).
*
* 2. scan over 'hp_cpu_list' HP_PER_CPU times, the first time sets each
* hp_cpu's 'iterator' to point to its first handler. With each loop,
* allocate rx/tx FQIDs and mixer values to the hp_cpu's iterator handler
* and advance the iterator for the next loop. This includes a final fixup,
* which connects the last handler to the first (and which is why phase 2
* and 3 are separate).
*
* 3. scan over 'hp_cpu_list' HP_PER_CPU times, the first time sets each
* hp_cpu's 'iterator' to point to its first handler. With each loop,
* initialise FQ objects and advance the iterator for the next loop.
* Moreover, do this initialisation on the cpu it applies to so that Rx FQ
* initialisation targets the correct cpu.
*/
/*
* helper to run something on all cpus (can't use on_each_cpu(), as that invokes
* the fn from irq context, which is too restrictive).
*/
struct bstrap {
int (*fn)(void);
atomic_t started;
};
static int bstrap_fn(void *bs)
{
struct bstrap *bstrap = bs;
int err;
atomic_inc(&bstrap->started);
err = bstrap->fn();
if (err)
return err;
while (!kthread_should_stop())
msleep(20);
return 0;
}
static int on_all_cpus(int (*fn)(void))
{
int cpu;
for_each_cpu(cpu, cpu_online_mask) {
struct bstrap bstrap = {
.fn = fn,
.started = ATOMIC_INIT(0)
};
struct task_struct *k = kthread_create(bstrap_fn, &bstrap,
"hotpotato%d", cpu);
int ret;
if (IS_ERR(k))
return -ENOMEM;
kthread_bind(k, cpu);
wake_up_process(k);
/*
* If we call kthread_stop() before the "wake up" has had an
* effect, then the thread may exit with -EINTR without ever
* running the function. So poll until it's started before
* requesting it to stop.
*/
while (!atomic_read(&bstrap.started))
msleep(20);
ret = kthread_stop(k);
if (ret)
return ret;
}
return 0;
}
struct hp_handler {
/* The following data is stashed when 'rx' is dequeued; */
/* -------------- */
/* The Rx FQ, dequeues of which will stash the entire hp_handler */
struct qman_fq rx;
/* The Tx FQ we should forward to */
struct qman_fq tx;
/* The value we XOR post-dequeue, prior to validating */
u32 rx_mixer;
/* The value we XOR pre-enqueue, after validating */
u32 tx_mixer;
/* what the hotpotato address should be on dequeue */
dma_addr_t addr;
u32 *frame_ptr;
/* The following data isn't (necessarily) stashed on dequeue; */
/* -------------- */
u32 fqid_rx, fqid_tx;
/* list node for linking us into 'hp_cpu' */
struct list_head node;
/* Just to check ... */
unsigned int processor_id;
} ____cacheline_aligned;
struct hp_cpu {
/* identify the cpu we run on; */
unsigned int processor_id;
/* root node for the per-cpu list of handlers */
struct list_head handlers;
/* list node for linking us into 'hp_cpu_list' */
struct list_head node;
/*
* when repeatedly scanning 'hp_list', each time linking the n'th
* handlers together, this is used as per-cpu iterator state
*/
struct hp_handler *iterator;
};
/* Each cpu has one of these */
static DEFINE_PER_CPU(struct hp_cpu, hp_cpus);
/* links together the hp_cpu structs, in first-come first-serve order. */
static LIST_HEAD(hp_cpu_list);
static spinlock_t hp_lock = __SPIN_LOCK_UNLOCKED(hp_lock);
static unsigned int hp_cpu_list_length;
/* the "special" handler, that starts and terminates the test. */
static struct hp_handler *special_handler;
static int loop_counter;
/* handlers are allocated out of this, so they're properly aligned. */
static struct kmem_cache *hp_handler_slab;
/* this is the frame data */
static void *__frame_ptr;
static u32 *frame_ptr;
static dma_addr_t frame_dma;
/* the main function waits on this */
static DECLARE_WAIT_QUEUE_HEAD(queue);
#define HP_PER_CPU 2
#define HP_LOOPS 8
/* 80 bytes, like a small ethernet frame, and bleeds into a second cacheline */
#define HP_NUM_WORDS 80
/* First word of the LFSR-based frame data */
#define HP_FIRST_WORD 0xabbaf00d
static inline u32 do_lfsr(u32 prev)
{
return (prev >> 1) ^ (-(prev & 1u) & 0xd0000001u);
}
static int allocate_frame_data(void)
{
u32 lfsr = HP_FIRST_WORD;
int loop;
struct platform_device *pdev = platform_device_alloc("foobar", -1);
if (!pdev) {
pr_crit("platform_device_alloc() failed");
return -EIO;
}
if (platform_device_add(pdev)) {
pr_crit("platform_device_add() failed");
return -EIO;
}
__frame_ptr = kmalloc(4 * HP_NUM_WORDS, GFP_KERNEL);
if (!__frame_ptr)
return -ENOMEM;
frame_ptr = PTR_ALIGN(__frame_ptr, 64);
for (loop = 0; loop < HP_NUM_WORDS; loop++) {
frame_ptr[loop] = lfsr;
lfsr = do_lfsr(lfsr);
}
frame_dma = dma_map_single(&pdev->dev, frame_ptr, 4 * HP_NUM_WORDS,
DMA_BIDIRECTIONAL);
platform_device_del(pdev);
platform_device_put(pdev);
return 0;
}
static void deallocate_frame_data(void)
{
kfree(__frame_ptr);
}
static inline int process_frame_data(struct hp_handler *handler,
const struct qm_fd *fd)
{
u32 *p = handler->frame_ptr;
u32 lfsr = HP_FIRST_WORD;
int loop;
if (qm_fd_addr_get64(fd) != handler->addr) {
pr_crit("bad frame address");
return -EIO;
}
for (loop = 0; loop < HP_NUM_WORDS; loop++, p++) {
*p ^= handler->rx_mixer;
if (*p != lfsr) {
pr_crit("corrupt frame data");
return -EIO;
}
*p ^= handler->tx_mixer;
lfsr = do_lfsr(lfsr);
}
return 0;
}
static enum qman_cb_dqrr_result normal_dqrr(struct qman_portal *portal,
struct qman_fq *fq,
const struct qm_dqrr_entry *dqrr)
{
struct hp_handler *handler = (struct hp_handler *)fq;
if (process_frame_data(handler, &dqrr->fd)) {
WARN_ON(1);
goto skip;
}
if (qman_enqueue(&handler->tx, &dqrr->fd)) {
pr_crit("qman_enqueue() failed");
WARN_ON(1);
}
skip:
return qman_cb_dqrr_consume;
}
static enum qman_cb_dqrr_result special_dqrr(struct qman_portal *portal,
struct qman_fq *fq,
const struct qm_dqrr_entry *dqrr)
{
struct hp_handler *handler = (struct hp_handler *)fq;
process_frame_data(handler, &dqrr->fd);
if (++loop_counter < HP_LOOPS) {
if (qman_enqueue(&handler->tx, &dqrr->fd)) {
pr_crit("qman_enqueue() failed");
WARN_ON(1);
goto skip;
}
} else {
pr_info("Received final (%dth) frame\n", loop_counter);
wake_up(&queue);
}
skip:
return qman_cb_dqrr_consume;
}
static int create_per_cpu_handlers(void)
{
struct hp_handler *handler;
int loop;
struct hp_cpu *hp_cpu = this_cpu_ptr(&hp_cpus);
hp_cpu->processor_id = smp_processor_id();
spin_lock(&hp_lock);
list_add_tail(&hp_cpu->node, &hp_cpu_list);
hp_cpu_list_length++;
spin_unlock(&hp_lock);
INIT_LIST_HEAD(&hp_cpu->handlers);
for (loop = 0; loop < HP_PER_CPU; loop++) {
handler = kmem_cache_alloc(hp_handler_slab, GFP_KERNEL);
if (!handler) {
pr_crit("kmem_cache_alloc() failed");
WARN_ON(1);
return -EIO;
}
handler->processor_id = hp_cpu->processor_id;
handler->addr = frame_dma;
handler->frame_ptr = frame_ptr;
list_add_tail(&handler->node, &hp_cpu->handlers);
}
return 0;
}
static int destroy_per_cpu_handlers(void)
{
struct list_head *loop, *tmp;
struct hp_cpu *hp_cpu = this_cpu_ptr(&hp_cpus);
spin_lock(&hp_lock);
list_del(&hp_cpu->node);
spin_unlock(&hp_lock);
list_for_each_safe(loop, tmp, &hp_cpu->handlers) {
u32 flags = 0;
struct hp_handler *handler = list_entry(loop, struct hp_handler,
node);
if (qman_retire_fq(&handler->rx, &flags) ||
(flags & QMAN_FQ_STATE_BLOCKOOS)) {
pr_crit("qman_retire_fq(rx) failed, flags: %x", flags);
WARN_ON(1);
return -EIO;
}
if (qman_oos_fq(&handler->rx)) {
pr_crit("qman_oos_fq(rx) failed");
WARN_ON(1);
return -EIO;
}
qman_destroy_fq(&handler->rx);
qman_destroy_fq(&handler->tx);
qman_release_fqid(handler->fqid_rx);
list_del(&handler->node);
kmem_cache_free(hp_handler_slab, handler);
}
return 0;
}
static inline u8 num_cachelines(u32 offset)
{
u8 res = (offset + (L1_CACHE_BYTES - 1))
/ (L1_CACHE_BYTES);
if (res > 3)
return 3;
return res;
}
#define STASH_DATA_CL \
num_cachelines(HP_NUM_WORDS * 4)
#define STASH_CTX_CL \
num_cachelines(offsetof(struct hp_handler, fqid_rx))
static int init_handler(void *h)
{
struct qm_mcc_initfq opts;
struct hp_handler *handler = h;
int err;
if (handler->processor_id != smp_processor_id()) {
err = -EIO;
goto failed;
}
/* Set up rx */
memset(&handler->rx, 0, sizeof(handler->rx));
if (handler == special_handler)
handler->rx.cb.dqrr = special_dqrr;
else
handler->rx.cb.dqrr = normal_dqrr;
err = qman_create_fq(handler->fqid_rx, 0, &handler->rx);
if (err) {
pr_crit("qman_create_fq(rx) failed");
goto failed;
}
memset(&opts, 0, sizeof(opts));
opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
opts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING;
qm_fqd_set_stashing(&opts.fqd, 0, STASH_DATA_CL, STASH_CTX_CL);
err = qman_init_fq(&handler->rx, QMAN_INITFQ_FLAG_SCHED |
QMAN_INITFQ_FLAG_LOCAL, &opts);
if (err) {
pr_crit("qman_init_fq(rx) failed");
goto failed;
}
/* Set up tx */
memset(&handler->tx, 0, sizeof(handler->tx));
err = qman_create_fq(handler->fqid_tx, QMAN_FQ_FLAG_NO_MODIFY,
&handler->tx);
if (err) {
pr_crit("qman_create_fq(tx) failed");
goto failed;
}
return 0;
failed:
return err;
}
static void init_handler_cb(void *h)
{
if (init_handler(h))
WARN_ON(1);
}
static int init_phase2(void)
{
int loop;
u32 fqid = 0;
u32 lfsr = 0xdeadbeef;
struct hp_cpu *hp_cpu;
struct hp_handler *handler;
for (loop = 0; loop < HP_PER_CPU; loop++) {
list_for_each_entry(hp_cpu, &hp_cpu_list, node) {
int err;
if (!loop)
hp_cpu->iterator = list_first_entry(
&hp_cpu->handlers,
struct hp_handler, node);
else
hp_cpu->iterator = list_entry(
hp_cpu->iterator->node.next,
struct hp_handler, node);
/* Rx FQID is the previous handler's Tx FQID */
hp_cpu->iterator->fqid_rx = fqid;
/* Allocate new FQID for Tx */
err = qman_alloc_fqid(&fqid);
if (err) {
pr_crit("qman_alloc_fqid() failed");
return err;
}
hp_cpu->iterator->fqid_tx = fqid;
/* Rx mixer is the previous handler's Tx mixer */
hp_cpu->iterator->rx_mixer = lfsr;
/* Get new mixer for Tx */
lfsr = do_lfsr(lfsr);
hp_cpu->iterator->tx_mixer = lfsr;
}
}
/* Fix up the first handler (fqid_rx==0, rx_mixer=0xdeadbeef) */
hp_cpu = list_first_entry(&hp_cpu_list, struct hp_cpu, node);
handler = list_first_entry(&hp_cpu->handlers, struct hp_handler, node);
if (handler->fqid_rx != 0 || handler->rx_mixer != 0xdeadbeef)
return 1;
handler->fqid_rx = fqid;
handler->rx_mixer = lfsr;
/* and tag it as our "special" handler */
special_handler = handler;
return 0;
}
static int init_phase3(void)
{
int loop, err;
struct hp_cpu *hp_cpu;
for (loop = 0; loop < HP_PER_CPU; loop++) {
list_for_each_entry(hp_cpu, &hp_cpu_list, node) {
if (!loop)
hp_cpu->iterator = list_first_entry(
&hp_cpu->handlers,
struct hp_handler, node);
else
hp_cpu->iterator = list_entry(
hp_cpu->iterator->node.next,
struct hp_handler, node);
preempt_disable();
if (hp_cpu->processor_id == smp_processor_id()) {
err = init_handler(hp_cpu->iterator);
if (err)
return err;
} else {
smp_call_function_single(hp_cpu->processor_id,
init_handler_cb, hp_cpu->iterator, 1);
}
preempt_enable();
}
}
return 0;
}
static int send_first_frame(void *ignore)
{
u32 *p = special_handler->frame_ptr;
u32 lfsr = HP_FIRST_WORD;
int loop, err;
struct qm_fd fd;
if (special_handler->processor_id != smp_processor_id()) {
err = -EIO;
goto failed;
}
memset(&fd, 0, sizeof(fd));
qm_fd_addr_set64(&fd, special_handler->addr);
qm_fd_set_contig_big(&fd, HP_NUM_WORDS * 4);
for (loop = 0; loop < HP_NUM_WORDS; loop++, p++) {
if (*p != lfsr) {
err = -EIO;
pr_crit("corrupt frame data");
goto failed;
}
*p ^= special_handler->tx_mixer;
lfsr = do_lfsr(lfsr);
}
pr_info("Sending first frame\n");
err = qman_enqueue(&special_handler->tx, &fd);
if (err) {
pr_crit("qman_enqueue() failed");
goto failed;
}
return 0;
failed:
return err;
}
static void send_first_frame_cb(void *ignore)
{
if (send_first_frame(NULL))
WARN_ON(1);
}
int qman_test_stash(void)
{
int err;
if (cpumask_weight(cpu_online_mask) < 2) {
pr_info("%s(): skip - only 1 CPU\n", __func__);
return 0;
}
pr_info("%s(): Starting\n", __func__);
hp_cpu_list_length = 0;
loop_counter = 0;
hp_handler_slab = kmem_cache_create("hp_handler_slab",
sizeof(struct hp_handler), L1_CACHE_BYTES,
SLAB_HWCACHE_ALIGN, NULL);
if (!hp_handler_slab) {
err = -EIO;
pr_crit("kmem_cache_create() failed");
goto failed;
}
err = allocate_frame_data();
if (err)
goto failed;
/* Init phase 1 */
pr_info("Creating %d handlers per cpu...\n", HP_PER_CPU);
if (on_all_cpus(create_per_cpu_handlers)) {
err = -EIO;
pr_crit("on_each_cpu() failed");
goto failed;
}
pr_info("Number of cpus: %d, total of %d handlers\n",
hp_cpu_list_length, hp_cpu_list_length * HP_PER_CPU);
err = init_phase2();
if (err)
goto failed;
err = init_phase3();
if (err)
goto failed;
preempt_disable();
if (special_handler->processor_id == smp_processor_id()) {
err = send_first_frame(NULL);
if (err)
goto failed;
} else {
smp_call_function_single(special_handler->processor_id,
send_first_frame_cb, NULL, 1);
}
preempt_enable();
wait_event(queue, loop_counter == HP_LOOPS);
deallocate_frame_data();
if (on_all_cpus(destroy_per_cpu_handlers)) {
err = -EIO;
pr_crit("on_each_cpu() failed");
goto failed;
}
kmem_cache_destroy(hp_handler_slab);
pr_info("%s(): Finished\n", __func__);
return 0;
failed:
WARN_ON(1);
return err;
}

3
drivers/soc/fsl/qe/gpio.c
View File

@ -41,7 +41,8 @@ struct qe_gpio_chip {
static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
{
struct qe_gpio_chip *qe_gc = gpiochip_get_data(&mm_gc->gc);
struct qe_gpio_chip *qe_gc =
container_of(mm_gc, struct qe_gpio_chip, mm_gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
qe_gc->cpdata = in_be32(&regs->cpdata);

10
drivers/soc/fsl/qe/qe.c
View File

@ -69,8 +69,8 @@ static phys_addr_t qebase = -1;
phys_addr_t get_qe_base(void)
{
struct device_node *qe;
int size;
const u32 *prop;
int ret;
struct resource res;
if (qebase != -1)
return qebase;
@ -82,9 +82,9 @@ phys_addr_t get_qe_base(void)
return qebase;
}
prop = of_get_property(qe, "reg", &size);
if (prop && size >= sizeof(*prop))
qebase = of_translate_address(qe, prop);
ret = of_address_to_resource(qe, 0, &res);
if (!ret)
qebase = res.start;
of_node_put(qe);
return qebase;

8
drivers/soc/fsl/qe/qe_common.c
View File

@ -70,6 +70,11 @@ int cpm_muram_init(void)
}
muram_pool = gen_pool_create(0, -1);
if (!muram_pool) {
pr_err("Cannot allocate memory pool for CPM/QE muram");
ret = -ENOMEM;
goto out_muram;
}
muram_pbase = of_translate_address(np, zero);
if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) {
pr_err("Cannot translate zero through CPM muram node");
@ -116,6 +121,9 @@ static unsigned long cpm_muram_alloc_common(unsigned long size,
struct muram_block *entry;
unsigned long start;
if (!muram_pool && cpm_muram_init())
goto out2;
start = gen_pool_alloc_algo(muram_pool, size, algo, data);
if (!start)
goto out2;

4
drivers/soc/fsl/qe/qe_tdm.c
View File

@ -99,7 +99,7 @@ int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
utdm->tdm_port = val;
ut_info->uf_info.tdm_num = utdm->tdm_port;
if (of_get_property(np, "fsl,tdm-internal-loopback", NULL))
if (of_property_read_bool(np, "fsl,tdm-internal-loopback"))
utdm->tdm_mode = TDM_INTERNAL_LOOPBACK;
else
utdm->tdm_mode = TDM_NORMAL;
@ -167,7 +167,7 @@ int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
}
if (siram_init_flag == 0) {
memset_io(utdm->siram, 0, res->end - res->start + 1);
memset_io(utdm->siram, 0, resource_size(res));
siram_init_flag = 1;
}

129
include/soc/fsl/bman.h Normal file
View File

@ -0,0 +1,129 @@
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FSL_BMAN_H
#define __FSL_BMAN_H
/* wrapper for 48-bit buffers */
struct bm_buffer {
union {
struct {
__be16 bpid; /* hi 8-bits reserved */
__be16 hi; /* High 16-bits of 48-bit address */
__be32 lo; /* Low 32-bits of 48-bit address */
};
__be64 data;
};
} __aligned(8);
/*
* Restore the 48 bit address previously stored in BMan
* hardware pools as a dma_addr_t
*/
static inline dma_addr_t bm_buf_addr(const struct bm_buffer *buf)
{
return be64_to_cpu(buf->data) & 0xffffffffffffLLU;
}
static inline u64 bm_buffer_get64(const struct bm_buffer *buf)
{
return be64_to_cpu(buf->data) & 0xffffffffffffLLU;
}
static inline void bm_buffer_set64(struct bm_buffer *buf, u64 addr)
{
buf->hi = cpu_to_be16(upper_32_bits(addr));
buf->lo = cpu_to_be32(lower_32_bits(addr));
}
static inline u8 bm_buffer_get_bpid(const struct bm_buffer *buf)
{
return be16_to_cpu(buf->bpid) & 0xff;
}
static inline void bm_buffer_set_bpid(struct bm_buffer *buf, int bpid)
{
buf->bpid = cpu_to_be16(bpid & 0xff);
}
/* Managed portal, high-level i/face */
/* Portal and Buffer Pools */
struct bman_portal;
struct bman_pool;
#define BM_POOL_MAX 64 /* max # of buffer pools */
/**
* bman_new_pool - Allocates a Buffer Pool object
*
* Creates a pool object, and returns a reference to it or NULL on error.
*/
struct bman_pool *bman_new_pool(void);
/**
* bman_free_pool - Deallocates a Buffer Pool object
* @pool: the pool object to release
*/
void bman_free_pool(struct bman_pool *pool);
/**
* bman_get_bpid - Returns a pool object's BPID.
* @pool: the pool object
*
* The returned value is the index of the encapsulated buffer pool,
* in the range of [0, @BM_POOL_MAX-1].
*/
int bman_get_bpid(const struct bman_pool *pool);
/**
* bman_release - Release buffer(s) to the buffer pool
* @pool: the buffer pool object to release to
* @bufs: an array of buffers to release
* @num: the number of buffers in @bufs (1-8)
*
* Adds the given buffers to RCR entries. If the RCR ring is unresponsive,
* the function will return -ETIMEDOUT. Otherwise, it returns zero.
*/
int bman_release(struct bman_pool *pool, const struct bm_buffer *bufs, u8 num);
/**
* bman_acquire - Acquire buffer(s) from a buffer pool
* @pool: the buffer pool object to acquire from
* @bufs: array for storing the acquired buffers
* @num: the number of buffers desired (@bufs is at least this big)
*
* Issues an "Acquire" command via the portal's management command interface.
* The return value will be the number of buffers obtained from the pool, or a
* negative error code if a h/w error or pool starvation was encountered. In
* the latter case, the content of @bufs is undefined.
*/
int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num);
#endif /* __FSL_BMAN_H */

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include/soc/fsl/qman.h Normal file
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tools/testing/selftests/powerpc/copyloops/asm/export.h Normal file
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#define EXPORT_SYMBOL(x)

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