qlcnic: 83xx adpater flash interface routines
83xx adapter flash memory map, data structures and interface routines Signed-off-by: Himanshu Madhani <himanshu.madhani@qlogic.com> Signed-off-by: Sony Chacko <sony.chacko@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sony Chacko
David S. Miller
parent
319ecf121e
commit
d865ebb479
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@ -204,6 +204,7 @@ struct uni_data_desc{
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/* Flash Defines and Structures */
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#define QLCNIC_FLT_LOCATION 0x3F1000
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#define QLCNIC_FDT_LOCATION 0x3F0000
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#define QLCNIC_B0_FW_IMAGE_REGION 0x74
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#define QLCNIC_C0_FW_IMAGE_REGION 0x97
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#define QLCNIC_BOOTLD_REGION 0X72
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@ -224,6 +225,36 @@ struct qlcnic_flt_entry {
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u32 end_addr;
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};
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/* Flash Descriptor Table */
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struct qlcnic_fdt {
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u32 valid;
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u16 ver;
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u16 len;
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u16 cksum;
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u16 unused;
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u8 model[16];
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u16 mfg_id;
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u16 id;
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u8 flag;
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u8 erase_cmd;
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u8 alt_erase_cmd;
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u8 write_enable_cmd;
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u8 write_enable_bits;
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u8 write_statusreg_cmd;
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u8 unprotected_sec_cmd;
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u8 read_manuf_cmd;
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u32 block_size;
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u32 alt_block_size;
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u32 flash_size;
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u32 write_enable_data;
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u8 readid_addr_len;
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u8 write_disable_bits;
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u8 read_dev_id_len;
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u8 chip_erase_cmd;
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u16 read_timeo;
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u8 protected_sec_cmd;
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u8 resvd[65];
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};
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/* Magic number to let user know flash is programmed */
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#define QLCNIC_BDINFO_MAGIC 0x12345678
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@ -404,6 +435,7 @@ struct qlcnic_hardware_context {
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struct qlcnic_hardware_ops *hw_ops;
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struct qlcnic_nic_intr_coalesce coal;
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struct qlcnic_fw_dump fw_dump;
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struct qlcnic_fdt fdt;
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struct qlcnic_intrpt_config *intr_tbl;
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u32 *reg_tbl;
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u32 *ext_reg_tbl;
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@ -972,6 +1004,7 @@ struct qlcnic_adapter {
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u64 dev_rst_time;
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u8 mac_learn;
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unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
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u8 flash_mfg_id;
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struct qlcnic_npar_info *npars;
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struct qlcnic_eswitch *eswitch;
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struct qlcnic_nic_template *nic_ops;
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@ -1782,3 +1782,363 @@ out:
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qlcnic_free_mbx_args(&cmd);
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return err;
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}
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int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
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{
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int id, timeout = 0;
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u32 status = 0;
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while (status == 0) {
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status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
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if (status)
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break;
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if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
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id = QLC_SHARED_REG_RD32(adapter,
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QLCNIC_FLASH_LOCK_OWNER);
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dev_err(&adapter->pdev->dev,
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"%s: failed, lock held by %d\n", __func__, id);
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return -EIO;
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}
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usleep_range(1000, 2000);
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}
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QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
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return 0;
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}
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void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
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{
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QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
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QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
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}
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static int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
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u32 flash_addr, u8 *p_data,
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int count)
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{
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int i, ret;
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u32 word, range, flash_offset, addr = flash_addr;
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ulong indirect_add, direct_window;
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flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
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if (addr & 0x3) {
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dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
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return -EIO;
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}
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
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(addr));
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range = flash_offset + (count * sizeof(u32));
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/* Check if data is spread across multiple sectors */
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if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
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/* Multi sector read */
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for (i = 0; i < count; i++) {
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indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
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ret = qlcnic_83xx_rd_reg_indirect(adapter,
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indirect_add);
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if (ret == -EIO)
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return -EIO;
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word = ret;
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*(u32 *)p_data = word;
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p_data = p_data + 4;
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addr = addr + 4;
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flash_offset = flash_offset + 4;
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if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
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direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
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/* This write is needed once for each sector */
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qlcnic_83xx_wrt_reg_indirect(adapter,
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direct_window,
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(addr));
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flash_offset = 0;
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}
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}
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} else {
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/* Single sector read */
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for (i = 0; i < count; i++) {
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indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
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ret = qlcnic_83xx_rd_reg_indirect(adapter,
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indirect_add);
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if (ret == -EIO)
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return -EIO;
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word = ret;
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*(u32 *)p_data = word;
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p_data = p_data + 4;
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addr = addr + 4;
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}
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}
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return 0;
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}
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static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
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{
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u32 status;
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int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
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do {
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status = qlcnic_83xx_rd_reg_indirect(adapter,
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QLC_83XX_FLASH_STATUS);
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if ((status & QLC_83XX_FLASH_STATUS_READY) ==
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QLC_83XX_FLASH_STATUS_READY)
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break;
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msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
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} while (--retries);
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if (!retries)
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return -EIO;
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return 0;
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}
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static int qlcnic_83xx_enable_flash_write_op(struct qlcnic_adapter *adapter)
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{
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int ret;
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u32 cmd;
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cmd = adapter->ahw->fdt.write_statusreg_cmd;
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
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(QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
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adapter->ahw->fdt.write_enable_bits);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
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QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret)
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return -EIO;
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return 0;
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}
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static int qlcnic_83xx_disable_flash_write_op(struct qlcnic_adapter *adapter)
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{
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int ret;
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
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(QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
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adapter->ahw->fdt.write_statusreg_cmd));
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
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adapter->ahw->fdt.write_disable_bits);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
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QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret)
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return -EIO;
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return 0;
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}
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int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
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{
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int ret, mfg_id;
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if (qlcnic_83xx_lock_flash(adapter))
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return -EIO;
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
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QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
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QLC_83XX_FLASH_READ_CTRL);
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret) {
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qlcnic_83xx_unlock_flash(adapter);
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return -EIO;
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}
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mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
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if (mfg_id == -EIO)
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return -EIO;
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adapter->flash_mfg_id = (mfg_id & 0xFF);
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qlcnic_83xx_unlock_flash(adapter);
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return 0;
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}
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int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
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{
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int count, fdt_size, ret = 0;
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fdt_size = sizeof(struct qlcnic_fdt);
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count = fdt_size / sizeof(u32);
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if (qlcnic_83xx_lock_flash(adapter))
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return -EIO;
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memset(&adapter->ahw->fdt, 0, fdt_size);
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ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
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(u8 *)&adapter->ahw->fdt,
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count);
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qlcnic_83xx_unlock_flash(adapter);
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return ret;
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}
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int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
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u32 sector_start_addr)
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{
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u32 reversed_addr, addr1, addr2, cmd;
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int ret = -EIO;
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if (qlcnic_83xx_lock_flash(adapter) != 0)
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return -EIO;
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if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
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ret = qlcnic_83xx_enable_flash_write_op(adapter);
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if (ret) {
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qlcnic_83xx_unlock_flash(adapter);
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dev_err(&adapter->pdev->dev,
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"%s failed at %d\n",
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__func__, __LINE__);
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return ret;
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}
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}
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret) {
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qlcnic_83xx_unlock_flash(adapter);
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dev_err(&adapter->pdev->dev,
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"%s: failed at %d\n", __func__, __LINE__);
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return -EIO;
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}
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addr1 = (sector_start_addr & 0xFF) << 16;
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addr2 = (sector_start_addr & 0xFF0000) >> 16;
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reversed_addr = addr1 | addr2;
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
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reversed_addr);
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cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
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if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
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else
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
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QLC_83XX_FLASH_OEM_ERASE_SIG);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
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QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret) {
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qlcnic_83xx_unlock_flash(adapter);
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dev_err(&adapter->pdev->dev,
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"%s: failed at %d\n", __func__, __LINE__);
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return -EIO;
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}
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if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
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ret = qlcnic_83xx_disable_flash_write_op(adapter);
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if (ret) {
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qlcnic_83xx_unlock_flash(adapter);
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dev_err(&adapter->pdev->dev,
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"%s: failed at %d\n", __func__, __LINE__);
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return ret;
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}
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}
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qlcnic_83xx_unlock_flash(adapter);
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return 0;
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}
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int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
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u32 *p_data)
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{
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int ret = -EIO;
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u32 addr1 = 0x00800000 | (addr >> 2);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
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QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret) {
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dev_err(&adapter->pdev->dev,
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"%s: failed at %d\n", __func__, __LINE__);
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return -EIO;
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}
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return 0;
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}
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int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
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u32 *p_data, int count)
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{
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u32 temp;
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int ret = -EIO;
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if ((count < QLC_83XX_FLASH_BULK_WRITE_MIN) ||
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(count > QLC_83XX_FLASH_BULK_WRITE_MAX)) {
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dev_err(&adapter->pdev->dev,
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"%s: Invalid word count\n", __func__);
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return -EIO;
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}
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temp = qlcnic_83xx_rd_reg_indirect(adapter,
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QLC_83XX_FLASH_SPI_CONTROL);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
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(temp | QLC_83XX_FLASH_SPI_CTRL));
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
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QLC_83XX_FLASH_ADDR_TEMP_VAL);
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/* First DWORD write */
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
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QLC_83XX_FLASH_FIRST_MS_PATTERN);
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret) {
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dev_err(&adapter->pdev->dev,
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"%s: failed at %d\n", __func__, __LINE__);
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return -EIO;
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}
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count--;
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
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QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
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/* Second to N-1 DWORD writes */
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while (count != 1) {
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
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*p_data++);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
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QLC_83XX_FLASH_SECOND_MS_PATTERN);
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret) {
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dev_err(&adapter->pdev->dev,
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"%s: failed at %d\n", __func__, __LINE__);
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return -EIO;
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}
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count--;
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}
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
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QLC_83XX_FLASH_ADDR_TEMP_VAL |
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(addr >> 2));
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/* Last DWORD write */
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
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qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
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QLC_83XX_FLASH_LAST_MS_PATTERN);
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ret = qlcnic_83xx_poll_flash_status_reg(adapter);
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if (ret) {
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dev_err(&adapter->pdev->dev,
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"%s: failed at %d\n", __func__, __LINE__);
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return -EIO;
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}
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ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
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if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
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dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
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__func__, __LINE__);
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/* Operation failed, clear error bit */
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temp = qlcnic_83xx_rd_reg_indirect(adapter,
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QLC_83XX_FLASH_SPI_CONTROL);
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qlcnic_83xx_wrt_reg_indirect(adapter,
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QLC_83XX_FLASH_SPI_CONTROL,
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(temp | QLC_83XX_FLASH_SPI_CTRL));
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}
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return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -134,6 +134,46 @@ struct qlcnic_macvlan_mbx {
|
|||
#define QLC_83XX_DEFAULT_MODE 0x0
|
||||
#define QLCNIC_BRDTYPE_83XX_10G 0x0083
|
||||
|
||||
#define QLC_83XX_FLASH_SPI_STATUS 0x2808E010
|
||||
#define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014
|
||||
#define QLC_83XX_FLASH_STATUS 0x42100004
|
||||
#define QLC_83XX_FLASH_CONTROL 0x42110004
|
||||
#define QLC_83XX_FLASH_ADDR 0x42110008
|
||||
#define QLC_83XX_FLASH_WRDATA 0x4211000C
|
||||
#define QLC_83XX_FLASH_RDDATA 0x42110018
|
||||
#define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030
|
||||
#define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
|
||||
#define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
|
||||
#define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda
|
||||
#define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca
|
||||
#define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
|
||||
#define QLC_83XX_FLASH_STATUS_READY 0x6
|
||||
#define QLC_83XX_FLASH_BULK_WRITE_MIN 2
|
||||
#define QLC_83XX_FLASH_BULK_WRITE_MAX 64
|
||||
#define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1
|
||||
#define QLC_83XX_ERASE_MODE 1
|
||||
#define QLC_83XX_WRITE_MODE 2
|
||||
#define QLC_83XX_BULK_WRITE_MODE 3
|
||||
#define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100
|
||||
#define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300
|
||||
#define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F
|
||||
#define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8
|
||||
#define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101
|
||||
#define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005
|
||||
#define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000
|
||||
#define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001
|
||||
#define QLC_83XX_FLASH_WRDATA_DEF 0x0
|
||||
#define QLC_83XX_FLASH_READ_CTRL 0x3F
|
||||
#define QLC_83XX_FLASH_SPI_CTRL 0x4
|
||||
#define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2
|
||||
#define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5
|
||||
#define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D
|
||||
#define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
|
||||
#define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F
|
||||
#define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D
|
||||
#define QLC_83xx_FLASH_MAX_WAIT_USEC 100
|
||||
#define QLC_83XX_FLASH_LOCK_TIMEOUT 10000
|
||||
|
||||
/* Additional registers in 83xx */
|
||||
enum qlc_83xx_ext_regs {
|
||||
QLCNIC_GLOBAL_RESET = 0,
|
||||
|
|
@ -253,4 +293,14 @@ void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
|
|||
void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
|
||||
void qlcnic_83xx_idc_aen_work(struct work_struct *);
|
||||
void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
|
||||
|
||||
int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
|
||||
int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
|
||||
int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
|
||||
int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
|
||||
void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
|
||||
int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
|
||||
int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue