[MIPS] i8253 PIT clocksource and clockevent drivers
Derived from the i386 variant with a few x86 complexities chopped off. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
87b2335d6e
commit
d865bea4da
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@ -65,6 +65,7 @@ config MIPS_COBALT
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bool "Cobalt Server"
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select I8253
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select I8259
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select IRQ_CPU
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select IRQ_GT641XX
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@ -112,6 +113,7 @@ config MACH_JAZZ
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select ARCH_MAY_HAVE_PC_FDC
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select GENERIC_ISA_DMA
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select IRQ_CPU
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select I8253
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select I8259
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select ISA
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select PCSPEAKER
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@ -201,6 +203,7 @@ config MIPS_MALTA
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select GENERIC_ISA_DMA
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select IRQ_CPU
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select HW_HAS_PCI
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select I8253
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select I8259
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select MIPS_BOARDS_GEN
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select MIPS_BONITO64
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@ -334,6 +337,7 @@ config QEMU
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select DMA_COHERENT
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select GENERIC_ISA_DMA
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select HAVE_STD_PC_SERIAL_PORT
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select I8253
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select I8259
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select IRQ_CPU
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select ISA
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@ -362,6 +366,7 @@ config SGI_IP22
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select BOOT_ELF32
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select DMA_NONCOHERENT
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select HW_HAS_EISA
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select I8253
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select IP22_CPU_SCACHE
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select IRQ_CPU
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select GENERIC_ISA_DMA_SUPPORT_BROKEN
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@ -534,6 +539,7 @@ config SNI_RM
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select HW_HAS_EISA
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select HW_HAS_PCI
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select IRQ_CPU
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select I8253
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select I8259
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select ISA
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select PCSPEAKER
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@ -1893,6 +1899,9 @@ config MMU
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bool
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default y
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config I8253
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bool
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config PCSPEAKER
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bool
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@ -15,6 +15,7 @@
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/i8253.h>
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#include <asm/io.h>
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#include <asm/reboot.h>
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#include <asm/gt64120.h>
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@ -84,6 +85,11 @@ static struct resource cobalt_reserved_resources[] = {
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},
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};
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void __init plat_time_init(void)
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{
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setup_pit_timer();
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}
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void __init plat_mem_setup(void)
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{
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int i;
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@ -25,6 +25,7 @@
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#include <linux/serial_8250.h>
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#include <asm/bootinfo.h>
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#include <asm/i8253.h>
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#include <asm/irq.h>
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#include <asm/jazz.h>
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#include <asm/jazzdma.h>
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@ -63,6 +64,11 @@ static struct resource jazz_io_resources[] = {
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}
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};
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void __init plat_time_init(void)
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{
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setup_pit_timer();
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}
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void __init plat_mem_setup(void)
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{
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int i;
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@ -65,6 +65,7 @@ obj-$(CONFIG_PROC_FS) += proc.o
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obj-$(CONFIG_64BIT) += cpu-bugs64.o
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obj-$(CONFIG_I8253) += i8253.o
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obj-$(CONFIG_PCSPEAKER) += pcspeaker.o
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obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
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@ -0,0 +1,213 @@
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/*
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* i8253.c 8253/PIT functions
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*
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*/
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <asm/delay.h>
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#include <asm/i8253.h>
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#include <asm/io.h>
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static DEFINE_SPINLOCK(i8253_lock);
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/*
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* Initialize the PIT timer.
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*
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* This is also called after resume to bring the PIT into operation again.
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*/
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static void init_pit_timer(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8253_lock, flags);
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* binary, mode 2, LSB/MSB, ch 0 */
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outb_p(0x34, PIT_MODE);
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outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
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outb(LATCH >> 8 , PIT_CH0); /* MSB */
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
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evt->mode == CLOCK_EVT_MODE_ONESHOT) {
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outb_p(0x30, PIT_MODE);
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outb_p(0, PIT_CH0);
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outb_p(0, PIT_CH0);
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}
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* One shot setup */
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outb_p(0x38, PIT_MODE);
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break;
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case CLOCK_EVT_MODE_RESUME:
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/* Nothing to do here */
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break;
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}
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spin_unlock_irqrestore(&i8253_lock, flags);
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}
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/*
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* Program the next event in oneshot mode
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*
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* Delta is given in PIT ticks
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*/
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static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8253_lock, flags);
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outb_p(delta & 0xff , PIT_CH0); /* LSB */
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outb(delta >> 8 , PIT_CH0); /* MSB */
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spin_unlock_irqrestore(&i8253_lock, flags);
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return 0;
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}
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/*
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* On UP the PIT can serve all of the possible timer functions. On SMP systems
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* it can be solely used for the global tick.
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*
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* The profiling and update capabilites are switched off once the local apic is
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* registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
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* !using_apic_timer decisions in do_timer_interrupt_hook()
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*/
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struct clock_event_device pit_clockevent = {
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.name = "pit",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = init_pit_timer,
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.set_next_event = pit_next_event,
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.shift = 32,
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.irq = 0,
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};
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irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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pit_clockevent.event_handler(&pit_clockevent);
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return IRQ_HANDLED;
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}
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static struct irqaction irq0 = {
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_NOBALANCING,
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.mask = CPU_MASK_NONE,
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.name = "timer"
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};
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/*
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* Initialize the conversion factor and the min/max deltas of the clock event
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* structure and register the clock event source with the framework.
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*/
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void __init setup_pit_timer(void)
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{
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/*
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* Start pit with the boot cpu mask and make it global after the
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* IO_APIC has been initialized.
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*/
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pit_clockevent.cpumask = cpumask_of_cpu(0);
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pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
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pit_clockevent.max_delta_ns =
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clockevent_delta2ns(0x7FFF, &pit_clockevent);
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pit_clockevent.min_delta_ns =
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clockevent_delta2ns(0xF, &pit_clockevent);
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clockevents_register_device(&pit_clockevent);
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irq0.mask = cpumask_of_cpu(0);
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setup_irq(0, &irq0);
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}
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/*
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* Since the PIT overflows every tick, its not very useful
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* to just read by itself. So use jiffies to emulate a free
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* running counter:
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*/
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static cycle_t pit_read(void)
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{
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unsigned long flags;
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int count;
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u32 jifs;
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static int old_count;
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static u32 old_jifs;
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spin_lock_irqsave(&i8253_lock, flags);
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/*
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* Although our caller may have the read side of xtime_lock,
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* this is now a seqlock, and we are cheating in this routine
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* by having side effects on state that we cannot undo if
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* there is a collision on the seqlock and our caller has to
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* retry. (Namely, old_jifs and old_count.) So we must treat
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* jiffies as volatile despite the lock. We read jiffies
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* before latching the timer count to guarantee that although
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* the jiffies value might be older than the count (that is,
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* the counter may underflow between the last point where
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* jiffies was incremented and the point where we latch the
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* count), it cannot be newer.
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*/
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jifs = jiffies;
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outb_p(0x00, PIT_MODE); /* latch the count ASAP */
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count = inb_p(PIT_CH0); /* read the latched count */
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count |= inb_p(PIT_CH0) << 8;
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/* VIA686a test code... reset the latch if count > max + 1 */
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if (count > LATCH) {
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outb_p(0x34, PIT_MODE);
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outb_p(LATCH & 0xff, PIT_CH0);
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outb(LATCH >> 8, PIT_CH0);
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count = LATCH - 1;
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}
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/*
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* It's possible for count to appear to go the wrong way for a
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* couple of reasons:
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*
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* 1. The timer counter underflows, but we haven't handled the
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* resulting interrupt and incremented jiffies yet.
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* 2. Hardware problem with the timer, not giving us continuous time,
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* the counter does small "jumps" upwards on some Pentium systems,
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* (see c't 95/10 page 335 for Neptun bug.)
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*
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* Previous attempts to handle these cases intelligently were
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* buggy, so we just do the simple thing now.
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*/
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if (count > old_count && jifs == old_jifs) {
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count = old_count;
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}
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old_count = count;
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old_jifs = jifs;
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spin_unlock_irqrestore(&i8253_lock, flags);
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count = (LATCH - 1) - count;
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return (cycle_t)(jifs * LATCH) + count;
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}
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static struct clocksource clocksource_pit = {
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.name = "pit",
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.rating = 110,
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.read = pit_read,
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.mask = CLOCKSOURCE_MASK(32),
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.mult = 0,
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.shift = 20,
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};
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static int __init init_pit_clocksource(void)
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{
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if (num_possible_cpus() > 1) /* PIT does not scale! */
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return 0;
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clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
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return clocksource_register(&clocksource_pit);
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}
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arch_initcall(init_pit_clocksource);
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@ -31,6 +31,7 @@
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/hardirq.h>
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#include <asm/i8253.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <asm/cpu.h>
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@ -141,6 +142,9 @@ void __init plat_time_init(void)
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cpu_khz = est_freq / 1000;
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mips_scroll_message();
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#ifdef CONFIG_I8253 /* Only Malta has a PIT */
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setup_pit_timer();
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#endif
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}
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//static irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
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@ -1,4 +1,6 @@
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#include <linux/init.h>
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#include <asm/i8253.h>
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#include <asm/io.h>
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#include <asm/time.h>
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@ -11,12 +13,9 @@ const char *get_system_type(void)
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return "Qemu";
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}
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void __init plat_timer_setup(struct irqaction *irq)
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void __init plat_time_init(void)
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{
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/* set the clock to 100 Hz */
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outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
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outb_p(LATCH & 0xff , 0x40); /* LSB */
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outb(LATCH >> 8 , 0x40); /* MSB */
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setup_pit_timer();
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}
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void __init plat_mem_setup(void)
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@ -20,6 +20,7 @@
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#include <asm/cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/i8253.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/time.h>
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@ -172,6 +173,9 @@ __init void plat_time_init(void)
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(int) (r4k_tick % (500000 / HZ)));
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mips_hpt_frequency = r4k_tick * HZ;
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if (ip22_is_fullhouse())
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setup_pit_timer();
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}
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/* Generic SGI handler for (spurious) 8254 interrupts */
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@ -2,6 +2,7 @@
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <asm/i8253.h>
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#include <asm/sni.h>
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#include <asm/time.h>
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#include <asm-generic/rtc.h>
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@ -116,6 +117,8 @@ void __init plat_time_init(void)
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(int) (r4k_tick % (500000 / HZ)));
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mips_hpt_frequency = r4k_tick * HZ;
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setup_pit_timer();
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}
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/*
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@ -0,0 +1,30 @@
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/*
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* Machine specific IO port address definition for generic.
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* Written by Osamu Tomita <tomita@cinet.co.jp>
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*/
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#ifndef _MACH_IO_PORTS_H
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#define _MACH_IO_PORTS_H
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/* i8253A PIT registers */
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#define PIT_MODE 0x43
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#define PIT_CH0 0x40
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#define PIT_CH2 0x42
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/* i8259A PIC registers */
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#define PIC_MASTER_CMD 0x20
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#define PIC_MASTER_IMR 0x21
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#define PIC_MASTER_ISR PIC_MASTER_CMD
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#define PIC_MASTER_POLL PIC_MASTER_ISR
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#define PIC_MASTER_OCW3 PIC_MASTER_ISR
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#define PIC_SLAVE_CMD 0xa0
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#define PIC_SLAVE_IMR 0xa1
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/* i8259A PIC related value */
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#define PIC_CASCADE_IR 2
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#define MASTER_ICW4_DEFAULT 0x01
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#define SLAVE_ICW4_DEFAULT 0x01
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#define PIC_ICW4_AEOI 2
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extern void setup_pit_timer(void);
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#endif /* !_MACH_IO_PORTS_H */
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