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dt-bindings: IDU-intc: Add support for edge-triggered interrupts 

This updates the documentation for supporting an optional extra interrupt
cell to specify edge vs level triggered.

Signed-off-by: Mischa Jonker <mischa.jonker@synopsys.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Mischa Jonker 2019-07-24 14:04:36 +02:00 committed by Vineet Gupta
parent 01449985e6
commit d85f6b93a7
1 changed files with 13 additions and 4 deletions
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17
Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
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@ -8,11 +8,20 @@ Properties:
- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1>.
- #interrupt-cells: Must be <1> or <2>.
Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
of the particular interrupt line of IDU corresponds to the line N+24 of the
core interrupt controller.
Value of the first cell specifies the "common" IRQ from peripheral to IDU.
Number N of the particular interrupt line of IDU corresponds to the line N+24
of the core interrupt controller.
The (optional) second cell specifies any of the following flags:
- bits[3:0] trigger type and level flags
1 = low-to-high edge triggered
2 = NOT SUPPORTED (high-to-low edge triggered)
4 = active high level-sensitive <<< DEFAULT
8 = NOT SUPPORTED (active low level-sensitive)
When no second cell is specified, the interrupt is assumed to be level
sensitive.
The interrupt controller is accessed via the special ARC AUX register
interface, hence "reg" property is not specified.