clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock. As such we need to be able to describe this relationship in the device tree. Export the PLL_PERIPH0 clock so we can reference it in the PRCM node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -31,7 +31,9 @@
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#define CLK_PLL_VIDEO0_2X 8
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#define CLK_PLL_VE 9
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#define CLK_PLL_DDR0 10
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#define CLK_PLL_PERIPH0 11
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/* PLL_PERIPH0 exported for PRCM */
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#define CLK_PLL_PERIPH0_2X 12
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#define CLK_PLL_PERIPH1 13
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#define CLK_PLL_PERIPH1_2X 14
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@ -43,6 +43,8 @@
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#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
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#define _DT_BINDINGS_CLK_SUN50I_A64_H_
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#define CLK_PLL_PERIPH0 11
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#define CLK_BUS_MIPI_DSI 28
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#define CLK_BUS_CE 29
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#define CLK_BUS_DMA 30
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