[SCSI] qla2xxx: Make the logging functions verify their arguments and fixed the current broken uses as appropriate.
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Saurav Kashyap <saurav.kashyap@qlogic.com> Signed-off-by: Chad Dupuis <chad.dupuis@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
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086b3e8a39
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@ -667,7 +667,7 @@ qla2x00_sysfs_write_edc(struct file *filp, struct kobject *kobj,
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dev, adr, len, opt);
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dev, adr, len, opt);
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if (rval != QLA_SUCCESS) {
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if (rval != QLA_SUCCESS) {
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ql_log(ql_log_warn, vha, 0x7074,
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ql_log(ql_log_warn, vha, 0x7074,
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"Unable to write EDC (%x) %02x:%04x:%02x:%02hhx\n",
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"Unable to write EDC (%x) %02x:%04x:%02x:%02x:%02hhx\n",
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rval, dev, adr, opt, len, buf[8]);
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rval, dev, adr, opt, len, buf[8]);
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return -EIO;
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return -EIO;
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}
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}
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@ -724,7 +724,7 @@ qla2x00_sysfs_write_edc_status(struct file *filp, struct kobject *kobj,
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dev, adr, len, opt);
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dev, adr, len, opt);
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if (rval != QLA_SUCCESS) {
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if (rval != QLA_SUCCESS) {
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ql_log(ql_log_info, vha, 0x7075,
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ql_log(ql_log_info, vha, 0x7075,
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"Unable to write EDC status (%x) %02x:%04x:%02x.\n",
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"Unable to write EDC status (%x) %02x:%04x:%02x:%02x.\n",
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rval, dev, adr, opt, len);
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rval, dev, adr, opt, len);
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return -EIO;
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return -EIO;
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}
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}
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@ -244,14 +244,14 @@ struct qla2xxx_fw_dump {
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extern int ql_errlev;
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extern int ql_errlev;
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void
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void __attribute__((format (printf, 4, 5)))
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ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
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ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
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void
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void __attribute__((format (printf, 4, 5)))
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ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
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ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
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void
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void __attribute__((format (printf, 4, 5)))
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ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
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ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
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void
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void __attribute__((format (printf, 4, 5)))
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ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
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ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
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/* Debug Levels */
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/* Debug Levels */
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@ -4188,7 +4188,8 @@ qla2x00_abort_isp(scsi_qla_host_t *vha)
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spin_unlock_irqrestore(&ha->vport_slock, flags);
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spin_unlock_irqrestore(&ha->vport_slock, flags);
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} else {
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} else {
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ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n");
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ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
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__func__);
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}
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}
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return(status);
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return(status);
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@ -1004,7 +1004,7 @@ qla24xx_walk_and_build_sglist(struct qla_hw_data *ha, srb_t *sp, uint32_t *dsd,
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sle_dma = sg_dma_address(sg);
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sle_dma = sg_dma_address(sg);
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ql_dbg(ql_dbg_io, vha, 0x300a,
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ql_dbg(ql_dbg_io, vha, 0x300a,
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"sg entry %d - addr=0x%x 0x%x, " "len=%d for cmd=%p.\n",
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"sg entry %d - addr=0x%x 0x%x, " "len=%d for cmd=%p.\n",
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cur_dsd, i, LSD(sle_dma), MSD(sle_dma), sg_dma_len(sg),
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i, LSD(sle_dma), MSD(sle_dma), sg_dma_len(sg),
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sp->cmd);
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sp->cmd);
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*cur_dsd++ = cpu_to_le32(LSD(sle_dma));
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*cur_dsd++ = cpu_to_le32(LSD(sle_dma));
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*cur_dsd++ = cpu_to_le32(MSD(sle_dma));
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*cur_dsd++ = cpu_to_le32(MSD(sle_dma));
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@ -298,7 +298,7 @@ qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
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return;
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return;
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ql_dbg(ql_dbg_async, vha, 0x5022,
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ql_dbg(ql_dbg_async, vha, 0x5022,
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"Inter-Driver Commucation %s -- ACK timeout=%d.\n",
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"%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
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vha->host_no, event[aen & 0xff], timeout);
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vha->host_no, event[aen & 0xff], timeout);
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rval = qla2x00_post_idc_ack_work(vha, mb);
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rval = qla2x00_post_idc_ack_work(vha, mb);
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@ -369,7 +369,7 @@ qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
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ql_dbg(ql_dbg_p3p, vha, 0xb000,
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ql_dbg(ql_dbg_p3p, vha, 0xb000,
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"%s: Written crbwin (0x%x) "
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"%s: Written crbwin (0x%x) "
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"!= Read crbwin (0x%x), off=0x%lx.\n",
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"!= Read crbwin (0x%x), off=0x%lx.\n",
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ha->crb_win, win_read, *off);
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__func__, ha->crb_win, win_read, *off);
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}
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}
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*off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
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*off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
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}
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}
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@ -409,7 +409,7 @@ qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
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}
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}
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/* strange address given */
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/* strange address given */
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ql_dbg(ql_dbg_p3p, vha, 0xb001,
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ql_dbg(ql_dbg_p3p, vha, 0xb001,
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"%x: Warning: unm_nic_pci_set_crbwindow "
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"%s: Warning: unm_nic_pci_set_crbwindow "
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"called with an unknown address(%llx).\n",
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"called with an unknown address(%llx).\n",
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QLA2XXX_DRIVER_NAME, off);
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QLA2XXX_DRIVER_NAME, off);
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return off;
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return off;
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@ -1711,12 +1711,12 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
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ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
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ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
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"nx_pci_base=%p iobase=%p "
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"nx_pci_base=%p iobase=%p "
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"max_req_queues=%d msix_count=%d.\n",
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"max_req_queues=%d msix_count=%d.\n",
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ha->nx_pcibase, ha->iobase,
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(void *)ha->nx_pcibase, ha->iobase,
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ha->max_req_queues, ha->msix_count);
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ha->max_req_queues, ha->msix_count);
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
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"nx_pci_base=%p iobase=%p "
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"nx_pci_base=%p iobase=%p "
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"max_req_queues=%d msix_count=%d.\n",
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"max_req_queues=%d msix_count=%d.\n",
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ha->nx_pcibase, ha->iobase,
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(void *)ha->nx_pcibase, ha->iobase,
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ha->max_req_queues, ha->msix_count);
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ha->max_req_queues, ha->msix_count);
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return 0;
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return 0;
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@ -1744,7 +1744,7 @@ qla82xx_pci_config(scsi_qla_host_t *vha)
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ret = pci_set_mwi(ha->pdev);
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ret = pci_set_mwi(ha->pdev);
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ha->chip_revision = ha->pdev->revision;
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ha->chip_revision = ha->pdev->revision;
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ql_dbg(ql_dbg_init, vha, 0x0043,
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ql_dbg(ql_dbg_init, vha, 0x0043,
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"Chip revision:%ld.\n",
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"Chip revision:%d.\n",
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ha->chip_revision);
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ha->chip_revision);
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return 0;
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return 0;
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}
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}
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@ -3661,8 +3661,7 @@ qla82xx_check_md_needed(scsi_qla_host_t *vha)
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qla82xx_md_prep(vha);
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qla82xx_md_prep(vha);
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} else
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} else
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ql_log(ql_log_info, vha, 0xb02e,
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ql_log(ql_log_info, vha, 0xb02e,
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"Firmware dump available to retrieve\n",
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"Firmware dump available to retrieve\n");
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vha->host_no);
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}
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}
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}
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}
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return rval;
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return rval;
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@ -4067,7 +4066,7 @@ int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
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}
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}
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}
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}
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ql_dbg(ql_dbg_p3p, vha, 0xb027,
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ql_dbg(ql_dbg_p3p, vha, 0xb027,
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"%s status=%d.\n", status);
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"%s: status=%d.\n", __func__, status);
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return status;
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return status;
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}
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}
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@ -1017,7 +1017,7 @@ __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
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eh_reset_failed:
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eh_reset_failed:
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ql_log(ql_log_info, vha, 0x800f,
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ql_log(ql_log_info, vha, 0x800f,
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"%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
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"%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
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reset_errors[err], cmd->device->id, cmd->device->lun);
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reset_errors[err], cmd->device->id, cmd->device->lun, cmd);
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return FAILED;
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return FAILED;
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}
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}
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@ -1819,7 +1819,7 @@ qla2x00_set_isp_flags(struct qla_hw_data *ha)
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else
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else
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ha->flags.port0 = 0;
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ha->flags.port0 = 0;
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
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"device_type=0x%x port=%d fw_srisc_address=%p.\n",
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"device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
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ha->device_type, ha->flags.port0, ha->fw_srisc_address);
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ha->device_type, ha->flags.port0, ha->fw_srisc_address);
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}
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}
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@ -1860,8 +1860,8 @@ qla2x00_iospace_config(struct qla_hw_data *ha)
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}
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}
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ha->pio_address = pio;
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ha->pio_address = pio;
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
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"PIO address=%p.\n",
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"PIO address=%llu.\n",
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ha->pio_address);
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(unsigned long long)ha->pio_address);
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skip_pio:
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skip_pio:
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/* Use MMIO operations for all accesses. */
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/* Use MMIO operations for all accesses. */
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@ -2227,7 +2227,7 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
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ql_dbg(ql_dbg_init, base_vha, 0x0033,
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ql_dbg(ql_dbg_init, base_vha, 0x0033,
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"max_id=%d this_id=%d "
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"max_id=%d this_id=%d "
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"cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
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"cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
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"max_lun=%d transportt=%p, vendor_id=%d.\n", host->max_id,
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"max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
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host->this_id, host->cmd_per_lun, host->unique_id,
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host->this_id, host->cmd_per_lun, host->unique_id,
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host->max_cmd_len, host->max_channel, host->max_lun,
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host->max_cmd_len, host->max_channel, host->max_lun,
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host->transportt, sht->vendor_id);
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host->transportt, sht->vendor_id);
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@ -2833,7 +2833,7 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
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if (!ha->sns_cmd)
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if (!ha->sns_cmd)
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goto fail_dma_pool;
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goto fail_dma_pool;
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
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"sns_cmd.\n", ha->sns_cmd);
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"sns_cmd: %p.\n", ha->sns_cmd);
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} else {
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} else {
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/* Get consistent memory allocated for MS IOCB */
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/* Get consistent memory allocated for MS IOCB */
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ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
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ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
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@ -904,8 +904,9 @@ no_flash_data:
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}
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}
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done:
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done:
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ql_dbg(ql_dbg_init, vha, 0x004d,
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ql_dbg(ql_dbg_init, vha, 0x004d,
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"FDT[%x]: (0x%x/0x%x) erase=0x%x "
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"FDT[%s]: (0x%x/0x%x) erase=0x%x "
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"pr=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
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"pr=%x wrtd=0x%x blk=0x%x.\n",
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loc, mid, fid,
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ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
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ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
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ha->fdt_wrt_disable, ha->fdt_block_size);
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ha->fdt_wrt_disable, ha->fdt_block_size);
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