[SPARC64]: Detect sun4v early in boot process.
We look for "SUNW,sun4v" in the 'compatible' property of the root OBP device tree node. Protect every %ver register access, to make sure it is not touched on sun4v, as %ver is hyperprivileged there. Lock kernel TLB entries using hypervisor calls instead of calls into OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
1d2f1f90a1
commit
d82ace7dc4
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@ -71,6 +71,12 @@ void __init cpu_probe(void)
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unsigned long ver, fpu_vers, manuf, impl, fprs;
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int i;
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if (tlb_type == hypervisor) {
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sparc_cpu_type = "UltraSparc T1 (Niagara)";
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sparc_fpu_type = "UltraSparc T1 integrated FPU";
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return;
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}
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fprs = fprs_read();
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fprs_write(FPRS_FEF);
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__asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
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@ -95,12 +95,17 @@ sparc64_boot:
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wrpr %g1, 0x0, %pstate
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ba,a,pt %xcc, 1f
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.globl prom_finddev_name, prom_chosen_path
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.globl prom_getprop_name, prom_mmu_name
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.globl prom_callmethod_name, prom_translate_name
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.globl prom_finddev_name, prom_chosen_path, prom_root_node
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.globl prom_getprop_name, prom_mmu_name, prom_peer_name
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.globl prom_callmethod_name, prom_translate_name, prom_root_compatible
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.globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
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.globl prom_boot_mapped_pc, prom_boot_mapping_mode
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.globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
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.globl is_sun4v
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prom_peer_name:
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.asciz "peer"
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prom_compatible_name:
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.asciz "compatible"
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prom_finddev_name:
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.asciz "finddevice"
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prom_chosen_path:
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@ -117,7 +122,13 @@ prom_map_name:
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.asciz "map"
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prom_unmap_name:
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.asciz "unmap"
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prom_sun4v_name:
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.asciz "SUNW,sun4v"
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.align 4
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prom_root_compatible:
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.skip 64
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prom_root_node:
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.word 0
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prom_mmu_ihandle_cache:
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.word 0
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prom_boot_mapped_pc:
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@ -129,8 +140,54 @@ prom_boot_mapping_phys_high:
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.xword 0
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prom_boot_mapping_phys_low:
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.xword 0
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is_sun4v:
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.word 0
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1:
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rd %pc, %l0
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mov (1b - prom_peer_name), %l1
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sub %l0, %l1, %l1
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mov 0, %l2
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/* prom_root_node = prom_peer(0) */
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stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
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mov 1, %l3
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stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
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stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
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stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
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stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
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call %l7
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add %sp, (2047 + 128), %o0 ! argument array
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ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
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mov (1b - prom_root_node), %l1
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sub %l0, %l1, %l1
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stw %l4, [%l1]
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mov (1b - prom_getprop_name), %l1
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mov (1b - prom_compatible_name), %l2
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mov (1b - prom_root_compatible), %l5
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sub %l0, %l1, %l1
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sub %l0, %l2, %l2
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sub %l0, %l5, %l5
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/* prom_getproperty(prom_root_node, "compatible",
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* &prom_root_compatible, 64)
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*/
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stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
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mov 4, %l3
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stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
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mov 1, %l3
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stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
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stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
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stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
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stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
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mov 64, %l3
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stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
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stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
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call %l7
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add %sp, (2047 + 128), %o0 ! argument array
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mov (1b - prom_finddev_name), %l1
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mov (1b - prom_chosen_path), %l2
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mov (1b - prom_boot_mapped_pc), %l3
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@ -239,6 +296,27 @@ prom_boot_mapping_phys_low:
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add %sp, (192 + 128), %sp
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sparc64_boot_after_remap:
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sethi %hi(prom_root_compatible), %g1
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or %g1, %lo(prom_root_compatible), %g1
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sethi %hi(prom_sun4v_name), %g7
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or %g7, %lo(prom_sun4v_name), %g7
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mov 10, %g3
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1: ldub [%g7], %g2
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ldub [%g1], %g4
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cmp %g2, %g4
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bne,pn %icc, 2f
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add %g7, 1, %g7
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subcc %g3, 1, %g3
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bne,pt %xcc, 1b
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add %g1, 1, %g1
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sethi %hi(is_sun4v), %g1
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or %g1, %lo(is_sun4v), %g1
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mov 1, %g7
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stw %g7, [%g1]
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2:
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BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
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BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
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ba,pt %xcc, spitfire_boot
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@ -323,14 +401,12 @@ sun4u_init:
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membar #Sync
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BRANCH_IF_SUN4V(g1, niagara_tlb_fixup)
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BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
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ba,pt %xcc, spitfire_tlb_fixup
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nop
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/* XXX Nothing branches to here yet, when %ver register indicates
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* XXX Niagara we should do this.
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*/
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niagara_tlb_fixup:
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mov 3, %g2 /* Set TLB type to hypervisor. */
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sethi %hi(tlb_type), %g1
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@ -346,6 +422,9 @@ niagara_tlb_fixup:
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call hypervisor_patch_cachetlbops
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nop
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ba,pt %xcc, tlb_fixup_done
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nop
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cheetah_tlb_fixup:
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mov 2, %g2 /* Set TLB type to cheetah+. */
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
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@ -464,6 +543,7 @@ setup_trap_table:
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sllx %o2, 32, %o2
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wr %o2, 0, %tick_cmpr
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BRANCH_IF_SUN4V(o2, 1f)
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BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
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ba,pt %xcc, 2f
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@ -150,6 +150,9 @@ void enable_irq(unsigned int irq)
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preempt_disable();
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if (tlb_type == hypervisor) {
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/* XXX SUN4V: implement me... XXX */
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} else {
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if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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unsigned long ver;
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@ -178,7 +181,8 @@ void enable_irq(unsigned int irq)
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tid = ((tid & UPA_CONFIG_MID) << 9);
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tid &= IMAP_TID_UPA;
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} else {
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tid = (starfire_translate(imap, smp_processor_id()) << 26);
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tid = (starfire_translate(imap,
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smp_processor_id()) << 26);
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tid &= IMAP_TID_UPA;
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}
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@ -188,9 +192,11 @@ void enable_irq(unsigned int irq)
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* However for Graphics and UPA Slave devices the full
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* IMAP_INR field can be set by the programmer here.
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*
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* Things like FFB can now be handled via the new IRQ mechanism.
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* Things like FFB can now be handled via the new IRQ
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* mechanism.
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*/
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upa_writel(tid | IMAP_VALID, imap);
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}
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preempt_enable();
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}
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@ -504,9 +504,12 @@ static void __init per_cpu_patch(void)
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if (tlb_type == spitfire && !this_is_starfire)
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return;
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is_jbus = 0;
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if (tlb_type != hypervisor) {
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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is_jbus = ((ver >> 32) == __JALAPENO_ID ||
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(ver >> 32) == __SERRANO_ID);
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}
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p = &__cpuid_patch;
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while (p < &__cpuid_patch_end) {
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@ -16,6 +16,7 @@
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#include <asm/processor.h>
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#include <asm/thread_info.h>
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#include <asm/mmu.h>
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#include <asm/hypervisor.h>
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.data
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.align 8
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@ -34,6 +35,7 @@ dtlb_load:
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sparc64_cpu_startup:
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flushw
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BRANCH_IF_SUN4V(g1, niagara_startup)
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BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
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@ -70,7 +72,9 @@ cheetah_generic_startup:
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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/* fallthru */
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niagara_startup:
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/* Disable STICK_INT interrupts. */
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sethi %hi(0x80000000), %g5
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sllx %g5, 32, %g5
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@ -91,6 +95,8 @@ startup_continue:
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sllx %g2, 32, %g2
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wr %g2, 0, %tick_cmpr
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BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
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/* Call OBP by hand to lock KERNBASE into i/d tlbs.
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* We lock 2 consequetive entries if we are 'bigkernel'.
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*/
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@ -142,8 +148,7 @@ startup_continue:
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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cmp %g2, 0
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be,pt %icc, do_dtlb
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brz,pt %g2, do_dtlb
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nop
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sethi %hi(call_method), %g2
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@ -214,8 +219,7 @@ do_dtlb:
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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cmp %g2, 0
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be,pt %icc, do_unlock
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brz,pt %g2, do_unlock
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nop
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sethi %hi(call_method), %g2
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@ -257,6 +261,52 @@ do_unlock:
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stb %g0, [%g2 + %lo(prom_entry_lock)]
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membar #StoreStore | #StoreLoad
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ba,pt %xcc, after_lock_tlb
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nop
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niagara_lock_tlb:
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o0
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sethi %hi(KERNBASE), %o1
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clr %o2
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sethi %hi(kern_locked_tte_data), %o3
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ldx [%o3 + %lo(kern_locked_tte_data)], %o3
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mov HV_MMU_IMMU, %o4
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ta HV_FAST_TRAP
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o0
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sethi %hi(KERNBASE), %o1
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clr %o2
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sethi %hi(kern_locked_tte_data), %o3
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ldx [%o3 + %lo(kern_locked_tte_data)], %o3
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mov HV_MMU_DMMU, %o4
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ta HV_FAST_TRAP
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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brz,pt %g2, after_lock_tlb
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nop
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o0
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sethi %hi(KERNBASE + 0x400000), %o1
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clr %o2
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sethi %hi(kern_locked_tte_data), %o3
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ldx [%o3 + %lo(kern_locked_tte_data)], %o3
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sethi %hi(0x400000), %o4
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add %o3, %o4, %o3
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mov HV_MMU_IMMU, %o4
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ta HV_FAST_TRAP
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o0
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sethi %hi(KERNBASE + 0x400000), %o1
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clr %o2
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sethi %hi(kern_locked_tte_data), %o3
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ldx [%o3 + %lo(kern_locked_tte_data)], %o3
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sethi %hi(0x400000), %o4
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add %o3, %o4, %o3
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mov HV_MMU_DMMU, %o4
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ta HV_FAST_TRAP
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after_lock_tlb:
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mov %l1, %sp
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flushw
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@ -346,6 +346,9 @@ static int __init us2e_freq_init(void)
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unsigned long manuf, impl, ver;
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int ret;
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if (tlb_type != spitfire)
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return -ENODEV;
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__asm__("rdpr %%ver, %0" : "=r" (ver));
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manuf = ((ver >> 48) & 0xffff);
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impl = ((ver >> 32) & 0xffff);
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@ -203,6 +203,9 @@ static int __init us3_freq_init(void)
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unsigned long manuf, impl, ver;
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int ret;
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if (tlb_type != cheetah && tlb_type != cheetah_plus)
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return -ENODEV;
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__asm__("rdpr %%ver, %0" : "=r" (ver));
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manuf = ((ver >> 48) & 0xffff);
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impl = ((ver >> 32) & 0xffff);
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@ -514,6 +514,29 @@ static void __init read_obp_translations(void)
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}
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}
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static void __init hypervisor_tlb_lock(unsigned long vaddr,
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unsigned long pte,
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unsigned long mmu)
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{
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register unsigned long func asm("%o0");
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register unsigned long arg0 asm("%o1");
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register unsigned long arg1 asm("%o2");
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register unsigned long arg2 asm("%o3");
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register unsigned long arg3 asm("%o4");
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func = HV_FAST_MMU_MAP_PERM_ADDR;
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arg0 = vaddr;
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arg1 = 0;
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arg2 = pte;
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arg3 = mmu;
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__asm__ __volatile__("ta 0x80"
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: "=&r" (func), "=&r" (arg0),
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"=&r" (arg1), "=&r" (arg2),
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"=&r" (arg3)
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: "0" (func), "1" (arg0), "2" (arg1),
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"3" (arg2), "4" (arg3));
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}
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static void __init remap_kernel(void)
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{
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unsigned long phys_page, tte_vaddr, tte_data;
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@ -527,7 +550,17 @@ static void __init remap_kernel(void)
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kern_locked_tte_data = tte_data;
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/* Now lock us into the TLBs via OBP. */
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/* Now lock us into the TLBs via Hypervisor or OBP. */
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if (tlb_type == hypervisor) {
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hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
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hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
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if (bigkernel) {
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tte_vaddr += 0x400000;
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tte_data += 0x400000;
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hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
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hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
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}
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} else {
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prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
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prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
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if (bigkernel) {
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@ -540,6 +573,7 @@ static void __init remap_kernel(void)
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tte_vaddr + 0x400000);
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}
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sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
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}
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if (tlb_type == cheetah_plus) {
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sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
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CTX_CHEETAH_PLUS_NUC);
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@ -18,7 +18,6 @@ enum prom_major_version prom_vers;
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unsigned int prom_rev, prom_prev;
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/* The root node of the prom device tree. */
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int prom_root_node;
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int prom_stdin, prom_stdout;
|
||||
int prom_chosen_node;
|
||||
|
||||
|
|
@ -41,10 +40,6 @@ void __init prom_init(void *cif_handler, void *cif_stack)
|
|||
|
||||
prom_cif_init(cif_handler, cif_stack);
|
||||
|
||||
prom_root_node = prom_getsibling(0);
|
||||
if((prom_root_node == 0) || (prom_root_node == -1))
|
||||
prom_halt();
|
||||
|
||||
prom_chosen_node = prom_finddevice(prom_chosen_path);
|
||||
if (!prom_chosen_node || prom_chosen_node == -1)
|
||||
prom_halt();
|
||||
|
|
@ -88,6 +83,7 @@ void __init prom_init(void *cif_handler, void *cif_stack)
|
|||
prom_prev = (ints[0] << 16) | (ints[1] << 8) | ints[2];
|
||||
|
||||
printk("PROMLIB: Sun IEEE Boot Prom %s\n", buffer + bufadjust);
|
||||
printk("PROMLIB: Root node compatible: %s\n", prom_root_compatible);
|
||||
|
||||
/* Initialization successful. */
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ prom_getparent(int node)
|
|||
__inline__ int
|
||||
__prom_getsibling(int node)
|
||||
{
|
||||
return p1275_cmd ("peer", P1275_INOUT(1, 1), node);
|
||||
return p1275_cmd(prom_peer_name, P1275_INOUT(1, 1), node);
|
||||
}
|
||||
|
||||
__inline__ int
|
||||
|
|
@ -59,9 +59,12 @@ prom_getsibling(int node)
|
|||
{
|
||||
int sibnode;
|
||||
|
||||
if(node == -1) return 0;
|
||||
if (node == -1)
|
||||
return 0;
|
||||
sibnode = __prom_getsibling(node);
|
||||
if(sibnode == -1) return 0;
|
||||
if (sibnode == -1)
|
||||
return 0;
|
||||
|
||||
return sibnode;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,12 @@
|
|||
#define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
|
||||
#define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
|
||||
|
||||
#define BRANCH_IF_SUN4V(tmp1,label) \
|
||||
sethi %hi(is_sun4v), %tmp1; \
|
||||
lduw [%tmp1 + %lo(is_sun4v)], %tmp1; \
|
||||
brnz,pn %tmp1, label; \
|
||||
nop
|
||||
|
||||
#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
|
||||
rdpr %ver, %tmp1; \
|
||||
sethi %hi(__CHEETAH_ID), %tmp2; \
|
||||
|
|
|
|||
|
|
@ -39,6 +39,9 @@ extern int prom_stdin, prom_stdout;
|
|||
extern int prom_chosen_node;
|
||||
|
||||
/* Helper values and strings in arch/sparc64/kernel/head.S */
|
||||
extern const char prom_peer_name[];
|
||||
extern const char prom_compatible_name[];
|
||||
extern const char prom_root_compatible[];
|
||||
extern const char prom_finddev_name[];
|
||||
extern const char prom_chosen_path[];
|
||||
extern const char prom_getprop_name[];
|
||||
|
|
|
|||
Loading…
Reference in New Issue