intel_idle: Update support for Silvermont Core in Baytrail SOC
On some Silvermont-Core/Baytrail-SOC systems, C1E latency is higher than original specifications. Although C1E is still enumerated in CPUID.MWAIT.EDX, we delete the state from intel_idle to avoid latency impact. Under some conditions, the latency of the C6N-BYT and C6S-BYT states may exceed the specified values of 40 and 140 usec, respectively. Increase those values to 300 and 500 usec; to assure that the hardware does not violate constraints that may be set by the Linux PM_QOS sub-system. Also increase the C7-BYT target residency to 4.0 ms from 1.5 ms. Signed-off-by: Len Brown <len.brown@intel.com> Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: <stable@vger.kernel.org>
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@ -217,19 +217,11 @@ static struct cpuidle_state byt_cstates[] = {
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-BYT",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 15,
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.target_residency = 30,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6N-BYT",
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.desc = "MWAIT 0x58",
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.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 40,
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.exit_latency = 300,
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.target_residency = 275,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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@ -237,7 +229,7 @@ static struct cpuidle_state byt_cstates[] = {
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.name = "C6S-BYT",
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.desc = "MWAIT 0x52",
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.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 140,
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.exit_latency = 500,
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.target_residency = 560,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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@ -246,7 +238,7 @@ static struct cpuidle_state byt_cstates[] = {
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 1200,
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.target_residency = 1500,
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.target_residency = 4000,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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