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drm/nouveau/mc: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-01-14 15:08:21 +10:00
parent 2799bba69a
commit d7e5fcd2e7
20 changed files with 192 additions and 208 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/nouveau/include/nvkm/core/os.h
View File

@ -239,5 +239,6 @@
#define nouveau_fb_tile nvkm_fb_tile #define nouveau_fb_tile nvkm_fb_tile
#define nvc0_pte_storage_type_map gf100_pte_storage_type_map #define nvc0_pte_storage_type_map gf100_pte_storage_type_map
#define nouveau_fuse nvkm_fuse #define nouveau_fuse nvkm_fuse
#define nouveau_mc nvkm_mc
#endif #endif

1
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
View File

@ -28,5 +28,4 @@ nvkm_ltc(void *obj)
extern struct nvkm_oclass *gf100_ltc_oclass; extern struct nvkm_oclass *gf100_ltc_oclass;
extern struct nvkm_oclass *gk104_ltc_oclass; extern struct nvkm_oclass *gk104_ltc_oclass;
extern struct nvkm_oclass *gm107_ltc_oclass; extern struct nvkm_oclass *gm107_ltc_oclass;
#endif #endif

39
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
View File

@ -1,31 +1,28 @@
#ifndef __NOUVEAU_MC_H__ #ifndef __NVKM_MC_H__
#define __NOUVEAU_MC_H__ #define __NVKM_MC_H__
#include <core/subdev.h> #include <core/subdev.h>
#include <core/device.h>
struct nouveau_mc { struct nvkm_mc {
struct nouveau_subdev base; struct nvkm_subdev base;
bool use_msi; bool use_msi;
unsigned int irq; unsigned int irq;
void (*unk260)(struct nouveau_mc *, u32); void (*unk260)(struct nvkm_mc *, u32);
}; };
static inline struct nouveau_mc * static inline struct nvkm_mc *
nouveau_mc(void *obj) nvkm_mc(void *obj)
{ {
return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MC); return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MC);
} }
extern struct nouveau_oclass *nv04_mc_oclass; extern struct nvkm_oclass *nv04_mc_oclass;
extern struct nouveau_oclass *nv40_mc_oclass; extern struct nvkm_oclass *nv40_mc_oclass;
extern struct nouveau_oclass *nv44_mc_oclass; extern struct nvkm_oclass *nv44_mc_oclass;
extern struct nouveau_oclass *nv4c_mc_oclass; extern struct nvkm_oclass *nv4c_mc_oclass;
extern struct nouveau_oclass *nv50_mc_oclass; extern struct nvkm_oclass *nv50_mc_oclass;
extern struct nouveau_oclass *nv94_mc_oclass; extern struct nvkm_oclass *g94_mc_oclass;
extern struct nouveau_oclass *nv98_mc_oclass; extern struct nvkm_oclass *g98_mc_oclass;
extern struct nouveau_oclass *nvc0_mc_oclass; extern struct nvkm_oclass *gf100_mc_oclass;
extern struct nouveau_oclass *nvc3_mc_oclass; extern struct nvkm_oclass *gf106_mc_oclass;
extern struct nouveau_oclass *gk20a_mc_oclass; extern struct nvkm_oclass *gk20a_mc_oclass;
#endif #endif

20
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -184,7 +184,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -213,7 +213,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -242,7 +242,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -271,7 +271,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
@ -300,7 +300,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
@ -329,7 +329,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
@ -358,7 +358,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@ -389,7 +389,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@ -419,7 +419,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
@ -449,7 +449,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;

18
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View File

@ -69,7 +69,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -102,7 +102,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -135,7 +135,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -167,7 +167,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -200,7 +200,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -232,7 +232,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -264,7 +264,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -297,7 +297,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
@ -329,7 +329,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;

10
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View File

@ -69,7 +69,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -103,7 +103,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -137,7 +137,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -193,7 +193,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
@ -227,7 +227,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;

8
drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
View File

@ -4,8 +4,8 @@ nvkm-y += nvkm/subdev/mc/nv40.o
nvkm-y += nvkm/subdev/mc/nv44.o nvkm-y += nvkm/subdev/mc/nv44.o
nvkm-y += nvkm/subdev/mc/nv4c.o nvkm-y += nvkm/subdev/mc/nv4c.o
nvkm-y += nvkm/subdev/mc/nv50.o nvkm-y += nvkm/subdev/mc/nv50.o
nvkm-y += nvkm/subdev/mc/nv94.o nvkm-y += nvkm/subdev/mc/g94.o
nvkm-y += nvkm/subdev/mc/nv98.o nvkm-y += nvkm/subdev/mc/g98.o
nvkm-y += nvkm/subdev/mc/nvc0.o nvkm-y += nvkm/subdev/mc/gf100.o
nvkm-y += nvkm/subdev/mc/nvc3.o nvkm-y += nvkm/subdev/mc/gf106.o
nvkm-y += nvkm/subdev/mc/gk20a.o nvkm-y += nvkm/subdev/mc/gk20a.o

69
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
View File

@ -21,20 +21,21 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "priv.h" #include "priv.h"
#include <core/device.h>
#include <core/option.h> #include <core/option.h>
static inline void static inline void
nouveau_mc_unk260(struct nouveau_mc *pmc, u32 data) nvkm_mc_unk260(struct nvkm_mc *pmc, u32 data)
{ {
const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc); const struct nvkm_mc_oclass *impl = (void *)nv_oclass(pmc);
if (impl->unk260) if (impl->unk260)
impl->unk260(pmc, data); impl->unk260(pmc, data);
} }
static inline u32 static inline u32
nouveau_mc_intr_mask(struct nouveau_mc *pmc) nvkm_mc_intr_mask(struct nvkm_mc *pmc)
{ {
u32 intr = nv_rd32(pmc, 0x000100); u32 intr = nv_rd32(pmc, 0x000100);
if (intr == 0xffffffff) /* likely fallen off the bus */ if (intr == 0xffffffff) /* likely fallen off the bus */
@ -43,25 +44,25 @@ nouveau_mc_intr_mask(struct nouveau_mc *pmc)
} }
static irqreturn_t static irqreturn_t
nouveau_mc_intr(int irq, void *arg) nvkm_mc_intr(int irq, void *arg)
{ {
struct nouveau_mc *pmc = arg; struct nvkm_mc *pmc = arg;
const struct nouveau_mc_oclass *oclass = (void *)nv_object(pmc)->oclass; const struct nvkm_mc_oclass *oclass = (void *)nv_object(pmc)->oclass;
const struct nouveau_mc_intr *map = oclass->intr; const struct nvkm_mc_intr *map = oclass->intr;
struct nouveau_subdev *unit; struct nvkm_subdev *unit;
u32 intr; u32 intr;
nv_wr32(pmc, 0x000140, 0x00000000); nv_wr32(pmc, 0x000140, 0x00000000);
nv_rd32(pmc, 0x000140); nv_rd32(pmc, 0x000140);
intr = nouveau_mc_intr_mask(pmc); intr = nvkm_mc_intr_mask(pmc);
if (pmc->use_msi) if (pmc->use_msi)
oclass->msi_rearm(pmc); oclass->msi_rearm(pmc);
if (intr) { if (intr) {
u32 stat = intr = nouveau_mc_intr_mask(pmc); u32 stat = intr = nvkm_mc_intr_mask(pmc);
while (map->stat) { while (map->stat) {
if (intr & map->stat) { if (intr & map->stat) {
unit = nouveau_subdev(pmc, map->unit); unit = nvkm_subdev(pmc, map->unit);
if (unit && unit->intr) if (unit && unit->intr)
unit->intr(unit); unit->intr(unit);
stat &= ~map->stat; stat &= ~map->stat;
@ -78,18 +79,18 @@ nouveau_mc_intr(int irq, void *arg)
} }
int int
_nouveau_mc_fini(struct nouveau_object *object, bool suspend) _nvkm_mc_fini(struct nvkm_object *object, bool suspend)
{ {
struct nouveau_mc *pmc = (void *)object; struct nvkm_mc *pmc = (void *)object;
nv_wr32(pmc, 0x000140, 0x00000000); nv_wr32(pmc, 0x000140, 0x00000000);
return nouveau_subdev_fini(&pmc->base, suspend); return nvkm_subdev_fini(&pmc->base, suspend);
} }
int int
_nouveau_mc_init(struct nouveau_object *object) _nvkm_mc_init(struct nvkm_object *object)
{ {
struct nouveau_mc *pmc = (void *)object; struct nvkm_mc *pmc = (void *)object;
int ret = nouveau_subdev_init(&pmc->base); int ret = nvkm_subdev_init(&pmc->base);
if (ret) if (ret)
return ret; return ret;
nv_wr32(pmc, 0x000140, 0x00000001); nv_wr32(pmc, 0x000140, 0x00000001);
@ -97,32 +98,32 @@ _nouveau_mc_init(struct nouveau_object *object)
} }
void void
_nouveau_mc_dtor(struct nouveau_object *object) _nvkm_mc_dtor(struct nvkm_object *object)
{ {
struct nouveau_device *device = nv_device(object); struct nvkm_device *device = nv_device(object);
struct nouveau_mc *pmc = (void *)object; struct nvkm_mc *pmc = (void *)object;
free_irq(pmc->irq, pmc); free_irq(pmc->irq, pmc);
if (pmc->use_msi) if (pmc->use_msi)
pci_disable_msi(device->pdev); pci_disable_msi(device->pdev);
nouveau_subdev_destroy(&pmc->base); nvkm_subdev_destroy(&pmc->base);
} }
int int
nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *bclass, int length, void **pobject) struct nvkm_oclass *bclass, int length, void **pobject)
{ {
const struct nouveau_mc_oclass *oclass = (void *)bclass; const struct nvkm_mc_oclass *oclass = (void *)bclass;
struct nouveau_device *device = nv_device(parent); struct nvkm_device *device = nv_device(parent);
struct nouveau_mc *pmc; struct nvkm_mc *pmc;
int ret; int ret;
ret = nouveau_subdev_create_(parent, engine, bclass, 0, "PMC", ret = nvkm_subdev_create_(parent, engine, bclass, 0, "PMC",
"master", length, pobject); "master", length, pobject);
pmc = *pobject; pmc = *pobject;
if (ret) if (ret)
return ret; return ret;
pmc->unk260 = nouveau_mc_unk260; pmc->unk260 = nvkm_mc_unk260;
if (nv_device_is_pci(device)) { if (nv_device_is_pci(device)) {
switch (device->pdev->device & 0x0ff0) { switch (device->pdev->device & 0x0ff0) {
@ -141,8 +142,8 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
} }
} }
pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", pmc->use_msi = nvkm_boolopt(device->cfgopt, "NvMSI",
pmc->use_msi); pmc->use_msi);
if (pmc->use_msi && oclass->msi_rearm) { if (pmc->use_msi && oclass->msi_rearm) {
pmc->use_msi = pci_enable_msi(device->pdev) == 0; pmc->use_msi = pci_enable_msi(device->pdev) == 0;
@ -160,9 +161,7 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
return ret; return ret;
pmc->irq = ret; pmc->irq = ret;
ret = request_irq(pmc->irq, nouveau_mc_intr, IRQF_SHARED, "nouveau", ret = request_irq(pmc->irq, nvkm_mc_intr, IRQF_SHARED, "nvkm", pmc);
pmc);
if (ret < 0) if (ret < 0)
return ret; return ret;

11
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv94.c → drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c
View File

@ -21,17 +21,16 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
struct nouveau_oclass * struct nvkm_oclass *
nv94_mc_oclass = &(struct nouveau_mc_oclass) { g94_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x94), .base.handle = NV_SUBDEV(MC, 0x94),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init, .init = nv50_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nv50_mc_intr, .intr = nv50_mc_intr,
.msi_rearm = nv40_mc_msi_rearm, .msi_rearm = nv40_mc_msi_rearm,

17
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c → drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
View File

@ -21,11 +21,10 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
static const struct nouveau_mc_intr static const struct nvkm_mc_intr
nv98_mc_intr[] = { g98_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */ { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */
{ 0x00000001, NVDEV_ENGINE_MSPPP }, { 0x00000001, NVDEV_ENGINE_MSPPP },
{ 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00000100, NVDEV_ENGINE_FIFO },
@ -45,15 +44,15 @@ nv98_mc_intr[] = {
{}, {},
}; };
struct nouveau_oclass * struct nvkm_oclass *
nv98_mc_oclass = &(struct nouveau_mc_oclass) { g98_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x98), .base.handle = NV_SUBDEV(MC, 0x98),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init, .init = nv50_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nv98_mc_intr, .intr = g98_mc_intr,
.msi_rearm = nv40_mc_msi_rearm, .msi_rearm = nv40_mc_msi_rearm,
}.base; }.base;

25
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c → drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
View File

@ -21,11 +21,10 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
const struct nouveau_mc_intr const struct nvkm_mc_intr
nvc0_mc_intr[] = { gf100_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */
{ 0x00000001, NVDEV_ENGINE_MSPPP }, { 0x00000001, NVDEV_ENGINE_MSPPP },
{ 0x00000020, NVDEV_ENGINE_CE0 }, { 0x00000020, NVDEV_ENGINE_CE0 },
@ -50,28 +49,28 @@ nvc0_mc_intr[] = {
}; };
static void static void
nvc0_mc_msi_rearm(struct nouveau_mc *pmc) gf100_mc_msi_rearm(struct nvkm_mc *pmc)
{ {
struct nv04_mc_priv *priv = (void *)pmc; struct nv04_mc_priv *priv = (void *)pmc;
nv_wr32(priv, 0x088704, 0x00000000); nv_wr32(priv, 0x088704, 0x00000000);
} }
void void
nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data) gf100_mc_unk260(struct nvkm_mc *pmc, u32 data)
{ {
nv_wr32(pmc, 0x000260, data); nv_wr32(pmc, 0x000260, data);
} }
struct nouveau_oclass * struct nvkm_oclass *
nvc0_mc_oclass = &(struct nouveau_mc_oclass) { gf100_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xc0), .base.handle = NV_SUBDEV(MC, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init, .init = nv50_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nvc0_mc_intr, .intr = gf100_mc_intr,
.msi_rearm = nvc0_mc_msi_rearm, .msi_rearm = gf100_mc_msi_rearm,
.unk260 = nvc0_mc_unk260, .unk260 = gf100_mc_unk260,
}.base; }.base;

15
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc3.c → drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c
View File

@ -21,19 +21,18 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
struct nouveau_oclass * struct nvkm_oclass *
nvc3_mc_oclass = &(struct nouveau_mc_oclass) { gf106_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xc3), .base.handle = NV_SUBDEV(MC, 0xc3),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init, .init = nv50_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nvc0_mc_intr, .intr = gf100_mc_intr,
.msi_rearm = nv40_mc_msi_rearm, .msi_rearm = nv40_mc_msi_rearm,
.unk260 = nvc0_mc_unk260, .unk260 = gf100_mc_unk260,
}.base; }.base;

13
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
View File

@ -21,18 +21,17 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
struct nouveau_oclass * struct nvkm_oclass *
gk20a_mc_oclass = &(struct nouveau_mc_oclass) { gk20a_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xea), .base.handle = NV_SUBDEV(MC, 0xea),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init, .init = nv50_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nvc0_mc_intr, .intr = gf100_mc_intr,
.msi_rearm = nv40_mc_msi_rearm, .msi_rearm = nv40_mc_msi_rearm,
}.base; }.base;

25
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
View File

@ -21,10 +21,9 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
const struct nouveau_mc_intr const struct nvkm_mc_intr
nv04_mc_intr[] = { nv04_mc_intr[] = {
{ 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */ { 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */
{ 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00000100, NVDEV_ENGINE_FIFO },
@ -40,25 +39,25 @@ nv04_mc_intr[] = {
}; };
int int
nv04_mc_init(struct nouveau_object *object) nv04_mc_init(struct nvkm_object *object)
{ {
struct nv04_mc_priv *priv = (void *)object; struct nv04_mc_priv *priv = (void *)object;
nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */ nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */
nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */ nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */
return nouveau_mc_init(&priv->base); return nvkm_mc_init(&priv->base);
} }
int int
nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nv04_mc_priv *priv; struct nv04_mc_priv *priv;
int ret; int ret;
ret = nouveau_mc_create(parent, engine, oclass, &priv); ret = nvkm_mc_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
@ -66,14 +65,14 @@ nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass * struct nvkm_oclass *
nv04_mc_oclass = &(struct nouveau_mc_oclass) { nv04_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x04), .base.handle = NV_SUBDEV(MC, 0x04),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv04_mc_init, .init = nv04_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nv04_mc_intr, .intr = nv04_mc_intr,
}.base; }.base;

24
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h
View File

@ -1,22 +1,20 @@
#ifndef __NVKM_MC_NV04_H__ #ifndef __NVKM_MC_NV04_H__
#define __NVKM_MC_NV04_H__ #define __NVKM_MC_NV04_H__
#include "priv.h" #include "priv.h"
struct nv04_mc_priv { struct nv04_mc_priv {
struct nouveau_mc base; struct nvkm_mc base;
}; };
int nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *, int nv04_mc_ctor(struct nvkm_object *, struct nvkm_object *,
struct nouveau_oclass *, void *, u32, struct nvkm_oclass *, void *, u32,
struct nouveau_object **); struct nvkm_object **);
extern const struct nouveau_mc_intr nv04_mc_intr[];
int nv04_mc_init(struct nouveau_object *);
void nv40_mc_msi_rearm(struct nouveau_mc *);
int nv44_mc_init(struct nouveau_object *object);
int nv50_mc_init(struct nouveau_object *);
extern const struct nouveau_mc_intr nv50_mc_intr[];
extern const struct nouveau_mc_intr nvc0_mc_intr[];
extern const struct nvkm_mc_intr nv04_mc_intr[];
int nv04_mc_init(struct nvkm_object *);
void nv40_mc_msi_rearm(struct nvkm_mc *);
int nv44_mc_init(struct nvkm_object *object);
int nv50_mc_init(struct nvkm_object *);
extern const struct nvkm_mc_intr nv50_mc_intr[];
extern const struct nvkm_mc_intr gf100_mc_intr[];
#endif #endif

13
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c
View File

@ -21,24 +21,23 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
void void
nv40_mc_msi_rearm(struct nouveau_mc *pmc) nv40_mc_msi_rearm(struct nvkm_mc *pmc)
{ {
struct nv04_mc_priv *priv = (void *)pmc; struct nv04_mc_priv *priv = (void *)pmc;
nv_wr08(priv, 0x088068, 0xff); nv_wr08(priv, 0x088068, 0xff);
} }
struct nouveau_oclass * struct nvkm_oclass *
nv40_mc_oclass = &(struct nouveau_mc_oclass) { nv40_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x40), .base.handle = NV_SUBDEV(MC, 0x40),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv04_mc_init, .init = nv04_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nv04_mc_intr, .intr = nv04_mc_intr,
.msi_rearm = nv40_mc_msi_rearm, .msi_rearm = nv40_mc_msi_rearm,

15
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
View File

@ -21,11 +21,10 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
int int
nv44_mc_init(struct nouveau_object *object) nv44_mc_init(struct nvkm_object *object)
{ {
struct nv04_mc_priv *priv = (void *)object; struct nv04_mc_priv *priv = (void *)object;
u32 tmp = nv_rd32(priv, 0x10020c); u32 tmp = nv_rd32(priv, 0x10020c);
@ -37,17 +36,17 @@ nv44_mc_init(struct nouveau_object *object)
nv_wr32(priv, 0x001708, 0); nv_wr32(priv, 0x001708, 0);
nv_wr32(priv, 0x00170c, tmp); nv_wr32(priv, 0x00170c, tmp);
return nouveau_mc_init(&priv->base); return nvkm_mc_init(&priv->base);
} }
struct nouveau_oclass * struct nvkm_oclass *
nv44_mc_oclass = &(struct nouveau_mc_oclass) { nv44_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x44), .base.handle = NV_SUBDEV(MC, 0x44),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv44_mc_init, .init = nv44_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nv04_mc_intr, .intr = nv04_mc_intr,
.msi_rearm = nv40_mc_msi_rearm, .msi_rearm = nv40_mc_msi_rearm,

11
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c
View File

@ -21,17 +21,16 @@
* *
* Authors: Ilia Mirkin * Authors: Ilia Mirkin
*/ */
#include "nv04.h" #include "nv04.h"
struct nouveau_oclass * struct nvkm_oclass *
nv4c_mc_oclass = &(struct nouveau_mc_oclass) { nv4c_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x4c), .base.handle = NV_SUBDEV(MC, 0x4c),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv44_mc_init, .init = nv44_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nv04_mc_intr, .intr = nv04_mc_intr,
}.base; }.base;

23
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
View File

@ -21,10 +21,11 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h" #include "nv04.h"
const struct nouveau_mc_intr #include <core/device.h>
const struct nvkm_mc_intr
nv50_mc_intr[] = { nv50_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */
{ 0x00000001, NVDEV_ENGINE_MPEG }, { 0x00000001, NVDEV_ENGINE_MPEG },
@ -43,28 +44,28 @@ nv50_mc_intr[] = {
}; };
static void static void
nv50_mc_msi_rearm(struct nouveau_mc *pmc) nv50_mc_msi_rearm(struct nvkm_mc *pmc)
{ {
struct nouveau_device *device = nv_device(pmc); struct nvkm_device *device = nv_device(pmc);
pci_write_config_byte(device->pdev, 0x68, 0xff); pci_write_config_byte(device->pdev, 0x68, 0xff);
} }
int int
nv50_mc_init(struct nouveau_object *object) nv50_mc_init(struct nvkm_object *object)
{ {
struct nv04_mc_priv *priv = (void *)object; struct nv04_mc_priv *priv = (void *)object;
nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */ nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */
return nouveau_mc_init(&priv->base); return nvkm_mc_init(&priv->base);
} }
struct nouveau_oclass * struct nvkm_oclass *
nv50_mc_oclass = &(struct nouveau_mc_oclass) { nv50_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x50), .base.handle = NV_SUBDEV(MC, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor, .ctor = nv04_mc_ctor,
.dtor = _nouveau_mc_dtor, .dtor = _nvkm_mc_dtor,
.init = nv50_mc_init, .init = nv50_mc_init,
.fini = _nouveau_mc_fini, .fini = _nvkm_mc_fini,
}, },
.intr = nv50_mc_intr, .intr = nv50_mc_intr,
.msi_rearm = nv50_mc_msi_rearm, .msi_rearm = nv50_mc_msi_rearm,

42
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
View File

@ -1,38 +1,36 @@
#ifndef __NVKM_MC_PRIV_H__ #ifndef __NVKM_MC_PRIV_H__
#define __NVKM_MC_PRIV_H__ #define __NVKM_MC_PRIV_H__
#include <subdev/mc.h> #include <subdev/mc.h>
#define nouveau_mc_create(p,e,o,d) \ #define nvkm_mc_create(p,e,o,d) \
nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d) nvkm_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_mc_destroy(p) ({ \ #define nvkm_mc_destroy(p) ({ \
struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \ struct nvkm_mc *pmc = (p); _nvkm_mc_dtor(nv_object(pmc)); \
}) })
#define nouveau_mc_init(p) ({ \ #define nvkm_mc_init(p) ({ \
struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc)); \ struct nvkm_mc *pmc = (p); _nvkm_mc_init(nv_object(pmc)); \
}) })
#define nouveau_mc_fini(p,s) ({ \ #define nvkm_mc_fini(p,s) ({ \
struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s)); \ struct nvkm_mc *pmc = (p); _nvkm_mc_fini(nv_object(pmc), (s)); \
}) })
int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *, int nvkm_mc_create_(struct nvkm_object *, struct nvkm_object *,
struct nouveau_oclass *, int, void **); struct nvkm_oclass *, int, void **);
void _nouveau_mc_dtor(struct nouveau_object *); void _nvkm_mc_dtor(struct nvkm_object *);
int _nouveau_mc_init(struct nouveau_object *); int _nvkm_mc_init(struct nvkm_object *);
int _nouveau_mc_fini(struct nouveau_object *, bool); int _nvkm_mc_fini(struct nvkm_object *, bool);
struct nouveau_mc_intr { struct nvkm_mc_intr {
u32 stat; u32 stat;
u32 unit; u32 unit;
}; };
struct nouveau_mc_oclass { struct nvkm_mc_oclass {
struct nouveau_oclass base; struct nvkm_oclass base;
const struct nouveau_mc_intr *intr; const struct nvkm_mc_intr *intr;
void (*msi_rearm)(struct nouveau_mc *); void (*msi_rearm)(struct nvkm_mc *);
void (*unk260)(struct nouveau_mc *, u32); void (*unk260)(struct nvkm_mc *, u32);
}; };
void nvc0_mc_unk260(struct nouveau_mc *, u32); void gf100_mc_unk260(struct nvkm_mc *, u32);
#endif #endif