hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'nvme-4.14' of git://git.infradead.org/nvme into for-linus 

Pull NVMe fixes from Christoph:

"A trivial one-liner from Martin to fix the visible of the uuid attr,
and another one (originally from Abhishek Shah, rewritten by me) to fix
the CMB addresses passed back to the controller in case of a system that
remaps BAR addresses between host and device."
This commit is contained in:
Jens Axboe 2017-10-05 10:44:04 -06:00
parent eab40cf336 8969f1f829
commit d7b544def4
2 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/nvme/host/core.c
View File

@ -2136,7 +2136,7 @@ static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
struct nvme_ns *ns = nvme_get_ns_from_dev(dev); struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
if (a == &dev_attr_uuid.attr) { if (a == &dev_attr_uuid.attr) {
if (uuid_is_null(&ns->uuid) || if (uuid_is_null(&ns->uuid) &&
!memchr_inv(ns->nguid, 0, sizeof(ns->nguid))) !memchr_inv(ns->nguid, 0, sizeof(ns->nguid)))
return 0; return 0;
} }

14
drivers/nvme/host/pci.c
View File

@ -94,7 +94,7 @@ struct nvme_dev {
struct mutex shutdown_lock; struct mutex shutdown_lock;
bool subsystem; bool subsystem;
void __iomem *cmb; void __iomem *cmb;
dma_addr_t cmb_dma_addr; pci_bus_addr_t cmb_bus_addr;
u64 cmb_size; u64 cmb_size;
u32 cmbsz; u32 cmbsz;
u32 cmbloc; u32 cmbloc;
@ -1226,7 +1226,7 @@ static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
dev->ctrl.page_size); dev->ctrl.page_size);
nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
nvmeq->sq_cmds_io = dev->cmb + offset; nvmeq->sq_cmds_io = dev->cmb + offset;
} else { } else {
nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
@ -1527,7 +1527,7 @@ static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
resource_size_t bar_size; resource_size_t bar_size;
struct pci_dev *pdev = to_pci_dev(dev->dev); struct pci_dev *pdev = to_pci_dev(dev->dev);
void __iomem *cmb; void __iomem *cmb;
dma_addr_t dma_addr; int bar;
dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
if (!(NVME_CMB_SZ(dev->cmbsz))) if (!(NVME_CMB_SZ(dev->cmbsz)))
@ -1540,7 +1540,8 @@ static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
size = szu * NVME_CMB_SZ(dev->cmbsz); size = szu * NVME_CMB_SZ(dev->cmbsz);
offset = szu * NVME_CMB_OFST(dev->cmbloc); offset = szu * NVME_CMB_OFST(dev->cmbloc);
bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); bar = NVME_CMB_BIR(dev->cmbloc);
bar_size = pci_resource_len(pdev, bar);
if (offset > bar_size) if (offset > bar_size)
return NULL; return NULL;
@ -1553,12 +1554,11 @@ static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
if (size > bar_size - offset) if (size > bar_size - offset)
size = bar_size - offset; size = bar_size - offset;
dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
cmb = ioremap_wc(dma_addr, size);
if (!cmb) if (!cmb)
return NULL; return NULL;
dev->cmb_dma_addr = dma_addr; dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
dev->cmb_size = size; dev->cmb_size = size;
return cmb; return cmb;
} }