KVM: arm64: vgic-v3: Add ICV_BPR1_EL1 handler
Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1 register, which is located in the ICH_VMCR_EL2.BPR1 field. Tested-by: Alexander Graf <agraf@suse.de> Acked-by: David Daney <david.daney@cavium.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Christoffer Dall <cdall@linaro.org>
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@ -375,6 +375,57 @@ void __hyp_text __vgic_v3_write_vmcr(u32 vmcr)
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#ifdef CONFIG_ARM64
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static int __hyp_text __vgic_v3_bpr_min(void)
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{
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/* See Pseudocode for VPriorityGroup */
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return 8 - vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2));
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}
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static unsigned int __hyp_text __vgic_v3_get_bpr0(u32 vmcr)
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{
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return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
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}
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static unsigned int __hyp_text __vgic_v3_get_bpr1(u32 vmcr)
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{
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unsigned int bpr;
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if (vmcr & ICH_VMCR_CBPR_MASK) {
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bpr = __vgic_v3_get_bpr0(vmcr);
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if (bpr < 7)
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bpr++;
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} else {
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bpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
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}
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return bpr;
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}
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static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
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}
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static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
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{
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u64 val = vcpu_get_reg(vcpu, rt);
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u8 bpr_min = __vgic_v3_bpr_min();
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if (vmcr & ICH_VMCR_CBPR_MASK)
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return;
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/* Enforce BPR limiting */
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if (val < bpr_min)
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val = bpr_min;
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val <<= ICH_VMCR_BPR1_SHIFT;
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val &= ICH_VMCR_BPR1_MASK;
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vmcr &= ~ICH_VMCR_BPR1_MASK;
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vmcr |= val;
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__vgic_v3_write_vmcr(vmcr);
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}
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int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
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{
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int rt;
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@ -397,6 +448,12 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
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is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
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switch (sysreg) {
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case SYS_ICC_BPR1_EL1:
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if (is_read)
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fn = __vgic_v3_read_bpr1;
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else
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fn = __vgic_v3_write_bpr1;
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break;
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default:
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return 0;
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}
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