ARM: sa1100: convert to common clock framework
Convert sa1100 to use the common clock framework. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Russell King
parent
5c9e4d8c84
commit
d6c8204659
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@ -549,6 +549,7 @@ config ARCH_SA1100
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select CLKSRC_MMIO
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select CLKSRC_PXA
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select TIMER_OF if OF
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select COMMON_CLK
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select CPU_FREQ
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select CPU_SA1100
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select GENERIC_CLOCKEVENTS
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@ -2,176 +2,144 @@
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/*
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* linux/arch/arm/mach-sa1100/clock.c
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <mach/hardware.h>
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#include <mach/generic.h>
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struct clkops {
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void (*enable)(struct clk *);
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void (*disable)(struct clk *);
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unsigned long (*get_rate)(struct clk *);
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static const char * const clk_tucr_parents[] = {
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"clk32768", "clk3686400",
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};
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struct clk {
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const struct clkops *ops;
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unsigned int enabled;
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};
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static DEFINE_SPINLOCK(tucr_lock);
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#define DEFINE_CLK(_name, _ops) \
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struct clk clk_##_name = { \
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.ops = _ops, \
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}
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static DEFINE_SPINLOCK(clocks_lock);
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/* Dummy clk routine to build generic kernel parts that may be using them */
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long clk_round_rate(struct clk *clk, unsigned long rate)
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static int clk_gpio27_enable(struct clk_hw *hw)
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{
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return clk_get_rate(clk);
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}
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EXPORT_SYMBOL(clk_round_rate);
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unsigned long flags;
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_set_rate);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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struct clk *clk_get_parent(struct clk *clk)
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{
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return NULL;
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}
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EXPORT_SYMBOL(clk_get_parent);
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static void clk_gpio27_enable(struct clk *clk)
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{
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/*
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* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
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* (SA-1110 Developer's Manual, section 9.1.2.1)
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*/
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local_irq_save(flags);
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GAFR |= GPIO_32_768kHz;
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GPDR |= GPIO_32_768kHz;
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TUCR = TUCR_3_6864MHz;
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local_irq_restore(flags);
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return 0;
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}
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static void clk_gpio27_disable(struct clk *clk)
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static void clk_gpio27_disable(struct clk_hw *hw)
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{
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TUCR = 0;
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unsigned long flags;
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local_irq_save(flags);
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GPDR &= ~GPIO_32_768kHz;
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GAFR &= ~GPIO_32_768kHz;
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local_irq_restore(flags);
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}
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static void clk_cpu_enable(struct clk *clk)
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{
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}
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static void clk_cpu_disable(struct clk *clk)
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{
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}
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static unsigned long clk_cpu_get_rate(struct clk *clk)
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{
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return sa11x0_getspeed(0) * 1000;
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (clk) {
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spin_lock_irqsave(&clocks_lock, flags);
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if (clk->enabled++ == 0)
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clk->ops->enable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (clk) {
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WARN_ON(clk->enabled == 0);
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spin_lock_irqsave(&clocks_lock, flags);
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if (--clk->enabled == 0)
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clk->ops->disable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk && clk->ops && clk->ops->get_rate)
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return clk->ops->get_rate(clk);
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return 0;
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}
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EXPORT_SYMBOL(clk_get_rate);
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const struct clkops clk_gpio27_ops = {
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static const struct clk_ops clk_gpio27_ops = {
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.enable = clk_gpio27_enable,
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.disable = clk_gpio27_disable,
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};
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const struct clkops clk_cpu_ops = {
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.enable = clk_cpu_enable,
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.disable = clk_cpu_disable,
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.get_rate = clk_cpu_get_rate,
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static const char * const clk_gpio27_parents[] = {
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"tucr-mux",
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};
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static DEFINE_CLK(gpio27, &clk_gpio27_ops);
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static const struct clk_init_data clk_gpio27_init_data __initconst = {
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.name = "gpio27",
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.ops = &clk_gpio27_ops,
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.parent_names = clk_gpio27_parents,
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.num_parents = ARRAY_SIZE(clk_gpio27_parents),
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};
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static DEFINE_CLK(cpu, &clk_cpu_ops);
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static unsigned long clk_36864_get_rate(struct clk *clk)
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/*
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* Derived from the table 8-1 in the SA1110 manual, the MPLL appears to
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* multiply its input rate by 4 x (4 + PPCR). This calculation gives
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* the exact rate. The figures given in the table are the rates rounded
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* to 100kHz. Stick with sa11x0_getspeed() for the time being.
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*/
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static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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return 3686400;
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return sa11x0_getspeed(0) * 1000;
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}
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static struct clkops clk_36864_ops = {
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.enable = clk_cpu_enable,
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.disable = clk_cpu_disable,
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.get_rate = clk_36864_get_rate,
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static const struct clk_ops clk_mpll_ops = {
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.recalc_rate = clk_mpll_recalc_rate,
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};
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static DEFINE_CLK(36864, &clk_36864_ops);
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static const char * const clk_mpll_parents[] = {
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"clk3686400",
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};
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static struct clk_lookup sa11xx_clkregs[] = {
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CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
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CLKDEV_INIT("sa1100-rtc", NULL, NULL),
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CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu),
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CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu),
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CLKDEV_INIT("sa11x0-pcmcia.0", NULL, &clk_cpu),
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CLKDEV_INIT("sa11x0-pcmcia.1", NULL, &clk_cpu),
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/* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */
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CLKDEV_INIT("1800", NULL, &clk_cpu),
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CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864),
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static const struct clk_init_data clk_mpll_init_data __initconst = {
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.name = "mpll",
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.ops = &clk_mpll_ops,
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.parent_names = clk_mpll_parents,
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.num_parents = ARRAY_SIZE(clk_mpll_parents),
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.flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL,
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};
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int __init sa11xx_clk_init(void)
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{
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clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
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struct clk_hw *hw;
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int ret;
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hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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clk_hw_register_clkdev(hw, NULL, "sa1100-rtc");
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hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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clk_hw_register_clkdev(hw, "OSTIMER0", NULL);
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hw = kzalloc(sizeof(*hw), GFP_KERNEL);
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if (!hw)
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return -ENOMEM;
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hw->init = &clk_mpll_init_data;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(hw);
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return ret;
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}
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clk_hw_register_clkdev(hw, NULL, "sa11x0-fb");
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clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia");
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clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0");
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clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1");
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clk_hw_register_clkdev(hw, NULL, "1800");
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hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents,
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ARRAY_SIZE(clk_tucr_parents), 0,
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(void __iomem *)&TUCR, FShft(TUCR_TSEL),
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FAlnMsk(TUCR_TSEL), 0, &tucr_lock);
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clk_set_rate(hw->clk, 3686400);
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hw = kzalloc(sizeof(*hw), GFP_KERNEL);
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if (!hw)
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return -ENOMEM;
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hw->init = &clk_gpio27_init_data;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(hw);
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return ret;
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}
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clk_hw_register_clkdev(hw, NULL, "sa1111.0");
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return 0;
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}
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