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mx5: bring usb phy out of reset on freescale mx51 babbage hw 

This patch de-asserts the reset line that is connected to the USB
ULPI PHY on USB Host1.

This patch should be included with the original USB host enablement
set of patches of mx51 babbage hw, but was accidentily left out.

Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Dinh Nguyen 2010-05-17 10:46:01 -05:00 committed by Sascha Hauer
parent 4a870fc898
commit d6b273bfdf
2 changed files with 13 additions and 0 deletions
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12
arch/arm/mach-mx5/board-mx51_babbage.c
View File

@ -33,6 +33,7 @@
#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */
/* USB_CTRL_1 */ /* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10 #define MX51_USB_CTRL_1_OFFSET 0x10
@ -101,6 +102,7 @@ static inline void mxc_init_imx_uart(void)
static int gpio_usbh1_active(void) static int gpio_usbh1_active(void)
{ {
struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
int ret; int ret;
/* Set USBH1_STP to GPIO and toggle it */ /* Set USBH1_STP to GPIO and toggle it */
@ -115,6 +117,16 @@ static int gpio_usbh1_active(void)
gpio_set_value(BABBAGE_USBH1_STP, 1); gpio_set_value(BABBAGE_USBH1_STP, 1);
msleep(100); msleep(100);
gpio_free(BABBAGE_USBH1_STP); gpio_free(BABBAGE_USBH1_STP);
/* De-assert USB PHY RESETB */
mxc_iomux_v3_setup_pad(&phyreset_gpio);
ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
if (ret) {
pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
return ret;
}
gpio_direction_output(BABBAGE_PHY_RESET, 1);
return 0; return 0;
} }

1
arch/arm/plat-mxc/include/mach/iomux-mx51.h
View File

@ -63,6 +63,7 @@ typedef enum iomux_config {
#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)