Merge branch 'pci/bjorn-disable-decode' into next
* pci/bjorn-disable-decode: PCI: disable MEM decoding while updating 64-bit MEM BARs PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, too
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commit
d68e70c6e5
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@ -189,9 +189,6 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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pci_read_config_dword(dev, pos, &sz);
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pci_write_config_dword(dev, pos, l);
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if (!dev->mmio_always_on)
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pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
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/*
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* All bits set in sz means the device isn't working properly.
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* If the BAR isn't implemented, all bits must be 0. If it's a
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@ -276,6 +273,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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}
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out:
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if (!dev->mmio_always_on)
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pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
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return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
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fail:
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res->flags = 0;
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@ -30,6 +30,8 @@
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void pci_update_resource(struct pci_dev *dev, int resno)
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{
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struct pci_bus_region region;
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bool disable;
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u16 cmd;
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u32 new, check, mask;
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int reg;
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enum pci_bar_type type;
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@ -67,6 +69,18 @@ void pci_update_resource(struct pci_dev *dev, int resno)
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new |= PCI_ROM_ADDRESS_ENABLE;
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}
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/*
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* We can't update a 64-bit BAR atomically, so when possible,
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* disable decoding so that a half-updated BAR won't conflict
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* with another device.
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*/
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disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
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if (disable) {
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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pci_write_config_word(dev, PCI_COMMAND,
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cmd & ~PCI_COMMAND_MEMORY);
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}
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pci_write_config_dword(dev, reg, new);
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pci_read_config_dword(dev, reg, &check);
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@ -84,6 +98,10 @@ void pci_update_resource(struct pci_dev *dev, int resno)
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"(high %#08x != %#08x)\n", resno, new, check);
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}
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}
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if (disable)
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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res->flags &= ~IORESOURCE_UNSET;
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dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
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resno, res, (unsigned long long)region.start,
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