From 5210edcd527773c227465ad18e416a894966324f Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 28 Sep 2012 11:34:10 -0700 Subject: [PATCH 1/9] MIPS: Make __{,n,u}delay declarations match definitions and generic delay.h At some recent point arch/mips/include/asm/delay.h has started being included into csrc-octeon.c where the __?delay() functions are defined. This causes a compile failure due to conflicting declarations and definitions of the functions. It turns out that the generic definitions in arch/mips/lib/delay.c also conflict. Proposed fix: Declare the functions to take unsigned long parameters just like asm-generic (and x86) does. Update __delay to agree (__ndelay and __udelay need no change). Bonus: Get rid of 'inline' from __delay() definition, as it is globally visible, and the compiler should be making this decision itself (it does in fact inline the function without being told to). Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4354/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/delay.h | 6 +++--- arch/mips/lib/delay.c | 6 +++++- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h index e7cd78277c23..dc0a5f77a35c 100644 --- a/arch/mips/include/asm/delay.h +++ b/arch/mips/include/asm/delay.h @@ -13,9 +13,9 @@ #include -extern void __delay(unsigned int loops); -extern void __ndelay(unsigned int ns); -extern void __udelay(unsigned int us); +extern void __delay(unsigned long loops); +extern void __ndelay(unsigned long ns); +extern void __udelay(unsigned long us); #define ndelay(ns) __ndelay(ns) #define udelay(us) __udelay(us) diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c index 5995969e8c42..dc81ca8dc0dd 100644 --- a/arch/mips/lib/delay.c +++ b/arch/mips/lib/delay.c @@ -15,13 +15,17 @@ #include #include -inline void __delay(unsigned int loops) +void __delay(unsigned long loops) { __asm__ __volatile__ ( " .set noreorder \n" " .align 3 \n" "1: bnez %0, 1b \n" +#if __SIZEOF_LONG__ == 4 " subu %0, 1 \n" +#else + " dsubu %0, 1 \n" +#endif " .set reorder \n" : "=r" (loops) : "0" (loops)); From 02a5417751c31cd64197652c000a5ab0d3261465 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 13 Oct 2012 22:46:26 +0200 Subject: [PATCH 2/9] MIPS: tlbex: Deal with re-definition of label The microassembler used in tlbex.c does not notice if a label is redefined resulting in relocations against such labels silently missrelocated. The issues exists since commit add6eb04776db4189ea89f596cbcde31b899be9d [Synthesize TLB exception handlers at runtime.] in 2.6.10 and went unnoticed for so long because the relocations for the affected branches got computed to do something *almost* sensible. The issue affects R4000, R4400, QED/IDT RM5230, RM5231, RM5260, RM5261, RM5270 and RM5271 processors. Signed-off-by: Ralf Baechle --- arch/mips/mm/tlbex.c | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 658a520364ce..6ea152552e51 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -148,8 +148,8 @@ enum label_id { label_leave, label_vmalloc, label_vmalloc_done, - label_tlbw_hazard, - label_split, + label_tlbw_hazard_0, + label_split = label_tlbw_hazard_0 + 8, label_tlbl_goaround1, label_tlbl_goaround2, label_nopage_tlbl, @@ -167,7 +167,7 @@ UASM_L_LA(_second_part) UASM_L_LA(_leave) UASM_L_LA(_vmalloc) UASM_L_LA(_vmalloc_done) -UASM_L_LA(_tlbw_hazard) +/* _tlbw_hazard_x is handled differently. */ UASM_L_LA(_split) UASM_L_LA(_tlbl_goaround1) UASM_L_LA(_tlbl_goaround2) @@ -181,6 +181,30 @@ UASM_L_LA(_large_segbits_fault) UASM_L_LA(_tlb_huge_update) #endif +static int __cpuinitdata hazard_instance; + +static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) +{ + switch (instance) { + case 0 ... 7: + uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); + return; + default: + BUG(); + } +} + +static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) +{ + switch (instance) { + case 0 ... 7: + uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); + break; + default: + BUG(); + } +} + /* * For debug purposes. */ @@ -478,9 +502,10 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, * This branch uses up a mtc0 hazard nop slot and saves * two nops after the tlbw instruction. */ - uasm_il_bgezl(p, r, 0, label_tlbw_hazard); + uasm_bgezl_hazard(p, r, hazard_instance); tlbw(p); - uasm_l_tlbw_hazard(l, *p); + uasm_bgezl_label(l, p, hazard_instance); + hazard_instance++; uasm_i_nop(p); break; @@ -527,14 +552,16 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, break; case CPU_NEVADA: + uasm_i_nop(p); /* QED specifies 2 nops hazard */ uasm_i_nop(p); /* QED specifies 2 nops hazard */ /* * This branch uses up a mtc0 hazard nop slot and saves * a nop after the tlbw instruction. */ - uasm_il_bgezl(p, r, 0, label_tlbw_hazard); + uasm_bgezl_hazard(p, r, hazard_instance); tlbw(p); - uasm_l_tlbw_hazard(l, *p); + uasm_bgezl_label(l, p, hazard_instance); + hazard_instance++; break; case CPU_RM7000: From 359187d647a7a7813444ff5932d0b862f970bb0f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 16 Oct 2012 22:13:06 +0200 Subject: [PATCH 3/9] MIPS: R5000: Fix TLB hazard handling. R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and RM5271) are basically the same CPU core and all are documented to require two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0, c0_entrylo1 or c0_index. So far we were only providing on cycle before / after a TLBR/TLBWI for R5000 but 3 cycles before and 1 cycles after for the Nevadas. Signed-off-by: Ralf Baechle --- arch/mips/mm/tlbex.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 6ea152552e51..2833dcb67b5a 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -511,13 +511,19 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_R4600: case CPU_R4700: - case CPU_R5000: - case CPU_R5000A: uasm_i_nop(p); tlbw(p); uasm_i_nop(p); break; + case CPU_R5000: + case CPU_R5000A: + case CPU_NEVADA: + uasm_i_nop(p); /* QED specifies 2 nops hazard */ + uasm_i_nop(p); /* QED specifies 2 nops hazard */ + tlbw(p); + break; + case CPU_R4300: case CPU_5KC: case CPU_TX49XX: @@ -551,19 +557,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, tlbw(p); break; - case CPU_NEVADA: - uasm_i_nop(p); /* QED specifies 2 nops hazard */ - uasm_i_nop(p); /* QED specifies 2 nops hazard */ - /* - * This branch uses up a mtc0 hazard nop slot and saves - * a nop after the tlbw instruction. - */ - uasm_bgezl_hazard(p, r, hazard_instance); - tlbw(p); - uasm_bgezl_label(l, p, hazard_instance); - hazard_instance++; - break; - case CPU_RM7000: uasm_i_nop(p); uasm_i_nop(p); From 344afa6550a66eb4b7103cf1b65fca6f38d380d8 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 17 Oct 2012 01:01:12 +0200 Subject: [PATCH 4/9] MIPS: Hugetlbfs: Handle huge pages correctly in pmd_bad() Signed-off-by: Ralf Baechle --- arch/mips/include/asm/pgtable-64.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index c26e18250079..f5b521d5a67d 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -9,6 +9,7 @@ #ifndef _ASM_PGTABLE_64_H #define _ASM_PGTABLE_64_H +#include #include #include @@ -172,7 +173,19 @@ static inline int pmd_none(pmd_t pmd) return pmd_val(pmd) == (unsigned long) invalid_pte_table; } -#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) +static inline int pmd_bad(pmd_t pmd) +{ +#ifdef CONFIG_HUGETLB_PAGE + /* pmd_huge(pmd) but inline */ + if (unlikely(pmd_val(pmd) & _PAGE_HUGE)) + return 0; +#endif + + if (unlikely(pmd_val(pmd) & ~PAGE_MASK)) + return 1; + + return 0; +} static inline int pmd_present(pmd_t pmd) { From 01422ff49135e0b747132686405ea8a58f760997 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 17 Oct 2012 01:01:20 +0200 Subject: [PATCH 5/9] MIPS: Restore pagemask after dumping the TLB. Or bad things might happen if the last TLB entry isn't a basic size page. Signed-off-by: Ralf Baechle --- arch/mips/lib/dump_tlb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 3f69725556af..a99c1d3fc567 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -50,8 +50,9 @@ static void dump_tlb(int first, int last) { unsigned long s_entryhi, entryhi, asid; unsigned long long entrylo0, entrylo1; - unsigned int s_index, pagemask, c0, c1, i; + unsigned int s_index, s_pagemask, pagemask, c0, c1, i; + s_pagemask = read_c0_pagemask(); s_entryhi = read_c0_entryhi(); s_index = read_c0_index(); asid = s_entryhi & 0xff; @@ -103,6 +104,7 @@ static void dump_tlb(int first, int last) write_c0_entryhi(s_entryhi); write_c0_index(s_index); + write_c0_pagemask(s_pagemask); } void dump_tlb_all(void) From fb944c9ba3f4838a64929a1926822e987b4e44c0 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 17 Oct 2012 01:01:21 +0200 Subject: [PATCH 6/9] MIPS: hugetlbfs: Fix hazard between tlb write and pagemask restoration. On some CPU the write to pagemask might complete before the TLB write instruction reads from the pagemask register. Signed-off-by: Ralf Baechle --- arch/mips/mm/tlb-r4k.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 87b9cfcc30ff..4b9b935a070e 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -320,6 +320,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) tlb_write_random(); else tlb_write_indexed(); + tlbw_use_hazard(); write_c0_pagemask(PM_DEFAULT_MASK); } else #endif From a40b012f76e4016af7a56a9671904118b23107e8 Mon Sep 17 00:00:00 2001 From: Antony Pavlov Date: Tue, 16 Oct 2012 01:38:46 +0400 Subject: [PATCH 7/9] MIPS: JZ4740: Fix '#include guard' in serial.h Signed-off-by: Antony Pavlov Cc: linux-mips@linux-mips.org Cc: Lars-Peter Clausen Patchwork: https://patchwork.linux-mips.org/patch/4424/ Signed-off-by: Ralf Baechle --- arch/mips/jz4740/serial.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/jz4740/serial.h b/arch/mips/jz4740/serial.h index b9fe3ade0289..aa5a93982c4d 100644 --- a/arch/mips/jz4740/serial.h +++ b/arch/mips/jz4740/serial.h @@ -14,6 +14,7 @@ */ #ifndef __MIPS_JZ4740_SERIAL_H__ +#define __MIPS_JZ4740_SERIAL_H__ void jz4740_serial_out(struct uart_port *p, int offset, int value); From a12265400c18e6e67d444f05fec3a792a2f87c10 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 17 Oct 2012 17:00:50 +0200 Subject: [PATCH 8/9] MIPS: JZ4740: Forward declare struct uart_port in header. As suggested by Geert Uytterhoeven . Signed-off-by: Ralf Baechle Cc: Antony Pavlov Cc: linux-mips@linux-mips.org Cc: Lars-Peter Clausen --- arch/mips/jz4740/serial.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/jz4740/serial.h b/arch/mips/jz4740/serial.h index aa5a93982c4d..8eb715bb1ea8 100644 --- a/arch/mips/jz4740/serial.h +++ b/arch/mips/jz4740/serial.h @@ -16,6 +16,8 @@ #ifndef __MIPS_JZ4740_SERIAL_H__ #define __MIPS_JZ4740_SERIAL_H__ +struct uart_port; + void jz4740_serial_out(struct uart_port *p, int offset, int value); #endif From 0cc40dac8605b3b6b099b47cdde9500d592e6583 Mon Sep 17 00:00:00 2001 From: jerin jacob Date: Thu, 11 Oct 2012 22:18:51 +0530 Subject: [PATCH 9/9] MIPS: CMP: Fix physical core number calculation logic The CPUNum Field in EBase register is 10bit wide, so after 1 bit right shift, the mask value should be 0x1ff. Signed-off-by: jerin jacob Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4420/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index afc379ca3753..06cd0c610f44 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -97,7 +97,7 @@ static void cmp_init_secondary(void) /* Enable per-cpu interrupts: platform specific */ - c->core = (read_c0_ebase() >> 1) & 0xff; + c->core = (read_c0_ebase() >> 1) & 0x1ff; #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE; #endif