Merge branch 'clk-qcom-spmi-div' into clk-next
* clk-qcom-spmi-div: clk: qcom: Add spmi_pmic clock divider support dt-bindings: Add qcom spmi_pmic clock divider bindings
This commit is contained in:
Stephen Boyd
commit
d6185e81ba
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@ -0,0 +1,59 @@
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Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
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clkdiv configures the clock frequency of a set of outputs on the PMIC.
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These clocks are typically wired through alternate functions on
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gpio pins.
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=======================
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Properties
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=======================
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be "qcom,spmi-clkdiv".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: base address of CLKDIV peripherals.
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- qcom,num-clkdivs
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Usage: required
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Value type: <u32>
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Definition: number of CLKDIV peripherals.
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the xo clock.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "xo".
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- #clock-cells:
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Usage: required
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Value type: <u32>
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Definition: shall contain 1.
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=======
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Example
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=======
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pm8998_clk_divs: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <3>;
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clocks = <&xo_board>;
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clock-names = "xo";
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assigned-clocks = <&pm8998_clk_divs 1>,
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<&pm8998_clk_divs 2>,
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<&pm8998_clk_divs 3>;
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assigned-clock-rates = <9600000>,
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<9600000>,
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<9600000>;
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};
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@ -196,3 +196,12 @@ config MSM_MMCC_8996
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Support for the multimedia clock controller on msm8996 devices.
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Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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config SPMI_PMIC_CLKDIV
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tristate "SPMI PMIC clkdiv Support"
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depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
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help
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This driver supports the clkdiv functionality on the Qualcomm
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Technologies, Inc. SPMI PMIC. It configures the frequency of
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clkdiv outputs of the PMIC. These clocks are typically wired
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through alternate functions on GPIO pins.
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@ -34,3 +34,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
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obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
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obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
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obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
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obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
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@ -0,0 +1,302 @@
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/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#define REG_DIV_CTL1 0x43
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#define DIV_CTL1_DIV_FACTOR_MASK GENMASK(2, 0)
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#define REG_EN_CTL 0x46
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#define REG_EN_MASK BIT(7)
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struct clkdiv {
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struct regmap *regmap;
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u16 base;
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spinlock_t lock;
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struct clk_hw hw;
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unsigned int cxo_period_ns;
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};
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static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)
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{
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return container_of(hw, struct clkdiv, hw);
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}
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static inline unsigned int div_factor_to_div(unsigned int div_factor)
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{
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if (!div_factor)
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div_factor = 1;
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return 1 << (div_factor - 1);
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}
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static inline unsigned int div_to_div_factor(unsigned int div)
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{
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return min(ilog2(div) + 1, 7);
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}
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static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)
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{
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unsigned int val = 0;
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regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);
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return val & REG_EN_MASK;
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}
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static int
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__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,
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unsigned int div_factor)
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{
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int ret;
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unsigned int ns = clkdiv->cxo_period_ns;
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unsigned int div = div_factor_to_div(div_factor);
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ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
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REG_EN_MASK, enable ? REG_EN_MASK : 0);
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if (ret)
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return ret;
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if (enable)
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ndelay((2 + 3 * div) * ns);
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else
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ndelay(3 * div * ns);
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return 0;
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}
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static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)
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{
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unsigned int div_factor;
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regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
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div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
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return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
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}
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static int clk_spmi_pmic_div_enable(struct clk_hw *hw)
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{
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struct clkdiv *clkdiv = to_clkdiv(hw);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&clkdiv->lock, flags);
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ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
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spin_unlock_irqrestore(&clkdiv->lock, flags);
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return ret;
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}
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static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
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{
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struct clkdiv *clkdiv = to_clkdiv(hw);
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unsigned long flags;
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spin_lock_irqsave(&clkdiv->lock, flags);
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spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
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spin_unlock_irqrestore(&clkdiv->lock, flags);
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}
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static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned int div, div_factor;
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div = DIV_ROUND_UP(*parent_rate, rate);
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div_factor = div_to_div_factor(div);
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div = div_factor_to_div(div_factor);
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return *parent_rate / div;
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}
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static unsigned long
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clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clkdiv *clkdiv = to_clkdiv(hw);
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unsigned int div_factor;
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regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
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div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
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return parent_rate / div_factor_to_div(div_factor);
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}
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static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clkdiv *clkdiv = to_clkdiv(hw);
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unsigned int div_factor = div_to_div_factor(parent_rate / rate);
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unsigned long flags;
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bool enabled;
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int ret;
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spin_lock_irqsave(&clkdiv->lock, flags);
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enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
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if (enabled) {
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ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
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if (ret)
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goto unlock;
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}
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ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,
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DIV_CTL1_DIV_FACTOR_MASK, div_factor);
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if (ret)
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goto unlock;
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if (enabled)
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ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,
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div_factor);
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unlock:
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spin_unlock_irqrestore(&clkdiv->lock, flags);
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return ret;
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}
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static const struct clk_ops clk_spmi_pmic_div_ops = {
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.enable = clk_spmi_pmic_div_enable,
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.disable = clk_spmi_pmic_div_disable,
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.set_rate = clk_spmi_pmic_div_set_rate,
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.recalc_rate = clk_spmi_pmic_div_recalc_rate,
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.round_rate = clk_spmi_pmic_div_round_rate,
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};
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struct spmi_pmic_div_clk_cc {
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int nclks;
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struct clkdiv clks[];
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};
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static struct clk_hw *
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spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data)
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{
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struct spmi_pmic_div_clk_cc *cc = data;
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int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */
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if (idx < 0 || idx >= cc->nclks) {
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pr_err("%s: index value %u is invalid; allowed range [1, %d]\n",
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__func__, clkspec->args[0], cc->nclks);
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return ERR_PTR(-EINVAL);
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}
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return &cc->clks[idx].hw;
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}
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static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
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{
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struct spmi_pmic_div_clk_cc *cc;
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struct clk_init_data init = {};
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struct clkdiv *clkdiv;
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struct clk *cxo;
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struct regmap *regmap;
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struct device *dev = &pdev->dev;
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struct device_node *of_node = dev->of_node;
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const char *parent_name;
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int nclks, i, ret, cxo_hz;
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char name[20];
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u32 start;
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ret = of_property_read_u32(of_node, "reg", &start);
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if (ret < 0) {
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dev_err(dev, "reg property reading failed\n");
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return ret;
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}
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regmap = dev_get_regmap(dev->parent, NULL);
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if (!regmap) {
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dev_err(dev, "Couldn't get parent's regmap\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks);
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if (ret < 0) {
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dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n",
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ret);
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return ret;
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}
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if (!nclks)
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return -EINVAL;
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cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*cc->clks) * nclks,
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GFP_KERNEL);
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if (!cc)
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return -ENOMEM;
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cc->nclks = nclks;
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cxo = clk_get(dev, "xo");
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if (IS_ERR(cxo)) {
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ret = PTR_ERR(cxo);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "failed to get xo clock\n");
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return ret;
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}
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cxo_hz = clk_get_rate(cxo);
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clk_put(cxo);
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parent_name = of_clk_get_parent_name(of_node, 0);
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if (!parent_name) {
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dev_err(dev, "missing parent clock\n");
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return -ENODEV;
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}
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init.name = name;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.ops = &clk_spmi_pmic_div_ops;
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for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
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snprintf(name, sizeof(name), "div_clk%d", i + 1);
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spin_lock_init(&clkdiv[i].lock);
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clkdiv[i].base = start + i * 0x100;
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clkdiv[i].regmap = regmap;
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clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;
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clkdiv[i].hw.init = &init;
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ret = devm_clk_hw_register(dev, &clkdiv[i].hw);
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if (ret)
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return ret;
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}
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return devm_of_clk_add_hw_provider(dev, spmi_pmic_div_clk_hw_get, cc);
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}
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static const struct of_device_id spmi_pmic_clkdiv_match_table[] = {
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{ .compatible = "qcom,spmi-clkdiv" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table);
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static struct platform_driver spmi_pmic_clkdiv_driver = {
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.driver = {
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.name = "qcom,spmi-pmic-clkdiv",
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.of_match_table = spmi_pmic_clkdiv_match_table,
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},
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.probe = spmi_pmic_clkdiv_probe,
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};
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module_platform_driver(spmi_pmic_clkdiv_driver);
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MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver");
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MODULE_LICENSE("GPL v2");
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