cxl: Support the cxl kernel API from a guest
Like on bare-metal, the cxl driver creates a virtual PHB and a pci device for the AFU. The configuration space of the device is mapped to the configuration record of the AFU. Reuse the code defined in afu_cr_read8|16|32() when reading the configuration space of the AFU device. Even though the (virtual) AFU device is a pci device, the adapter is not. So a driver using the cxl kernel API cannot read the VPD of the adapter through the usual PCI interface. Therefore, we add a call to the cxl kernel API: ssize_t cxl_read_adapter_vpd(struct pci_dev *dev, void *buf, size_t count); Co-authored-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Frederic Barrat
Michael Ellerman
parent
b40844aa55
commit
d601ea918b
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@ -89,28 +89,11 @@ int cxl_release_context(struct cxl_context *ctx)
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}
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EXPORT_SYMBOL_GPL(cxl_release_context);
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int cxl_allocate_afu_irqs(struct cxl_context *ctx, int num)
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{
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if (num == 0)
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num = ctx->afu->pp_irqs;
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return afu_allocate_irqs(ctx, num);
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}
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EXPORT_SYMBOL_GPL(cxl_allocate_afu_irqs);
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void cxl_free_afu_irqs(struct cxl_context *ctx)
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{
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afu_irq_name_free(ctx);
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cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
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}
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EXPORT_SYMBOL_GPL(cxl_free_afu_irqs);
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static irq_hw_number_t cxl_find_afu_irq(struct cxl_context *ctx, int num)
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{
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__u16 range;
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int r;
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WARN_ON(num == 0);
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for (r = 0; r < CXL_IRQ_RANGES; r++) {
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range = ctx->irqs.range[r];
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if (num < range) {
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@ -121,6 +104,44 @@ static irq_hw_number_t cxl_find_afu_irq(struct cxl_context *ctx, int num)
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return 0;
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}
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int cxl_allocate_afu_irqs(struct cxl_context *ctx, int num)
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{
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int res;
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irq_hw_number_t hwirq;
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if (num == 0)
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num = ctx->afu->pp_irqs;
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res = afu_allocate_irqs(ctx, num);
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if (!res && !cpu_has_feature(CPU_FTR_HVMODE)) {
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/* In a guest, the PSL interrupt is not multiplexed. It was
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* allocated above, and we need to set its handler
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*/
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hwirq = cxl_find_afu_irq(ctx, 0);
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if (hwirq)
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cxl_map_irq(ctx->afu->adapter, hwirq, cxl_ops->psl_interrupt, ctx, "psl");
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}
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return res;
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}
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EXPORT_SYMBOL_GPL(cxl_allocate_afu_irqs);
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void cxl_free_afu_irqs(struct cxl_context *ctx)
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{
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irq_hw_number_t hwirq;
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unsigned int virq;
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if (!cpu_has_feature(CPU_FTR_HVMODE)) {
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hwirq = cxl_find_afu_irq(ctx, 0);
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if (hwirq) {
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virq = irq_find_mapping(NULL, hwirq);
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if (virq)
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cxl_unmap_irq(virq, ctx);
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}
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}
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afu_irq_name_free(ctx);
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cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
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}
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EXPORT_SYMBOL_GPL(cxl_free_afu_irqs);
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int cxl_map_afu_irq(struct cxl_context *ctx, int num,
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irq_handler_t handler, void *cookie, char *name)
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{
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@ -356,3 +377,11 @@ void cxl_perst_reloads_same_image(struct cxl_afu *afu,
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afu->adapter->perst_same_image = perst_reloads_same_image;
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}
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EXPORT_SYMBOL_GPL(cxl_perst_reloads_same_image);
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ssize_t cxl_read_adapter_vpd(struct pci_dev *dev, void *buf, size_t count)
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{
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struct cxl_afu *afu = cxl_pci_to_afu(dev);
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return cxl_ops->read_adapter_vpd(afu->adapter, buf, count);
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}
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EXPORT_SYMBOL_GPL(cxl_read_adapter_vpd);
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@ -587,6 +587,7 @@ int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq
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int cxl_update_image_control(struct cxl *adapter);
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int cxl_pci_reset(struct cxl *adapter);
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void cxl_pci_release_afu(struct device *dev);
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ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
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/* common == phyp + powernv */
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struct cxl_process_element_common {
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@ -808,7 +809,6 @@ int cxl_psl_purge(struct cxl_afu *afu);
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void cxl_stop_trace(struct cxl *cxl);
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int cxl_pci_vphb_add(struct cxl_afu *afu);
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void cxl_pci_vphb_reconfigure(struct cxl_afu *afu);
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void cxl_pci_vphb_remove(struct cxl_afu *afu);
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extern struct pci_driver cxl_pci_driver;
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@ -869,6 +869,10 @@ struct cxl_backend_ops {
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int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
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int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
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int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
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int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
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int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
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int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
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ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
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};
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extern const struct cxl_backend_ops cxl_native_ops;
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extern const struct cxl_backend_ops cxl_guest_ops;
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@ -418,6 +418,24 @@ static int guest_afu_cr_read64(struct cxl_afu *afu, int cr_idx, u64 offset,
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return _guest_afu_cr_readXX(8, afu, cr_idx, offset, out);
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}
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static int guest_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
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{
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/* config record is not writable from guest */
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return -EPERM;
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}
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static int guest_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
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{
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/* config record is not writable from guest */
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return -EPERM;
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}
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static int guest_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
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{
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/* config record is not writable from guest */
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return -EPERM;
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}
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static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
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{
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struct cxl_process_element_hcall *elem;
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@ -807,6 +825,9 @@ int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_n
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afu->enabled = true;
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if ((rc = cxl_pci_vphb_add(afu)))
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dev_info(&afu->dev, "Can't register vPHB\n");
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return 0;
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err_put2:
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@ -832,6 +853,7 @@ void cxl_guest_remove_afu(struct cxl_afu *afu)
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if (!afu)
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return;
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cxl_pci_vphb_remove(afu);
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cxl_sysfs_afu_remove(afu);
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spin_lock(&afu->adapter->afu_list_lock);
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@ -987,4 +1009,8 @@ const struct cxl_backend_ops cxl_guest_ops = {
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.afu_cr_read16 = guest_afu_cr_read16,
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.afu_cr_read32 = guest_afu_cr_read32,
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.afu_cr_read64 = guest_afu_cr_read64,
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.afu_cr_write8 = guest_afu_cr_write8,
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.afu_cr_write16 = guest_afu_cr_write16,
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.afu_cr_write32 = guest_afu_cr_write32,
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.read_adapter_vpd = cxl_guest_read_adapter_vpd,
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};
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@ -1019,6 +1019,52 @@ static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out)
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return rc;
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}
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static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
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{
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if (unlikely(!cxl_ops->link_ok(afu->adapter)))
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return -EIO;
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if (unlikely(off >= afu->crs_len))
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return -ERANGE;
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out_le32(afu->native->afu_desc_mmio + afu->crs_offset +
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(cr * afu->crs_len) + off, in);
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return 0;
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}
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static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
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{
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u64 aligned_off = off & ~0x3L;
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u32 val32, mask, shift;
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int rc;
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rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
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if (rc)
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return rc;
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shift = (off & 0x3) * 8;
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WARN_ON(shift == 24);
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mask = 0xffff << shift;
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val32 = (val32 & ~mask) | (in << shift);
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rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
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return rc;
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}
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static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
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{
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u64 aligned_off = off & ~0x3L;
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u32 val32, mask, shift;
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int rc;
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rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
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if (rc)
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return rc;
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shift = (off & 0x3) * 8;
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mask = 0xff << shift;
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val32 = (val32 & ~mask) | (in << shift);
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rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
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return rc;
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}
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const struct cxl_backend_ops cxl_native_ops = {
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.module = THIS_MODULE,
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.adapter_reset = cxl_pci_reset,
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@ -1044,4 +1090,8 @@ const struct cxl_backend_ops cxl_native_ops = {
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.afu_cr_read16 = native_afu_cr_read16,
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.afu_cr_read32 = native_afu_cr_read32,
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.afu_cr_read64 = native_afu_cr_read64,
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.afu_cr_write8 = native_afu_cr_write8,
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.afu_cr_write16 = native_afu_cr_write16,
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.afu_cr_write32 = native_afu_cr_write32,
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.read_adapter_vpd = cxl_pci_read_adapter_vpd,
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};
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@ -881,6 +881,7 @@ static void cxl_pci_remove_afu(struct cxl_afu *afu)
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if (!afu)
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return;
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cxl_pci_vphb_remove(afu);
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cxl_sysfs_afu_remove(afu);
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cxl_debugfs_afu_remove(afu);
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@ -1067,6 +1068,11 @@ static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
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return 0;
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}
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ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
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{
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return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
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}
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static void cxl_release_adapter(struct device *dev)
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{
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struct cxl *adapter = to_cxl_adapter(dev);
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@ -1272,7 +1278,6 @@ static void cxl_remove(struct pci_dev *dev)
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*/
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for (i = 0; i < adapter->slices; i++) {
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afu = adapter->afu[i];
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cxl_pci_vphb_remove(afu);
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cxl_pci_remove_afu(afu);
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}
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cxl_pci_remove_adapter(adapter);
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@ -1451,8 +1456,6 @@ static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
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if (cxl_afu_select_best_mode(afu))
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goto err;
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cxl_pci_vphb_reconfigure(afu);
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list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
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/* Reset the device context.
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* TODO: make this less disruptive
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@ -99,113 +99,90 @@ static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
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return (bus << 8) + devfn;
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}
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static unsigned long cxl_pcie_cfg_addr(struct pci_controller* phb,
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u8 bus, u8 devfn, int offset)
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{
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int record = cxl_pcie_cfg_record(bus, devfn);
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return (unsigned long)phb->cfg_addr + ((unsigned long)phb->cfg_data * record) + offset;
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}
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static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
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int offset, int len,
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volatile void __iomem **ioaddr,
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u32 *mask, int *shift)
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struct cxl_afu **_afu, int *_record)
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{
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struct pci_controller *phb;
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struct cxl_afu *afu;
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unsigned long addr;
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int record;
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phb = pci_bus_to_host(bus);
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if (phb == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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afu = (struct cxl_afu *)phb->private_data;
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if (cxl_pcie_cfg_record(bus->number, devfn) > afu->crs_num)
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record = cxl_pcie_cfg_record(bus->number, devfn);
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if (record > afu->crs_num)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (offset >= (unsigned long)phb->cfg_data)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = cxl_pcie_cfg_addr(phb, bus->number, devfn, offset);
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*ioaddr = (void *)(addr & ~0x3ULL);
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*shift = ((addr & 0x3) * 8);
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switch (len) {
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case 1:
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*mask = 0xff;
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break;
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case 2:
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*mask = 0xffff;
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break;
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default:
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*mask = 0xffffffff;
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break;
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}
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*_afu = afu;
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*_record = record;
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return 0;
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}
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static inline bool cxl_config_link_ok(struct pci_bus *bus)
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{
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struct pci_controller *phb;
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struct cxl_afu *afu;
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/* Config space IO is based on phb->cfg_addr, which is based on
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* afu_desc_mmio. This isn't safe to read/write when the link
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* goes down, as EEH tears down MMIO space.
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*
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* Check if the link is OK before proceeding.
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*/
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phb = pci_bus_to_host(bus);
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if (phb == NULL)
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return false;
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afu = (struct cxl_afu *)phb->private_data;
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return cxl_ops->link_ok(afu->adapter);
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}
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static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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volatile void __iomem *ioaddr;
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int shift, rc;
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u32 mask;
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int rc, record;
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struct cxl_afu *afu;
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u8 val8;
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u16 val16;
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u32 val32;
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rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
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&mask, &shift);
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rc = cxl_pcie_config_info(bus, devfn, &afu, &record);
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if (rc)
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return rc;
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if (!cxl_config_link_ok(bus))
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switch (len) {
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case 1:
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rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8);
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*val = val8;
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break;
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case 2:
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rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16);
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*val = val16;
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break;
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case 4:
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rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32);
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*val = val32;
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break;
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default:
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WARN_ON(1);
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}
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if (rc)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Can only read 32 bits */
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*val = (in_le32(ioaddr) >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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volatile void __iomem *ioaddr;
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u32 v, mask;
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int shift, rc;
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int rc, record;
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struct cxl_afu *afu;
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rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
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&mask, &shift);
|
||||
rc = cxl_pcie_config_info(bus, devfn, &afu, &record);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (!cxl_config_link_ok(bus))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
switch (len) {
|
||||
case 1:
|
||||
rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff);
|
||||
break;
|
||||
case 2:
|
||||
rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff);
|
||||
break;
|
||||
case 4:
|
||||
rc = cxl_ops->afu_cr_write32(afu, record, offset, val);
|
||||
break;
|
||||
default:
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
/* Can only write 32 bits so do read-modify-write */
|
||||
mask <<= shift;
|
||||
val <<= shift;
|
||||
if (rc)
|
||||
return PCIBIOS_SET_FAILED;
|
||||
|
||||
v = (in_le32(ioaddr) & ~mask) | (val & mask);
|
||||
|
||||
out_le32(ioaddr, v);
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
|
|
@ -233,23 +210,31 @@ int cxl_pci_vphb_add(struct cxl_afu *afu)
|
|||
{
|
||||
struct pci_dev *phys_dev;
|
||||
struct pci_controller *phb, *phys_phb;
|
||||
struct device_node *vphb_dn;
|
||||
struct device *parent;
|
||||
|
||||
phys_dev = to_pci_dev(afu->adapter->dev.parent);
|
||||
phys_phb = pci_bus_to_host(phys_dev->bus);
|
||||
if (cpu_has_feature(CPU_FTR_HVMODE)) {
|
||||
phys_dev = to_pci_dev(afu->adapter->dev.parent);
|
||||
phys_phb = pci_bus_to_host(phys_dev->bus);
|
||||
vphb_dn = phys_phb->dn;
|
||||
parent = &phys_dev->dev;
|
||||
} else {
|
||||
vphb_dn = afu->adapter->dev.parent->of_node;
|
||||
parent = afu->adapter->dev.parent;
|
||||
}
|
||||
|
||||
/* Alloc and setup PHB data structure */
|
||||
phb = pcibios_alloc_controller(phys_phb->dn);
|
||||
|
||||
phb = pcibios_alloc_controller(vphb_dn);
|
||||
if (!phb)
|
||||
return -ENODEV;
|
||||
|
||||
/* Setup parent in sysfs */
|
||||
phb->parent = &phys_dev->dev;
|
||||
phb->parent = parent;
|
||||
|
||||
/* Setup the PHB using arch provided callback */
|
||||
phb->ops = &cxl_pcie_pci_ops;
|
||||
phb->cfg_addr = afu->native->afu_desc_mmio + afu->crs_offset;
|
||||
phb->cfg_data = (void *)(u64)afu->crs_len;
|
||||
phb->cfg_addr = NULL;
|
||||
phb->cfg_data = 0;
|
||||
phb->private_data = afu;
|
||||
phb->controller_ops = cxl_pci_controller_ops;
|
||||
|
||||
|
|
@ -272,15 +257,6 @@ int cxl_pci_vphb_add(struct cxl_afu *afu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void cxl_pci_vphb_reconfigure(struct cxl_afu *afu)
|
||||
{
|
||||
/* When we are reconfigured, the AFU's MMIO space is unmapped
|
||||
* and remapped. We need to reflect this in the PHB's view of
|
||||
* the world.
|
||||
*/
|
||||
afu->phb->cfg_addr = afu->native->afu_desc_mmio + afu->crs_offset;
|
||||
}
|
||||
|
||||
void cxl_pci_vphb_remove(struct cxl_afu *afu)
|
||||
{
|
||||
struct pci_controller *phb;
|
||||
|
|
|
|||
|
|
@ -210,4 +210,9 @@ ssize_t cxl_fd_read(struct file *file, char __user *buf, size_t count,
|
|||
void cxl_perst_reloads_same_image(struct cxl_afu *afu,
|
||||
bool perst_reloads_same_image);
|
||||
|
||||
/*
|
||||
* Read the VPD for the card where the AFU resides
|
||||
*/
|
||||
ssize_t cxl_read_adapter_vpd(struct pci_dev *dev, void *buf, size_t count);
|
||||
|
||||
#endif /* _MISC_CXL_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue