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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable

This commit is contained in:
Russell King 2009-11-24 10:00:10 +00:00
parent 78d7530ac3 4998f1a30c
commit d5b7d8c226
43 changed files with 2933 additions and 519 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-mx2/Kconfig
View File

@ -6,11 +6,13 @@ choice
config MACH_MX21
bool "i.MX21 support"
select ARCH_MXC_AUDMUX_V1
help
This enables support for Freescale's MX2 based i.MX21 processor.
config MACH_MX27
bool "i.MX27 support"
select ARCH_MXC_AUDMUX_V1
help
This enables support for Freescale's MX2 based i.MX27 processor.

4
arch/arm/mach-mx2/clock_imx27.c
View File

@ -651,8 +651,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
_REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
_REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
_REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
_REGISTER_CLOCK(NULL, "vpu", vpu_clk)
_REGISTER_CLOCK(NULL, "dma", dma_clk)

78
arch/arm/mach-mx2/devices.c
View File

@ -530,6 +530,84 @@ struct platform_device mxc_usbh2 = {
};
#endif
static struct resource imx_ssi_resources0[] = {
{
.start = SSI1_BASE_ADDR,
.end = SSI1_BASE_ADDR + 0x6F,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_SSI1,
.end = MXC_INT_SSI1,
.flags = IORESOURCE_IRQ,
}, {
.name = "tx0",
.start = DMA_REQ_SSI1_TX0,
.end = DMA_REQ_SSI1_TX0,
.flags = IORESOURCE_DMA,
}, {
.name = "rx0",
.start = DMA_REQ_SSI1_RX0,
.end = DMA_REQ_SSI1_RX0,
.flags = IORESOURCE_DMA,
}, {
.name = "tx1",
.start = DMA_REQ_SSI1_TX1,
.end = DMA_REQ_SSI1_TX1,
.flags = IORESOURCE_DMA,
}, {
.name = "rx1",
.start = DMA_REQ_SSI1_RX1,
.end = DMA_REQ_SSI1_RX1,
.flags = IORESOURCE_DMA,
},
};
static struct resource imx_ssi_resources1[] = {
{
.start = SSI2_BASE_ADDR,
.end = SSI2_BASE_ADDR + 0x6F,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_SSI2,
.end = MXC_INT_SSI2,
.flags = IORESOURCE_IRQ,
}, {
.name = "tx0",
.start = DMA_REQ_SSI2_TX0,
.end = DMA_REQ_SSI2_TX0,
.flags = IORESOURCE_DMA,
}, {
.name = "rx0",
.start = DMA_REQ_SSI2_RX0,
.end = DMA_REQ_SSI2_RX0,
.flags = IORESOURCE_DMA,
}, {
.name = "tx1",
.start = DMA_REQ_SSI2_TX1,
.end = DMA_REQ_SSI2_TX1,
.flags = IORESOURCE_DMA,
}, {
.name = "rx1",
.start = DMA_REQ_SSI2_RX1,
.end = DMA_REQ_SSI2_RX1,
.flags = IORESOURCE_DMA,
},
};
struct platform_device imx_ssi_device0 = {
.name = "imx-ssi",
.id = 0,
.num_resources = ARRAY_SIZE(imx_ssi_resources0),
.resource = imx_ssi_resources0,
};
struct platform_device imx_ssi_device1 = {
.name = "imx-ssi",
.id = 1,
.num_resources = ARRAY_SIZE(imx_ssi_resources1),
.resource = imx_ssi_resources1,
};
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
{

3
arch/arm/mach-mx2/devices.h
View File

@ -26,4 +26,5 @@ extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_spi_device0;
extern struct platform_device mxc_spi_device1;
extern struct platform_device mxc_spi_device2;
extern struct platform_device imx_ssi_device0;
extern struct platform_device imx_ssi_device1;

2
arch/arm/mach-mx2/pca100.c
View File

@ -237,7 +237,7 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx27_map_io,
.init_irq = mxc_init_irq,
.init_irq = mx27_init_irq,
.init_machine = pca100_init,
.timer = &pca100_timer,
MACHINE_END

3
arch/arm/mach-mx3/Kconfig
View File

@ -2,11 +2,13 @@ if ARCH_MX3
config ARCH_MX31
select ARCH_HAS_RNGA
select ARCH_MXC_AUDMUX_V2
bool
config ARCH_MX35
bool
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
comment "MX3 platforms:"
@ -61,6 +63,7 @@ config MACH_MX31_3DS
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
select ARCH_MX31
select MXC_ULPI
help
Include support for mx31moboard platform. This includes specific
configurations for the board and its peripherals.

4
arch/arm/mach-mx3/Makefile
View File

@ -4,12 +4,12 @@
# Object file lists.
obj-y := mm.o devices.o
obj-y := mm.o devices.o cpu.o
obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o
obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o
obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o

60
arch/arm/mach-mx3/armadillo5x0.c
View File

@ -33,6 +33,9 @@
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -97,6 +100,47 @@ static int armadillo5x0_pins[] = {
MX31_PIN_FPSHIFT__FPSHIFT,
MX31_PIN_DRDY0__DRDY0,
IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
/* I2C2 */
MX31_PIN_CSPI2_MOSI__SCL,
MX31_PIN_CSPI2_MISO__SDA,
};
/* RTC over I2C*/
#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
static struct i2c_board_info armadillo5x0_i2c_rtc = {
I2C_BOARD_INFO("s35390a", 0x30),
};
/* GPIO BUTTONS */
static struct gpio_keys_button armadillo5x0_buttons[] = {
{
.code = KEY_ENTER, /*28*/
.gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0),
.active_low = 1,
.desc = "menu",
.wakeup = 1,
}, {
.code = KEY_BACK, /*158*/
.gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0),
.active_low = 1,
.desc = "back",
.wakeup = 1,
}
};
static struct gpio_keys_platform_data armadillo5x0_button_data = {
.buttons = armadillo5x0_buttons,
.nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
};
static struct platform_device armadillo5x0_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &armadillo5x0_button_data,
}
};
/*
@ -278,7 +322,7 @@ static struct resource armadillo5x0_smc911x_resources[] = {
};
static struct smsc911x_platform_config smsc911x_info = {
.flags = SMSC911X_USE_32BIT,
.flags = SMSC911X_USE_16BIT,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
};
@ -300,6 +344,8 @@ static struct imxuart_platform_data uart_pdata = {
static struct platform_device *devices[] __initdata = {
&armadillo5x0_smc911x_device,
&mxc_i2c_device1,
&armadillo5x0_button_device,
};
/*
@ -335,6 +381,18 @@ static void __init armadillo5x0_init(void)
/* set NAND page size to 2k if not configured via boot mode pins */
__raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
/* RTC */
/* Get RTC IRQ and register the chip */
if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) {
if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0)
armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO);
else
gpio_free(ARMADILLO5X0_RTC_GPIO);
}
if (armadillo5x0_i2c_rtc.irq == 0)
pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
}
static void __init armadillo5x0_timer_init(void)

41
arch/arm/mach-mx3/clock-imx35.c
View File

@ -335,7 +335,7 @@ static void clk_cgr_disable(struct clk *clk)
DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL);
DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL);
DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL);
/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */
DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL);
DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL);
@ -381,12 +381,41 @@ DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL);
DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
static int clk_dummy_enable(struct clk *clk)
{
return 0;
}
static void clk_dummy_disable(struct clk *clk)
{
}
static unsigned long get_rate_nfc(struct clk *clk)
{
unsigned long div1;
div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
return get_rate_ahb(NULL) / div1;
}
/* NAND Controller: It seems it can't be disabled */
static struct clk nfc_clk = {
.id = 0,
.enable_reg = 0,
.enable_shift = 0,
.get_rate = get_rate_nfc,
.set_rate = NULL, /* set_rate_nfc, */
.enable = clk_dummy_enable,
.disable = clk_dummy_disable
};
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
@ -397,7 +426,6 @@ DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "asrc", asrc_clk)
_REGISTER_CLOCK(NULL, "ata", ata_clk)
_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
_REGISTER_CLOCK(NULL, "can", can1_clk)
_REGISTER_CLOCK(NULL, "can", can2_clk)
_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
@ -434,8 +462,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "sdma", sdma_clk)
_REGISTER_CLOCK(NULL, "spba", spba_clk)
_REGISTER_CLOCK(NULL, "spdif", spdif_clk)
_REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
_REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
@ -445,10 +473,11 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "max", max_clk)
_REGISTER_CLOCK(NULL, "admux", admux_clk)
_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
_REGISTER_CLOCK(NULL, "csi", csi_clk)
_REGISTER_CLOCK(NULL, "iim", iim_clk)
_REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
};
int __init mx35_clocks_init()

6
arch/arm/mach-mx3/clock.c
View File

@ -558,8 +558,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
_REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
_REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK(NULL, "firi", firi_clk)
_REGISTER_CLOCK(NULL, "ata", ata_clk)
_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
@ -616,6 +616,8 @@ int __init mx31_clocks_init(unsigned long fref)
clk_enable(&serial_pll_clk);
mx31_read_cpu_rev();
if (mx31_revision() >= CHIP_REV_2_0) {
reg = __raw_readl(MXC_CCM_PMCR1);
/* No PLL restart on DVFS switch; enable auto EMI handshake */

57
arch/arm/mach-mx3/cpu.c Normal file
View File

@ -0,0 +1,57 @@
/*
* MX3 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/iim.h>
unsigned int mx31_cpu_rev;
EXPORT_SYMBOL(mx31_cpu_rev);
struct mx3_cpu_type {
u8 srev;
const char *name;
const char *v;
unsigned int rev;
};
static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = CHIP_REV_1_0 },
{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = CHIP_REV_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = CHIP_REV_1_1 },
{ .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = CHIP_REV_1_1 },
{ .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = CHIP_REV_1_1 },
{ .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = CHIP_REV_1_2 },
{ .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = CHIP_REV_1_2 },
{ .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = CHIP_REV_2_0 },
{ .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = CHIP_REV_2_0 },
};
void __init mx31_read_cpu_rev(void)
{
u32 i, srev;
/* read SREV register from IIM module */
srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV);
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev) {
printk(KERN_INFO
"CPU identified as %s, silicon rev %s\n",
mx31_cpu_type[i].name, mx31_cpu_type[i].v);
mx31_cpu_rev = mx31_cpu_type[i].rev;
return;
}
printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
}

44
arch/arm/mach-mx3/devices.c
View File

@ -537,6 +537,44 @@ struct platform_device mxc_fec_device = {
};
#endif
static struct resource imx_ssi_resources0[] = {
{
.start = SSI1_BASE_ADDR,
.end = SSI1_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
}, {
.start = MX31_INT_SSI1,
.end = MX31_INT_SSI1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource imx_ssi_resources1[] = {
{
.start = SSI2_BASE_ADDR,
.end = SSI2_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM
}, {
.start = MX31_INT_SSI2,
.end = MX31_INT_SSI2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_ssi_device0 = {
.name = "imx-ssi",
.id = 0,
.num_resources = ARRAY_SIZE(imx_ssi_resources0),
.resource = imx_ssi_resources0,
};
struct platform_device imx_ssi_device1 = {
.name = "imx-ssi",
.id = 1,
.num_resources = ARRAY_SIZE(imx_ssi_resources1),
.resource = imx_ssi_resources1,
};
static int mx3_devices_init(void)
{
if (cpu_is_mx31()) {
@ -546,7 +584,7 @@ static int mx3_devices_init(void)
}
if (cpu_is_mx35()) {
mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
otg_resources[0].start = MX35_OTG_BASE_ADDR;
otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
otg_resources[1].start = MXC_INT_USBOTG;
@ -555,6 +593,10 @@ static int mx3_devices_init(void)
mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
mxc_usbh1_resources[1].start = MXC_INT_USBHS;
mxc_usbh1_resources[1].end = MXC_INT_USBHS;
imx_ssi_resources0[1].start = MX35_INT_SSI1;
imx_ssi_resources0[1].end = MX35_INT_SSI1;
imx_ssi_resources1[1].start = MX35_INT_SSI2;
imx_ssi_resources1[1].end = MX35_INT_SSI2;
}
return 0;

2
arch/arm/mach-mx3/devices.h
View File

@ -23,4 +23,6 @@ extern struct platform_device mxc_rnga_device;
extern struct platform_device mxc_spi_device0;
extern struct platform_device mxc_spi_device1;
extern struct platform_device mxc_spi_device2;
extern struct platform_device imx_ssi_device0;
extern struct platform_device imx_ssi_device1;

10
arch/arm/mach-mx3/mx31lilly-db.c
View File

@ -109,6 +109,9 @@ static int mxc_mmc1_get_ro(struct device *dev)
static int gpio_det, gpio_wp;
#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
static int mxc_mmc1_init(struct device *dev,
irq_handler_t detect_irq, void *data)
{
@ -117,6 +120,13 @@ static int mxc_mmc1_init(struct device *dev,
gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
ret = gpio_request(gpio_det, "MMC detect");
if (ret)
return ret;

57
arch/arm/mach-mx3/mx31lilly.c
View File

@ -31,6 +31,8 @@
#include <linux/interrupt.h>
#include <linux/smsc911x.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13783.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -41,6 +43,7 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lilly.h>
#include <mach/spi.h>
#include "devices.h"
@ -108,7 +111,36 @@ static struct platform_device physmap_flash_device = {
static struct platform_device *devices[] __initdata = {
&smsc91x_device,
&physmap_flash_device,
&mxc_i2c_device1,
};
/* SPI */
static int spi_internal_chipselect[] = {
MXC_SPI_CS(0),
MXC_SPI_CS(1),
MXC_SPI_CS(2),
};
static struct spi_imx_master spi0_pdata = {
.chipselect = spi_internal_chipselect,
.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
};
static struct spi_imx_master spi1_pdata = {
.chipselect = spi_internal_chipselect,
.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
};
static struct mc13783_platform_data mc13783_pdata __initdata = {
.flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN,
};
static struct spi_board_info mc13783_dev __initdata = {
.modalias = "mc13783",
.max_speed_hz = 1000000,
.bus_num = 1,
.chip_select = 0,
.platform_data = &mc13783_pdata,
};
static int mx31lilly_baseboard;
@ -128,8 +160,27 @@ static void __init mx31lilly_board_init(void)
}
mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__SCL, "I2C SCL");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__SDA, "I2C SDA");
/* SPI */
mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
mxc_register_device(&mxc_spi_device0, &spi0_pdata);
mxc_register_device(&mxc_spi_device1, &spi1_pdata);
spi_register_board_info(&mc13783_dev, 1);
platform_add_devices(devices, ARRAY_SIZE(devices));
}

198
arch/arm/mach-mx3/mx31lite-db.c Normal file
View File

@ -0,0 +1,198 @@
/*
* LogicPD i.MX31 SOM-LV development board support
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
* based on code for other MX31 boards,
*
* Copyright 2005-2007 Freescale Semiconductor
* Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
* Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lite.h>
#include <mach/mmc.h>
#include <mach/spi.h>
#include "devices.h"
/*
* This file contains board-specific initialization routines for the
* LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
* If you design an own baseboard for the module, use this file as base
* for support code.
*/
static unsigned int litekit_db_board_pins[] __initdata = {
/* UART1 */
MX31_PIN_CTS1__CTS1,
MX31_PIN_RTS1__RTS1,
MX31_PIN_TXD1__TXD1,
MX31_PIN_RXD1__RXD1,
/* SPI 0 */
MX31_PIN_CSPI1_SCLK__SCLK,
MX31_PIN_CSPI1_MOSI__MOSI,
MX31_PIN_CSPI1_MISO__MISO,
MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
MX31_PIN_CSPI1_SS0__SS0,
MX31_PIN_CSPI1_SS1__SS1,
MX31_PIN_CSPI1_SS2__SS2,
};
/* UART */
static struct imxuart_platform_data uart_pdata __initdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
/* MMC */
static int gpio_det, gpio_wp;
#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
static int mxc_mmc1_get_ro(struct device *dev)
{
return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
}
static int mxc_mmc1_init(struct device *dev,
irq_handler_t detect_irq, void *data)
{
int ret;
gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
ret = gpio_request(gpio_det, "MMC detect");
if (ret)
return ret;
ret = gpio_request(gpio_wp, "MMC w/p");
if (ret)
goto exit_free_det;
gpio_direction_input(gpio_det);
gpio_direction_input(gpio_wp);
ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC detect", data);
if (ret)
goto exit_free_wp;
return 0;
exit_free_wp:
gpio_free(gpio_wp);
exit_free_det:
gpio_free(gpio_det);
return ret;
}
static void mxc_mmc1_exit(struct device *dev, void *data)
{
gpio_free(gpio_det);
gpio_free(gpio_wp);
free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
}
static struct imxmmc_platform_data mmc_pdata = {
.get_ro = mxc_mmc1_get_ro,
.init = mxc_mmc1_init,
.exit = mxc_mmc1_exit,
};
/* SPI */
static int spi_internal_chipselect[] = {
MXC_SPI_CS(0),
MXC_SPI_CS(1),
MXC_SPI_CS(2),
};
static struct spi_imx_master spi0_pdata = {
.chipselect = spi_internal_chipselect,
.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
};
/* GPIO LEDs */
static struct gpio_led litekit_leds[] = {
{
.name = "GPIO0",
.gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
.active_low = 1,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
{
.name = "GPIO1",
.gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
.active_low = 1,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
}
};
static struct gpio_led_platform_data litekit_led_platform_data = {
.leds = litekit_leds,
.num_leds = ARRAY_SIZE(litekit_leds),
};
static struct platform_device litekit_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &litekit_led_platform_data,
},
};
void __init mx31lite_db_init(void)
{
mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
ARRAY_SIZE(litekit_db_board_pins),
"development board pins");
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
mxc_register_device(&mxc_spi_device0, &spi0_pdata);
platform_device_register(&litekit_led_device);
}

175
arch/arm/mach-mx3/mx31lite.c
View File

@ -2,6 +2,7 @@
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -25,38 +26,47 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/mtd/physmap.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/board-mx31lite.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/irqs.h>
#include <mach/mxc_nand.h>
#include <mach/spi.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices.h"
/*
* This file contains the board-specific initialization routines.
* This file contains the module-specific initialization routines.
*/
static unsigned int mx31lite_pins[] = {
/* UART1 */
MX31_PIN_CTS1__CTS1,
MX31_PIN_RTS1__RTS1,
MX31_PIN_TXD1__TXD1,
MX31_PIN_RXD1__RXD1,
/* LAN9117 IRQ pin */
IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
};
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
/* SPI 1 */
MX31_PIN_CSPI2_SCLK__SCLK,
MX31_PIN_CSPI2_MOSI__MOSI,
MX31_PIN_CSPI2_MISO__MISO,
MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
MX31_PIN_CSPI2_SS0__SS0,
MX31_PIN_CSPI2_SS1__SS1,
MX31_PIN_CSPI2_SS2__SS2,
};
static struct mxc_nand_platform_data mx31lite_nand_board_info = {
@ -92,6 +102,111 @@ static struct platform_device smsc911x_device = {
},
};
/*
* SPI
*
* The MC13783 is the only hard-wired SPI device on the module.
*/
static int spi_internal_chipselect[] = {
MXC_SPI_CS(0),
};
static struct spi_imx_master spi1_pdata = {
.chipselect = spi_internal_chipselect,
.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
};
static struct mc13783_platform_data mc13783_pdata __initdata = {
.flags = MC13783_USE_RTC |
MC13783_USE_REGULATOR,
};
static struct spi_board_info mc13783_spi_dev __initdata = {
.modalias = "mc13783",
.max_speed_hz = 1000000,
.bus_num = 1,
.chip_select = 0,
.platform_data = &mc13783_pdata,
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
};
/*
* USB
*/
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
static int usbh2_init(struct platform_device *pdev)
{
int pins[] = {
MX31_PIN_USBH2_DATA0__USBH2_DATA0,
MX31_PIN_USBH2_DATA1__USBH2_DATA1,
MX31_PIN_USBH2_CLK__USBH2_CLK,
MX31_PIN_USBH2_DIR__USBH2_DIR,
MX31_PIN_USBH2_NXT__USBH2_NXT,
MX31_PIN_USBH2_STP__USBH2_STP,
};
mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
mxc_iomux_set_gpr(MUX_PGP_UH2, true);
/* chip select */
mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
"USBH2_CS");
gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
return 0;
}
static struct mxc_usbh_platform_data usbh2_pdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
/*
* NOR flash
*/
static struct physmap_flash_data nor_flash_data = {
.width = 2,
};
static struct resource nor_flash_resource = {
.start = 0xa0000000,
.end = 0xa1ffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device physmap_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &nor_flash_data,
},
.resource = &nor_flash_resource,
.num_resources = 1,
};
/*
* This structure defines the MX31 memory map.
*/
@ -118,19 +233,40 @@ void __init mx31lite_map_io(void)
iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
}
/*
* Board specific initialization.
*/
static int mx31lite_baseboard;
core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
static void __init mxc_board_init(void)
{
int ret;
switch (mx31lite_baseboard) {
case MX31LITE_NOBOARD:
break;
case MX31LITE_DB:
mx31lite_db_init();
break;
default:
printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
mx31lite_baseboard);
}
mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
"mx31lite");
mxc_register_device(&mxc_uart_device0, &uart_pdata);
/* NOR and NAND flash */
platform_device_register(&physmap_flash_device);
mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
mxc_register_device(&mxc_spi_device1, &spi1_pdata);
spi_register_board_info(&mc13783_spi_dev, 1);
/* USB */
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
/* SMSC9117 IRQ pin */
ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
if (ret)
@ -150,12 +286,7 @@ struct sys_timer mx31lite_timer = {
.init = mx31lite_timer_init,
};
/*
* The following uses standard kernel macros defined in arch.h in order to
* initialize __mach_desc_MX31LITE data structure.
*/
MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
/* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,

86
arch/arm/mach-mx3/mx31moboard-devboard.c
View File

@ -22,11 +22,15 @@
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/usb/otg.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices.h"
@ -39,6 +43,12 @@ static unsigned int devboard_pins[] = {
MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
/* USB H1 */
MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
};
static struct imxuart_platform_data uart_pdata = {
@ -98,6 +108,80 @@ static struct imxmmc_platform_data sdhc2_pdata = {
.exit = devboard_sdhc2_exit,
};
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
static int devboard_usbh1_hw_init(struct platform_device *pdev)
{
mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
return 0;
}
#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
static int devboard_isp1105_init(struct otg_transceiver *otg)
{
int ret = gpio_request(USBH1_MODE, "usbh1-mode");
if (ret)
return ret;
/* single ended */
gpio_direction_output(USBH1_MODE, 0);
ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
if (ret) {
gpio_free(USBH1_MODE);
return ret;
}
gpio_direction_output(USBH1_VBUSEN_B, 1);
return 0;
}
static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
{
if (on)
gpio_set_value(USBH1_VBUSEN_B, 0);
else
gpio_set_value(USBH1_VBUSEN_B, 1);
return 0;
}
static struct mxc_usbh_platform_data usbh1_pdata = {
.init = devboard_usbh1_hw_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
};
static int __init devboard_usbh1_init(void)
{
struct otg_transceiver *otg;
otg = kzalloc(sizeof(*otg), GFP_KERNEL);
if (!otg)
return -ENOMEM;
otg->label = "ISP1105";
otg->init = devboard_isp1105_init;
otg->set_vbus = devboard_isp1105_set_vbus;
usbh1_pdata.otg = otg;
return mxc_register_device(&mx31_usbh1, &usbh1_pdata);
}
/*
* system init for baseboard usage. Will be called by mx31moboard init.
*/
@ -111,4 +195,6 @@ void __init mx31moboard_devboard_init(void)
mxc_register_device(&mxc_uart_device1, &uart_pdata);
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
devboard_usbh1_init();
}

192
arch/arm/mach-mx3/mx31moboard-marxbot.c
View File

@ -16,17 +16,26 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/usb/otg.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
#include "devices.h"
@ -37,7 +46,6 @@ static unsigned int marxbot_pins[] = {
MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
/* CSI */
MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
@ -45,10 +53,19 @@ static unsigned int marxbot_pins[] = {
MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5,
MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
MX31_PIN_TXD2__GPIO1_28,
/* dsPIC resets */
MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
/*battery detection */
MX31_PIN_LCS0__GPIO3_23,
/* USB H1 */
MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
};
#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
@ -120,6 +137,166 @@ static void dspics_resets_init(void)
}
}
static struct spi_board_info marxbot_spi_board_info[] __initdata = {
{
.modalias = "spidev",
.max_speed_hz = 300000,
.bus_num = 1,
.chip_select = 1, /* according spi1_cs[] ! */
},
};
#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4)
#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2)
static int marxbot_basecam_power(struct device *dev, int on)
{
gpio_set_value(BASECAM_POWER, !on);
return 0;
}
static int marxbot_basecam_reset(struct device *dev)
{
gpio_set_value(BASECAM_RST_B, 0);
udelay(100);
gpio_set_value(BASECAM_RST_B, 1);
return 0;
}
static struct i2c_board_info marxbot_i2c_devices[] = {
{
I2C_BOARD_INFO("mt9t031", 0x5d),
},
};
static struct soc_camera_link base_iclink = {
.bus_id = 0, /* Must match with the camera ID */
.power = marxbot_basecam_power,
.reset = marxbot_basecam_reset,
.board_info = &marxbot_i2c_devices[0],
.i2c_adapter_id = 0,
.module_name = "mt9t031",
};
static struct platform_device marxbot_camera[] = {
{
.name = "soc-camera-pdrv",
.id = 0,
.dev = {
.platform_data = &base_iclink,
},
},
};
static struct platform_device *marxbot_cameras[] __initdata = {
&marxbot_camera[0],
};
static int __init marxbot_cam_init(void)
{
int ret = gpio_request(CAM_CHOICE, "cam-choice");
if (ret)
return ret;
gpio_direction_output(CAM_CHOICE, 1);
ret = gpio_request(BASECAM_RST_B, "basecam-reset");
if (ret)
return ret;
gpio_direction_output(BASECAM_RST_B, 1);
ret = gpio_request(BASECAM_POWER, "basecam-standby");
if (ret)
return ret;
gpio_direction_output(BASECAM_POWER, 0);
ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset");
if (ret)
return ret;
gpio_direction_output(TURRETCAM_RST_B, 1);
ret = gpio_request(TURRETCAM_POWER, "turretcam-standby");
if (ret)
return ret;
gpio_direction_output(TURRETCAM_POWER, 0);
return 0;
}
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
static int marxbot_usbh1_hw_init(struct platform_device *pdev)
{
mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
return 0;
}
#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
static int marxbot_isp1105_init(struct otg_transceiver *otg)
{
int ret = gpio_request(USBH1_MODE, "usbh1-mode");
if (ret)
return ret;
/* single ended */
gpio_direction_output(USBH1_MODE, 0);
ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
if (ret) {
gpio_free(USBH1_MODE);
return ret;
}
gpio_direction_output(USBH1_VBUSEN_B, 1);
return 0;
}
static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
{
if (on)
gpio_set_value(USBH1_VBUSEN_B, 0);
else
gpio_set_value(USBH1_VBUSEN_B, 1);
return 0;
}
static struct mxc_usbh_platform_data usbh1_pdata = {
.init = marxbot_usbh1_hw_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
};
static int __init marxbot_usbh1_init(void)
{
struct otg_transceiver *otg;
otg = kzalloc(sizeof(*otg), GFP_KERNEL);
if (!otg)
return -ENOMEM;
otg->label = "ISP1105";
otg->init = marxbot_isp1105_init;
otg->set_vbus = marxbot_isp1105_set_vbus;
usbh1_pdata.otg = otg;
return mxc_register_device(&mx31_usbh1, &usbh1_pdata);
}
/*
* system init for baseboard usage. Will be called by mx31moboard init.
*/
@ -133,4 +310,17 @@ void __init mx31moboard_marxbot_init(void)
dspics_resets_init();
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
spi_register_board_info(marxbot_spi_board_info,
ARRAY_SIZE(marxbot_spi_board_info));
marxbot_cam_init();
platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras));
/* battery present pin */
gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
marxbot_usbh1_init();
}

249
arch/arm/mach-mx3/mx31moboard.c
View File

@ -17,6 +17,7 @@
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/fsl_devices.h>
#include <linux/gpio.h>
#include <linux/init.h>
@ -26,8 +27,14 @@
#include <linux/mtd/physmap.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/types.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@ -37,16 +44,20 @@
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/i2c.h>
#include <mach/mmc.h>
#include <mach/mx31.h>
#include <mach/mxc_ehci.h>
#include <mach/mx3_camera.h>
#include <mach/spi.h>
#include <mach/ulpi.h>
#include "devices.h"
static unsigned int moboard_pins[] = {
/* UART0 */
MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1,
MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
MX31_PIN_CTS1__GPIO2_7,
/* UART4 */
MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
@ -73,12 +84,31 @@ static unsigned int moboard_pins[] = {
MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
MX31_PIN_USB_OC__GPIO1_30,
/* USB H2 */
MX31_PIN_USBH2_DATA0__USBH2_DATA0,
MX31_PIN_USBH2_DATA1__USBH2_DATA1,
MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
MX31_PIN_SCK6__GPIO1_25,
/* LEDs */
MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
/* SEL */
MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
/* SPI1 */
MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
/* Atlas IRQ */
MX31_PIN_GPIO1_3__GPIO1_3,
/* SPI2 */
MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
MX31_PIN_CSPI2_SS1__CSPI3_SS1,
};
static struct physmap_flash_data mx31moboard_flash_data = {
@ -101,7 +131,18 @@ static struct platform_device mx31moboard_flash = {
.num_resources = 1,
};
static struct imxuart_platform_data uart_pdata = {
static int moboard_uart0_init(struct platform_device *pdev)
{
gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
return 0;
}
static struct imxuart_platform_data uart0_pdata = {
.init = moboard_uart0_init,
};
static struct imxuart_platform_data uart4_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
@ -113,6 +154,103 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
.bitrate = 100000,
};
static int moboard_spi1_cs[] = {
MXC_SPI_CS(0),
MXC_SPI_CS(2),
};
static struct spi_imx_master moboard_spi1_master = {
.chipselect = moboard_spi1_cs,
.num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
};
static struct regulator_consumer_supply sdhc_consumers[] = {
{
.dev = &mxcsdhc_device0.dev,
.supply = "sdhc0_vcc",
},
{
.dev = &mxcsdhc_device1.dev,
.supply = "sdhc1_vcc",
},
};
static struct regulator_init_data sdhc_vreg_data = {
.constraints = {
.min_uV = 2700000,
.max_uV = 3000000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
.valid_modes_mask = REGULATOR_MODE_NORMAL |
REGULATOR_MODE_FAST,
.always_on = 0,
.boot_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
.consumer_supplies = sdhc_consumers,
};
static struct regulator_consumer_supply cam_consumers[] = {
{
.dev = &mx3_camera.dev,
.supply = "cam_vcc",
},
};
static struct regulator_init_data cam_vreg_data = {
.constraints = {
.min_uV = 2700000,
.max_uV = 3000000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
.valid_modes_mask = REGULATOR_MODE_NORMAL |
REGULATOR_MODE_FAST,
.always_on = 0,
.boot_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(cam_consumers),
.consumer_supplies = cam_consumers,
};
static struct mc13783_regulator_init_data moboard_regulators[] = {
{
.id = MC13783_REGU_VMMC1,
.init_data = &sdhc_vreg_data,
},
{
.id = MC13783_REGU_VCAM,
.init_data = &cam_vreg_data,
},
};
static struct mc13783_platform_data moboard_pmic = {
.regulators = moboard_regulators,
.num_regulators = ARRAY_SIZE(moboard_regulators),
.flags = MC13783_USE_REGULATOR | MC13783_USE_RTC,
MC13783_USE_ADC,
};
static struct spi_board_info moboard_spi_board_info[] __initdata = {
{
.modalias = "mc13783",
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
.max_speed_hz = 300000,
.bus_num = 1,
.chip_select = 0,
.platform_data = &moboard_pmic,
.mode = SPI_CS_HIGH,
},
};
static int moboard_spi2_cs[] = {
MXC_SPI_CS(1),
};
static struct spi_imx_master moboard_spi2_master = {
.chipselect = moboard_spi2_cs,
.num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
};
#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
@ -208,6 +346,56 @@ static struct fsl_usb2_platform_data usb_pdata = {
.phy_mode = FSL_USB2_PHY_ULPI,
};
#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
static int moboard_usbh2_hw_init(struct platform_device *pdev)
{
int ret = gpio_request(USBH2_EN_B, "usbh2-en");
if (ret)
return ret;
mxc_iomux_set_gpr(MUX_PGP_UH2, true);
mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
gpio_direction_output(USBH2_EN_B, 0);
return 0;
}
static int moboard_usbh2_hw_exit(struct platform_device *pdev)
{
gpio_free(USBH2_EN_B);
return 0;
}
static struct mxc_usbh_platform_data usbh2_pdata = {
.init = moboard_usbh2_hw_init,
.exit = moboard_usbh2_hw_exit,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static int __init moboard_usbh2_init(void)
{
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
return mxc_register_device(&mx31_usbh2, &usbh2_pdata);
}
static struct gpio_led mx31moboard_leds[] = {
{
.name = "coreboard-led-0:red:running",
@ -266,11 +454,48 @@ static void mx31moboard_init_sel_gpios(void)
}
}
static struct ipu_platform_data mx3_ipu_data = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct platform_device *devices[] __initdata = {
&mx31moboard_flash,
&mx31moboard_leds_device,
};
static struct mx3_camera_pdata camera_pdata = {
.dma_dev = &mx3_ipu.dev,
.flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 4800,
};
#define CAMERA_BUF_SIZE (4*1024*1024)
static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
{
dma_addr_t dma_handle;
void *buf;
int dma;
if (buf_size < 2 * 1024 * 1024)
return -EINVAL;
buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
if (!buf) {
pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
return -ENOMEM;
}
memset(buf, 0, buf_size);
dma = dma_declare_coherent_memory(&mx3_camera.dev,
dma_handle, dma_handle, buf_size,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
/* The way we call dma_declare_coherent_memory only a malloc can fail */
return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
}
static int mx31moboard_baseboard;
core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
@ -284,20 +509,34 @@ static void __init mxc_board_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_uart_device4, &uart_pdata);
mxc_register_device(&mxc_uart_device0, &uart0_pdata);
mxc_register_device(&mxc_uart_device4, &uart4_pdata);
mx31moboard_init_sel_gpios();
mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(moboard_spi_board_info,
ARRAY_SIZE(moboard_spi_board_info));
mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
mxc_register_device(&mx3_camera, &camera_pdata);
usb_xcvr_reset();
moboard_usbotg_init();
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
moboard_usbh2_init();
switch (mx31moboard_baseboard) {
case MX31NOBOARD:

7
arch/arm/mach-mx3/pcm043.c
View File

@ -43,6 +43,7 @@
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mxc_nand.h>
#include "devices.h"
@ -206,6 +207,11 @@ static struct pad_desc pcm043_pads[] = {
MX35_PAD_ATA_CS0__GPIO2_6,
};
static struct mxc_nand_platform_data pcm037_nand_board_info = {
.width = 1,
.hw_ecc = 1,
};
/*
* Board specific initialization.
*/
@ -216,6 +222,7 @@ static void __init mxc_board_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
mxc_register_device(&mxc_uart_device1, &uart_pdata);

10
arch/arm/plat-mxc/Kconfig
View File

@ -69,10 +69,20 @@ config MXC_PWM
help
Enable support for the i.MX PWM controller(s).
config MXC_ULPI
bool
config ARCH_HAS_RNGA
bool
depends on ARCH_MXC
config ARCH_MXC_IOMUX_V3
bool
config ARCH_MXC_AUDMUX_V1
bool
config ARCH_MXC_AUDMUX_V2
bool
endif

3
arch/arm/plat-mxc/Makefile
View File

@ -9,3 +9,6 @@ obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
obj-$(CONFIG_MXC_PWM) += pwm.o
obj-$(CONFIG_MXC_ULPI) += ulpi.o
obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o

53
arch/arm/plat-mxc/audmux-v1.c Normal file
View File

@ -0,0 +1,53 @@
/*
* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* Initial development of this code was funded by
* Phytec Messtechnik GmbH, http://www.phytec.de
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <mach/audmux.h>
#include <mach/hardware.h>
static void __iomem *audmux_base;
#define MXC_AUDMUX_V1_PCR(x) ((x) * 4)
int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
{
if (!audmux_base) {
printk("%s: not configured\n", __func__);
return -ENOSYS;
}
writel(pcr, audmux_base + MXC_AUDMUX_V1_PCR(port));
return 0;
}
EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
static int mxc_audmux_v1_init(void)
{
if (cpu_is_mx27() || cpu_is_mx21())
audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
return 0;
}
postcore_initcall(mxc_audmux_v1_init);

74
arch/arm/plat-mxc/audmux-v2.c Normal file
View File

@ -0,0 +1,74 @@
/*
* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* Initial development of this code was funded by
* Phytec Messtechnik GmbH, http://www.phytec.de
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <mach/audmux.h>
#include <mach/hardware.h>
static struct clk *audmux_clk;
static void __iomem *audmux_base;
#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8)
#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
unsigned int pdcr)
{
if (!audmux_base)
return -ENOSYS;
if (audmux_clk)
clk_enable(audmux_clk);
writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
if (audmux_clk)
clk_disable(audmux_clk);
return 0;
}
EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
static int mxc_audmux_v2_init(void)
{
int ret;
if (cpu_is_mx35()) {
audmux_clk = clk_get(NULL, "audmux");
if (IS_ERR(audmux_clk)) {
ret = PTR_ERR(audmux_clk);
printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
ret);
return ret;
}
}
if (cpu_is_mx31() || cpu_is_mx35())
audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
return 0;
}
postcore_initcall(mxc_audmux_v2_init);

3
arch/arm/plat-mxc/dma-mx1-mx2.c
View File

@ -156,7 +156,8 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
}
now = min(imxdma->resbytes, sg->length);
imxdma->resbytes -= now;
if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
imxdma->resbytes -= now;
if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
__raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));

2
arch/arm/plat-mxc/gpio.c
View File

@ -282,7 +282,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
for (j = port[i].virtual_irq_start;
j < port[i].virtual_irq_start + 32; j++) {
set_irq_chip(j, &gpio_irq_chip);
set_irq_handler(j, handle_edge_irq);
set_irq_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}

52
arch/arm/plat-mxc/include/mach/audmux.h Normal file
View File

@ -0,0 +1,52 @@
#ifndef __MACH_AUDMUX_H
#define __MACH_AUDMUX_H
#define MX27_AUDMUX_HPCR1_SSI0 0
#define MX27_AUDMUX_HPCR2_SSI1 1
#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2
#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3
#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4
#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5
#define MX31_AUDMUX_PORT1_SSI0 0
#define MX31_AUDMUX_PORT2_SSI1 1
#define MX31_AUDMUX_PORT3_SSI_PINS_3 2
#define MX31_AUDMUX_PORT4_SSI_PINS_4 3
#define MX31_AUDMUX_PORT5_SSI_PINS_5 4
#define MX31_AUDMUX_PORT6_SSI_PINS_6 5
/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
#define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff)
#define MXC_AUDMUX_V1_PCR_INMEN (1 << 8)
#define MXC_AUDMUX_V1_PCR_TXRXEN (1 << 10)
#define MXC_AUDMUX_V1_PCR_SYN (1 << 12)
#define MXC_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13)
#define MXC_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20)
#define MXC_AUDMUX_V1_PCR_RCLKDIR (1 << 24)
#define MXC_AUDMUX_V1_PCR_RFSDIR (1 << 25)
#define MXC_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26)
#define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30)
#define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31)
/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */
#define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31)
#define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27)
#define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26)
#define MXC_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22)
#define MXC_AUDMUX_V2_PTCR_RFSDIR (1 << 21)
#define MXC_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17)
#define MXC_AUDMUX_V2_PTCR_RCLKDIR (1 << 16)
#define MXC_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12)
#define MXC_AUDMUX_V2_PTCR_SYN (1 << 11)
#define MXC_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13)
#define MXC_AUDMUX_V2_PDCR_TXRXEN (1 << 12)
#define MXC_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8)
#define MXC_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff)
int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
unsigned int pdcr);
#endif /* __MACH_AUDMUX_H */

41
arch/arm/plat-mxc/include/mach/board-mx31lite.h
View File

@ -1,15 +1,42 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
*
* Based on code for mobots boards,
* Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
#ifndef __ASSEMBLY__
enum mx31lilly_boards {
MX31LITE_NOBOARD = 0,
MX31LITE_DB = 1,
};
/*
* This CPU module needs a baseboard to work. After basic initializing
* its own devices, it calls baseboard's init function.
*/
extern void mx31lite_db_init(void);
#endif
#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */

8
arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
View File

@ -58,6 +58,14 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address,
unsigned int dma_length, unsigned int dev_addr,
unsigned int dmamode);
/*
* Use this flag as the dma_length argument to imx_dma_setup_sg()
* to create an endless running dma loop. The end of the scatterlist
* must be linked to the beginning for this to work.
*/
#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
int
imx_dma_setup_sg(int channel, struct scatterlist *sg,
unsigned int sgcount, unsigned int dma_length,

26
arch/arm/plat-mxc/include/mach/iomux-mx3.h
View File

@ -623,6 +623,8 @@ enum iomux_pins {
#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
@ -642,12 +644,22 @@ enum iomux_pins {
#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@ -693,7 +705,19 @@ enum iomux_pins {
#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
* cspi1_ss1*/

17
arch/arm/plat-mxc/include/mach/iomux-v3.h
View File

@ -88,9 +88,7 @@ struct pad_desc {
#define PAD_CTL_SRE_FAST (1 << 0)
/*
* setups a single pad:
* - reserves the pad so that it is not claimed by another driver
* - setups the iomux according to the configuration
* setups a single pad in the iomuxer
*/
int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
@ -100,19 +98,6 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
*/
int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
/*
* releases a single pad:
* - make it available for a future use by another driver
* - DOES NOT reconfigure the IOMUX in its reset state
*/
void mxc_iomux_v3_release_pad(struct pad_desc *pad);
/*
* releases multiple pads
* convenvient way to call the above function with tables
*/
void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
/*
* Initialise the iomux controller
*/

209
arch/arm/plat-mxc/include/mach/mx21.h
View File

@ -25,46 +25,191 @@
#ifndef __ASM_ARCH_MXC_MX21_H__
#define __ASM_ARCH_MXC_MX21_H__
/* Memory regions and CS */
#define SDRAM_BASE_ADDR 0xC0000000
#define CSD1_BASE_ADDR 0xC4000000
#define MX21_AIPI_BASE_ADDR 0x10000000
#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
#define MX21_AIPI_SIZE SZ_1M
#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
#define CS0_BASE_ADDR 0xC8000000
#define CS1_BASE_ADDR 0xCC000000
#define CS2_BASE_ADDR 0xD0000000
#define CS3_BASE_ADDR 0xD1000000
#define CS4_BASE_ADDR 0xD2000000
#define CS5_BASE_ADDR 0xDD000000
#define PCMCIA_MEM_BASE_ADDR 0xD4000000
#define MX21_AVIC_BASE_ADDR 0x10040000
#define MX21_SAHB1_BASE_ADDR 0x80000000
#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
#define MX21_SAHB1_SIZE SZ_1M
#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
/* Memory regions and CS */
#define MX21_SDRAM_BASE_ADDR 0xc0000000
#define MX21_CSD1_BASE_ADDR 0xc4000000
#define MX21_CS0_BASE_ADDR 0xc8000000
#define MX21_CS1_BASE_ADDR 0xcc000000
#define MX21_CS2_BASE_ADDR 0xd0000000
#define MX21_CS3_BASE_ADDR 0xd1000000
#define MX21_CS4_BASE_ADDR 0xd2000000
#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
#define MX21_CS5_BASE_ADDR 0xdd000000
/* NAND, SDRAM, WEIM etc controllers */
#define X_MEMC_BASE_ADDR 0xDF000000
#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
#define X_MEMC_SIZE SZ_256K
#define MX21_X_MEMC_BASE_ADDR 0xdf000000
#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
#define MX21_X_MEMC_SIZE SZ_256K
#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
#define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
/* fixed interrupt numbers */
#define MXC_INT_USBCTRL 58
#define MXC_INT_USBCTRL 58
#define MXC_INT_USBMNP 57
#define MXC_INT_USBFUNC 56
#define MXC_INT_USBHOST 55
#define MXC_INT_USBDMA 54
#define MXC_INT_USBWKUP 53
#define MXC_INT_EMMADEC 50
#define MXC_INT_EMMAENC 49
#define MXC_INT_BMI 30
#define MXC_INT_FIRI 9
#define MX21_INT_CSPI3 6
#define MX21_INT_GPIO 8
#define MX21_INT_FIRI 9
#define MX21_INT_SDHC2 10
#define MX21_INT_SDHC1 11
#define MX21_INT_I2C 12
#define MX21_INT_SSI2 13
#define MX21_INT_SSI1 14
#define MX21_INT_CSPI2 15
#define MX21_INT_CSPI1 16
#define MX21_INT_UART4 17
#define MX21_INT_UART3 18
#define MX21_INT_UART2 19
#define MX21_INT_UART1 20
#define MX21_INT_KPP 21
#define MX21_INT_RTC 22
#define MX21_INT_PWM 23
#define MX21_INT_GPT3 24
#define MX21_INT_GPT2 25
#define MX21_INT_GPT1 26
#define MX21_INT_WDOG 27
#define MX21_INT_PCMCIA 28
#define MX21_INT_NANDFC 29
#define MX21_INT_BMI 30
#define MX21_INT_CSI 31
#define MX21_INT_DMACH0 32
#define MX21_INT_DMACH1 33
#define MX21_INT_DMACH2 34
#define MX21_INT_DMACH3 35
#define MX21_INT_DMACH4 36
#define MX21_INT_DMACH5 37
#define MX21_INT_DMACH6 38
#define MX21_INT_DMACH7 39
#define MX21_INT_DMACH8 40
#define MX21_INT_DMACH9 41
#define MX21_INT_DMACH10 42
#define MX21_INT_DMACH11 43
#define MX21_INT_DMACH12 44
#define MX21_INT_DMACH13 45
#define MX21_INT_DMACH14 46
#define MX21_INT_DMACH15 47
#define MX21_INT_EMMAENC 49
#define MX21_INT_EMMADEC 50
#define MX21_INT_EMMAPRP 51
#define MX21_INT_EMMAPP 52
#define MX21_INT_USBWKUP 53
#define MX21_INT_USBDMA 54
#define MX21_INT_USBHOST 55
#define MX21_INT_USBFUNC 56
#define MX21_INT_USBMNP 57
#define MX21_INT_USBCTRL 58
#define MX21_INT_SLCDC 60
#define MX21_INT_LCDC 61
/* fixed DMA request numbers */
#define DMA_REQ_BMI_RX 29
#define DMA_REQ_BMI_TX 28
#define DMA_REQ_FIRI_RX 4
#define MX21_DMA_REQ_CSPI3_RX 1
#define MX21_DMA_REQ_CSPI3_TX 2
#define MX21_DMA_REQ_EXT 3
#define MX21_DMA_REQ_FIRI_RX 4
#define MX21_DMA_REQ_SDHC2 6
#define MX21_DMA_REQ_SDHC1 7
#define MX21_DMA_REQ_SSI2_RX0 8
#define MX21_DMA_REQ_SSI2_TX0 9
#define MX21_DMA_REQ_SSI2_RX1 10
#define MX21_DMA_REQ_SSI2_TX1 11
#define MX21_DMA_REQ_SSI1_RX0 12
#define MX21_DMA_REQ_SSI1_TX0 13
#define MX21_DMA_REQ_SSI1_RX1 14
#define MX21_DMA_REQ_SSI1_TX1 15
#define MX21_DMA_REQ_CSPI2_RX 16
#define MX21_DMA_REQ_CSPI2_TX 17
#define MX21_DMA_REQ_CSPI1_RX 18
#define MX21_DMA_REQ_CSPI1_TX 19
#define MX21_DMA_REQ_UART4_RX 20
#define MX21_DMA_REQ_UART4_TX 21
#define MX21_DMA_REQ_UART3_RX 22
#define MX21_DMA_REQ_UART3_TX 23
#define MX21_DMA_REQ_UART2_RX 24
#define MX21_DMA_REQ_UART2_TX 25
#define MX21_DMA_REQ_UART1_RX 26
#define MX21_DMA_REQ_UART1_TX 27
#define MX21_DMA_REQ_BMI_TX 28
#define MX21_DMA_REQ_BMI_RX 29
#define MX21_DMA_REQ_CSI_STAT 30
#define MX21_DMA_REQ_CSI_RX 31
/* these should go away */
#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
#define X_MEMC_SIZE MX21_X_MEMC_SIZE
#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
#define MXC_INT_FIRI MX21_INT_FIRI
#define MXC_INT_BMI MX21_INT_BMI
#define MXC_INT_EMMAENC MX21_INT_EMMAENC
#define MXC_INT_EMMADEC MX21_INT_EMMADEC
#define MXC_INT_USBWKUP MX21_INT_USBWKUP
#define MXC_INT_USBDMA MX21_INT_USBDMA
#define MXC_INT_USBHOST MX21_INT_USBHOST
#define MXC_INT_USBFUNC MX21_INT_USBFUNC
#define MXC_INT_USBMNP MX21_INT_USBMNP
#define MXC_INT_USBCTRL MX21_INT_USBCTRL
#define MXC_INT_USBCTRL MX21_INT_USBCTRL
#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
#endif /* __ASM_ARCH_MXC_MX21_H__ */

10
arch/arm/plat-mxc/include/mach/mx25.h
View File

@ -1,14 +1,14 @@
#ifndef __MACH_MX25_H__
#define __MACH_MX25_H__
#define MX25_AIPS1_BASE_ADDR 0x43F00000
#define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000
#define MX25_AIPS1_BASE_ADDR 0x43f00000
#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX25_AIPS1_SIZE SZ_1M
#define MX25_AIPS2_BASE_ADDR 0x53F00000
#define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000
#define MX25_AIPS2_BASE_ADDR 0x53f00000
#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX25_AIPS2_SIZE SZ_1M
#define MX25_AVIC_BASE_ADDR 0x68000000
#define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000
#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX25_AVIC_SIZE SZ_1M
#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)

313
arch/arm/plat-mxc/include/mach/mx27.h
View File

@ -24,87 +24,198 @@
#ifndef __ASM_ARCH_MXC_MX27_H__
#define __ASM_ARCH_MXC_MX27_H__
/* IRAM */
#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
#define MX27_AIPI_BASE_ADDR 0x10000000
#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
#define MX27_AIPI_SIZE SZ_1M
#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR
#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000)
#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000)
#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
#define OTG_BASE_ADDR USBOTG_BASE_ADDR
#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
#define MX27_AVIC_BASE_ADDR 0x10040000
/* ROM patch */
#define ROMP_BASE_ADDR 0x10041000
#define MX27_ROMP_BASE_ADDR 0x10041000
#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
#define MX27_SAHB1_BASE_ADDR 0x80000000
#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
#define MX27_SAHB1_SIZE SZ_1M
#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
/* Memory regions and CS */
#define SDRAM_BASE_ADDR 0xA0000000
#define CSD1_BASE_ADDR 0xB0000000
#define MX27_SDRAM_BASE_ADDR 0xa0000000
#define MX27_CSD1_BASE_ADDR 0xb0000000
#define CS0_BASE_ADDR 0xC0000000
#define CS1_BASE_ADDR 0xC8000000
#define CS2_BASE_ADDR 0xD0000000
#define CS3_BASE_ADDR 0xD2000000
#define CS4_BASE_ADDR 0xD4000000
#define CS5_BASE_ADDR 0xD6000000
#define PCMCIA_MEM_BASE_ADDR 0xDC000000
#define MX27_CS0_BASE_ADDR 0xc0000000
#define MX27_CS1_BASE_ADDR 0xc8000000
#define MX27_CS2_BASE_ADDR 0xd0000000
#define MX27_CS3_BASE_ADDR 0xd2000000
#define MX27_CS4_BASE_ADDR 0xd4000000
#define MX27_CS5_BASE_ADDR 0xd6000000
/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
#define X_MEMC_BASE_ADDR 0xD8000000
#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
#define X_MEMC_SIZE SZ_1M
#define MX27_X_MEMC_BASE_ADDR 0xd8000000
#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
#define MX27_X_MEMC_SIZE SZ_1M
#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
/* IRAM */
#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
/* fixed interrupt numbers */
#define MXC_INT_CCM 63
#define MXC_INT_IIM 62
#define MXC_INT_SAHARA 59
#define MXC_INT_SCC_SCM 58
#define MXC_INT_SCC_SMN 57
#define MXC_INT_USB3 56
#define MXC_INT_USB2 55
#define MXC_INT_USB1 54
#define MXC_INT_VPU 53
#define MXC_INT_FEC 50
#define MXC_INT_UART5 49
#define MXC_INT_UART6 48
#define MXC_INT_ATA 30
#define MXC_INT_SDHC3 9
#define MXC_INT_SDHC 7
#define MXC_INT_RTIC 5
#define MXC_INT_GPT4 4
#define MXC_INT_GPT5 3
#define MXC_INT_GPT6 2
#define MXC_INT_I2C2 1
#define MX27_INT_I2C2 1
#define MX27_INT_GPT6 2
#define MX27_INT_GPT5 3
#define MX27_INT_GPT4 4
#define MX27_INT_RTIC 5
#define MX27_INT_CSPI3 6
#define MX27_INT_SDHC 7
#define MX27_INT_GPIO 8
#define MX27_INT_SDHC3 9
#define MX27_INT_SDHC2 10
#define MX27_INT_SDHC1 11
#define MX27_INT_I2C 12
#define MX27_INT_SSI2 13
#define MX27_INT_SSI1 14
#define MX27_INT_CSPI2 15
#define MX27_INT_CSPI1 16
#define MX27_INT_UART4 17
#define MX27_INT_UART3 18
#define MX27_INT_UART2 19
#define MX27_INT_UART1 20
#define MX27_INT_KPP 21
#define MX27_INT_RTC 22
#define MX27_INT_PWM 23
#define MX27_INT_GPT3 24
#define MX27_INT_GPT2 25
#define MX27_INT_GPT1 26
#define MX27_INT_WDOG 27
#define MX27_INT_PCMCIA 28
#define MX27_INT_NANDFC 29
#define MX27_INT_ATA 30
#define MX27_INT_CSI 31
#define MX27_INT_DMACH0 32
#define MX27_INT_DMACH1 33
#define MX27_INT_DMACH2 34
#define MX27_INT_DMACH3 35
#define MX27_INT_DMACH4 36
#define MX27_INT_DMACH5 37
#define MX27_INT_DMACH6 38
#define MX27_INT_DMACH7 39
#define MX27_INT_DMACH8 40
#define MX27_INT_DMACH9 41
#define MX27_INT_DMACH10 42
#define MX27_INT_DMACH11 43
#define MX27_INT_DMACH12 44
#define MX27_INT_DMACH13 45
#define MX27_INT_DMACH14 46
#define MX27_INT_DMACH15 47
#define MX27_INT_UART6 48
#define MX27_INT_UART5 49
#define MX27_INT_FEC 50
#define MX27_INT_EMMAPRP 51
#define MX27_INT_EMMAPP 52
#define MX27_INT_VPU 53
#define MX27_INT_USB1 54
#define MX27_INT_USB2 55
#define MX27_INT_USB3 56
#define MX27_INT_SCC_SMN 57
#define MX27_INT_SCC_SCM 58
#define MX27_INT_SAHARA 59
#define MX27_INT_SLCDC 60
#define MX27_INT_LCDC 61
#define MX27_INT_IIM 62
#define MX27_INT_CCM 63
/* fixed DMA request numbers */
#define DMA_REQ_NFC 37
#define DMA_REQ_SDHC3 36
#define DMA_REQ_UART6_RX 35
#define DMA_REQ_UART6_TX 34
#define DMA_REQ_UART5_RX 33
#define DMA_REQ_UART5_TX 32
#define DMA_REQ_ATA_RCV 29
#define DMA_REQ_ATA_TX 28
#define DMA_REQ_MSHC 4
#define MX27_DMA_REQ_CSPI3_RX 1
#define MX27_DMA_REQ_CSPI3_TX 2
#define MX27_DMA_REQ_EXT 3
#define MX27_DMA_REQ_MSHC 4
#define MX27_DMA_REQ_SDHC2 6
#define MX27_DMA_REQ_SDHC1 7
#define MX27_DMA_REQ_SSI2_RX0 8
#define MX27_DMA_REQ_SSI2_TX0 9
#define MX27_DMA_REQ_SSI2_RX1 10
#define MX27_DMA_REQ_SSI2_TX1 11
#define MX27_DMA_REQ_SSI1_RX0 12
#define MX27_DMA_REQ_SSI1_TX0 13
#define MX27_DMA_REQ_SSI1_RX1 14
#define MX27_DMA_REQ_SSI1_TX1 15
#define MX27_DMA_REQ_CSPI2_RX 16
#define MX27_DMA_REQ_CSPI2_TX 17
#define MX27_DMA_REQ_CSPI1_RX 18
#define MX27_DMA_REQ_CSPI1_TX 19
#define MX27_DMA_REQ_UART4_RX 20
#define MX27_DMA_REQ_UART4_TX 21
#define MX27_DMA_REQ_UART3_RX 22
#define MX27_DMA_REQ_UART3_TX 23
#define MX27_DMA_REQ_UART2_RX 24
#define MX27_DMA_REQ_UART2_TX 25
#define MX27_DMA_REQ_UART1_RX 26
#define MX27_DMA_REQ_UART1_TX 27
#define MX27_DMA_REQ_ATA_TX 28
#define MX27_DMA_REQ_ATA_RCV 29
#define MX27_DMA_REQ_CSI_STAT 30
#define MX27_DMA_REQ_CSI_RX 31
#define MX27_DMA_REQ_UART5_TX 32
#define MX27_DMA_REQ_UART5_RX 33
#define MX27_DMA_REQ_UART6_TX 34
#define MX27_DMA_REQ_UART6_RX 35
#define MX27_DMA_REQ_SDHC3 36
#define MX27_DMA_REQ_NFC 37
/* silicon revisions specific to i.MX27 */
#define CHIP_REV_1_0 0x00
@ -114,6 +225,72 @@
extern int mx27_revision(void);
#endif
/* Mandatory defines used globally */
/* these should go away */
#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
#define X_MEMC_SIZE MX27_X_MEMC_SIZE
#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
#define MXC_INT_I2C2 MX27_INT_I2C2
#define MXC_INT_GPT6 MX27_INT_GPT6
#define MXC_INT_GPT5 MX27_INT_GPT5
#define MXC_INT_GPT4 MX27_INT_GPT4
#define MXC_INT_RTIC MX27_INT_RTIC
#define MXC_INT_SDHC MX27_INT_SDHC
#define MXC_INT_SDHC3 MX27_INT_SDHC3
#define MXC_INT_ATA MX27_INT_ATA
#define MXC_INT_UART6 MX27_INT_UART6
#define MXC_INT_UART5 MX27_INT_UART5
#define MXC_INT_FEC MX27_INT_FEC
#define MXC_INT_VPU MX27_INT_VPU
#define MXC_INT_USB1 MX27_INT_USB1
#define MXC_INT_USB2 MX27_INT_USB2
#define MXC_INT_USB3 MX27_INT_USB3
#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
#define MXC_INT_SAHARA MX27_INT_SAHARA
#define MXC_INT_IIM MX27_INT_IIM
#define MXC_INT_CCM MX27_INT_CCM
#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
#define DMA_REQ_NFC MX27_DMA_REQ_NFC
#endif /* __ASM_ARCH_MXC_MX27_H__ */

335
arch/arm/plat-mxc/include/mach/mx2x.h
View File

@ -26,50 +26,48 @@
/* The following addresses are common between i.MX21 and i.MX27 */
/* Register offests */
#define AIPI_BASE_ADDR 0x10000000
#define AIPI_BASE_ADDR_VIRT 0xF4000000
#define AIPI_SIZE SZ_1M
#define MX2x_AIPI_BASE_ADDR 0x10000000
#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
#define MX2x_AIPI_SIZE SZ_1M
#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
#define MX2x_AVIC_BASE_ADDR 0x10040000
#define AVIC_BASE_ADDR 0x10040000
#define SAHB1_BASE_ADDR 0x80000000
#define SAHB1_BASE_ADDR_VIRT 0xF4100000
#define SAHB1_SIZE SZ_1M
#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
#define MX2x_SAHB1_BASE_ADDR 0x80000000
#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
#define MX2x_SAHB1_SIZE SZ_1M
#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
/*
* This macro defines the physical to virtual address mapping for all the
@ -105,78 +103,189 @@
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
/* fixed interrupt numbers */
#define MXC_INT_LCDC 61
#define MXC_INT_SLCDC 60
#define MXC_INT_EMMAPP 52
#define MXC_INT_EMMAPRP 51
#define MXC_INT_DMACH15 47
#define MXC_INT_DMACH14 46
#define MXC_INT_DMACH13 45
#define MXC_INT_DMACH12 44
#define MXC_INT_DMACH11 43
#define MXC_INT_DMACH10 42
#define MXC_INT_DMACH9 41
#define MXC_INT_DMACH8 40
#define MXC_INT_DMACH7 39
#define MXC_INT_DMACH6 38
#define MXC_INT_DMACH5 37
#define MXC_INT_DMACH4 36
#define MXC_INT_DMACH3 35
#define MXC_INT_DMACH2 34
#define MXC_INT_DMACH1 33
#define MXC_INT_DMACH0 32
#define MXC_INT_CSI 31
#define MXC_INT_NANDFC 29
#define MXC_INT_PCMCIA 28
#define MXC_INT_WDOG 27
#define MXC_INT_GPT1 26
#define MXC_INT_GPT2 25
#define MXC_INT_GPT3 24
#define MXC_INT_GPT INT_GPT1
#define MXC_INT_PWM 23
#define MXC_INT_RTC 22
#define MXC_INT_KPP 21
#define MXC_INT_UART1 20
#define MXC_INT_UART2 19
#define MXC_INT_UART3 18
#define MXC_INT_UART4 17
#define MXC_INT_CSPI1 16
#define MXC_INT_CSPI2 15
#define MXC_INT_SSI1 14
#define MXC_INT_SSI2 13
#define MXC_INT_I2C 12
#define MXC_INT_SDHC1 11
#define MXC_INT_SDHC2 10
#define MXC_INT_GPIO 8
#define MXC_INT_CSPI3 6
#define MX2x_INT_CSPI3 6
#define MX2x_INT_GPIO 8
#define MX2x_INT_SDHC2 10
#define MX2x_INT_SDHC1 11
#define MX2x_INT_I2C 12
#define MX2x_INT_SSI2 13
#define MX2x_INT_SSI1 14
#define MX2x_INT_CSPI2 15
#define MX2x_INT_CSPI1 16
#define MX2x_INT_UART4 17
#define MX2x_INT_UART3 18
#define MX2x_INT_UART2 19
#define MX2x_INT_UART1 20
#define MX2x_INT_KPP 21
#define MX2x_INT_RTC 22
#define MX2x_INT_PWM 23
#define MX2x_INT_GPT3 24
#define MX2x_INT_GPT2 25
#define MX2x_INT_GPT1 26
#define MX2x_INT_WDOG 27
#define MX2x_INT_PCMCIA 28
#define MX2x_INT_NANDFC 29
#define MX2x_INT_CSI 31
#define MX2x_INT_DMACH0 32
#define MX2x_INT_DMACH1 33
#define MX2x_INT_DMACH2 34
#define MX2x_INT_DMACH3 35
#define MX2x_INT_DMACH4 36
#define MX2x_INT_DMACH5 37
#define MX2x_INT_DMACH6 38
#define MX2x_INT_DMACH7 39
#define MX2x_INT_DMACH8 40
#define MX2x_INT_DMACH9 41
#define MX2x_INT_DMACH10 42
#define MX2x_INT_DMACH11 43
#define MX2x_INT_DMACH12 44
#define MX2x_INT_DMACH13 45
#define MX2x_INT_DMACH14 46
#define MX2x_INT_DMACH15 47
#define MX2x_INT_EMMAPRP 51
#define MX2x_INT_EMMAPP 52
#define MX2x_INT_SLCDC 60
#define MX2x_INT_LCDC 61
/* fixed DMA request numbers */
#define DMA_REQ_CSI_RX 31
#define DMA_REQ_CSI_STAT 30
#define DMA_REQ_UART1_TX 27
#define DMA_REQ_UART1_RX 26
#define DMA_REQ_UART2_TX 25
#define DMA_REQ_UART2_RX 24
#define DMA_REQ_UART3_TX 23
#define DMA_REQ_UART3_RX 22
#define DMA_REQ_UART4_TX 21
#define DMA_REQ_UART4_RX 20
#define DMA_REQ_CSPI1_TX 19
#define DMA_REQ_CSPI1_RX 18
#define DMA_REQ_CSPI2_TX 17
#define DMA_REQ_CSPI2_RX 16
#define DMA_REQ_SSI1_TX1 15
#define DMA_REQ_SSI1_RX1 14
#define DMA_REQ_SSI1_TX0 13
#define DMA_REQ_SSI1_RX0 12
#define DMA_REQ_SSI2_TX1 11
#define DMA_REQ_SSI2_RX1 10
#define DMA_REQ_SSI2_TX0 9
#define DMA_REQ_SSI2_RX0 8
#define DMA_REQ_SDHC1 7
#define DMA_REQ_SDHC2 6
#define DMA_REQ_EXT 3
#define DMA_REQ_CSPI3_TX 2
#define DMA_REQ_CSPI3_RX 1
#define MX2x_DMA_REQ_CSPI3_RX 1
#define MX2x_DMA_REQ_CSPI3_TX 2
#define MX2x_DMA_REQ_EXT 3
#define MX2x_DMA_REQ_SDHC2 6
#define MX2x_DMA_REQ_SDHC1 7
#define MX2x_DMA_REQ_SSI2_RX0 8
#define MX2x_DMA_REQ_SSI2_TX0 9
#define MX2x_DMA_REQ_SSI2_RX1 10
#define MX2x_DMA_REQ_SSI2_TX1 11
#define MX2x_DMA_REQ_SSI1_RX0 12
#define MX2x_DMA_REQ_SSI1_TX0 13
#define MX2x_DMA_REQ_SSI1_RX1 14
#define MX2x_DMA_REQ_SSI1_TX1 15
#define MX2x_DMA_REQ_CSPI2_RX 16
#define MX2x_DMA_REQ_CSPI2_TX 17
#define MX2x_DMA_REQ_CSPI1_RX 18
#define MX2x_DMA_REQ_CSPI1_TX 19
#define MX2x_DMA_REQ_UART4_RX 20
#define MX2x_DMA_REQ_UART4_TX 21
#define MX2x_DMA_REQ_UART3_RX 22
#define MX2x_DMA_REQ_UART3_TX 23
#define MX2x_DMA_REQ_UART2_RX 24
#define MX2x_DMA_REQ_UART2_TX 25
#define MX2x_DMA_REQ_UART1_RX 26
#define MX2x_DMA_REQ_UART1_TX 27
#define MX2x_DMA_REQ_CSI_STAT 30
#define MX2x_DMA_REQ_CSI_RX 31
/* these should go away */
#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
#define AIPI_SIZE MX2x_AIPI_SIZE
#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
#define SAHB1_SIZE MX2x_SAHB1_SIZE
#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
#define MXC_INT_CSPI3 MX2x_INT_CSPI3
#define MXC_INT_GPIO MX2x_INT_GPIO
#define MXC_INT_SDHC2 MX2x_INT_SDHC2
#define MXC_INT_SDHC1 MX2x_INT_SDHC1
#define MXC_INT_I2C MX2x_INT_I2C
#define MXC_INT_SSI2 MX2x_INT_SSI2
#define MXC_INT_SSI1 MX2x_INT_SSI1
#define MXC_INT_CSPI2 MX2x_INT_CSPI2
#define MXC_INT_CSPI1 MX2x_INT_CSPI1
#define MXC_INT_UART4 MX2x_INT_UART4
#define MXC_INT_UART3 MX2x_INT_UART3
#define MXC_INT_UART2 MX2x_INT_UART2
#define MXC_INT_UART1 MX2x_INT_UART1
#define MXC_INT_KPP MX2x_INT_KPP
#define MXC_INT_RTC MX2x_INT_RTC
#define MXC_INT_PWM MX2x_INT_PWM
#define MXC_INT_GPT3 MX2x_INT_GPT3
#define MXC_INT_GPT2 MX2x_INT_GPT2
#define MXC_INT_GPT1 MX2x_INT_GPT1
#define MXC_INT_WDOG MX2x_INT_WDOG
#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
#define MXC_INT_NANDFC MX2x_INT_NANDFC
#define MXC_INT_CSI MX2x_INT_CSI
#define MXC_INT_DMACH0 MX2x_INT_DMACH0
#define MXC_INT_DMACH1 MX2x_INT_DMACH1
#define MXC_INT_DMACH2 MX2x_INT_DMACH2
#define MXC_INT_DMACH3 MX2x_INT_DMACH3
#define MXC_INT_DMACH4 MX2x_INT_DMACH4
#define MXC_INT_DMACH5 MX2x_INT_DMACH5
#define MXC_INT_DMACH6 MX2x_INT_DMACH6
#define MXC_INT_DMACH7 MX2x_INT_DMACH7
#define MXC_INT_DMACH8 MX2x_INT_DMACH8
#define MXC_INT_DMACH9 MX2x_INT_DMACH9
#define MXC_INT_DMACH10 MX2x_INT_DMACH10
#define MXC_INT_DMACH11 MX2x_INT_DMACH11
#define MXC_INT_DMACH12 MX2x_INT_DMACH12
#define MXC_INT_DMACH13 MX2x_INT_DMACH13
#define MXC_INT_DMACH14 MX2x_INT_DMACH14
#define MXC_INT_DMACH15 MX2x_INT_DMACH15
#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
#define MXC_INT_SLCDC MX2x_INT_SLCDC
#define MXC_INT_LCDC MX2x_INT_LCDC
#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
#endif /* __ASM_ARCH_MXC_MX2x_H__ */

237
arch/arm/plat-mxc/include/mach/mx31.h
View File

@ -1,45 +1,218 @@
/*
* IRAM
*/
#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
#define MX31_IRAM_SIZE SZ_16K
#define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
#define MX31_L2CC_BASE_ADDR 0x30000000
#define MX31_L2CC_SIZE SZ_1M
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX31_AIPS1_SIZE SZ_1M
#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
#define MX31_SPBA0_BASE_ADDR 0x50000000
#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
#define MX31_SPBA0_SIZE SZ_1M
#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
#define MX31_AIPS2_BASE_ADDR 0x53f00000
#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX31_AIPS2_SIZE SZ_1M
#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
#define MXC_INT_MPEG4_ENCODER 5
#define MXC_INT_FIRI 7
#define MX31_ROMP_BASE_ADDR 0x60000000
#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
#define MX31_ROMP_SIZE SZ_1M
#define MX31_AVIC_BASE_ADDR 0x68000000
#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX31_AVIC_SIZE SZ_1M
#define MX31_IPU_MEM_BASE_ADDR 0x70000000
#define MX31_CSD0_BASE_ADDR 0x80000000
#define MX31_CSD1_BASE_ADDR 0x90000000
#define MX31_CS0_BASE_ADDR 0xa0000000
#define MX31_CS1_BASE_ADDR 0xa8000000
#define MX31_CS2_BASE_ADDR 0xb0000000
#define MX31_CS3_BASE_ADDR 0xb2000000
#define MX31_CS4_BASE_ADDR 0xb4000000
#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000
#define MX31_CS4_SIZE SZ_32M
#define MX31_CS5_BASE_ADDR 0xb6000000
#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000
#define MX31_CS5_SIZE SZ_32M
#define MX31_X_MEMC_BASE_ADDR 0xb8000000
#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
#define MX31_X_MEMC_SIZE SZ_64K
#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX31_INT_I2C3 3
#define MX31_INT_I2C2 4
#define MX31_INT_MPEG4_ENCODER 5
#define MX31_INT_RTIC 6
#define MX31_INT_FIRI 7
#define MX31_INT_MMC_SDHC2 8
#define MXC_INT_MMC_SDHC1 9
#define MX31_INT_MMC_SDHC1 9
#define MX31_INT_I2C 10
#define MX31_INT_SSI2 11
#define MX31_INT_SSI1 12
#define MXC_INT_MBX 16
#define MXC_INT_CSPI3 17
#define MXC_INT_SIM2 20
#define MXC_INT_SIM1 21
#define MXC_INT_CCM_DVFS 31
#define MXC_INT_USB1 35
#define MXC_INT_USB2 36
#define MXC_INT_USB3 37
#define MXC_INT_USB4 38
#define MXC_INT_MSHC2 40
#define MXC_INT_UART4 46
#define MXC_INT_UART5 47
#define MXC_INT_CCM 53
#define MXC_INT_PCMCIA 54
#define MX31_INT_CSPI2 13
#define MX31_INT_CSPI1 14
#define MX31_INT_ATA 15
#define MX31_INT_MBX 16
#define MX31_INT_CSPI3 17
#define MX31_INT_UART3 18
#define MX31_INT_IIM 19
#define MX31_INT_SIM2 20
#define MX31_INT_SIM1 21
#define MX31_INT_RNGA 22
#define MX31_INT_EVTMON 23
#define MX31_INT_KPP 24
#define MX31_INT_RTC 25
#define MX31_INT_PWM 26
#define MX31_INT_EPIT2 27
#define MX31_INT_EPIT1 28
#define MX31_INT_GPT 29
#define MX31_INT_POWER_FAIL 30
#define MX31_INT_CCM_DVFS 31
#define MX31_INT_UART2 32
#define MX31_INT_NANDFC 33
#define MX31_INT_SDMA 34
#define MX31_INT_USB1 35
#define MX31_INT_USB2 36
#define MX31_INT_USB3 37
#define MX31_INT_USB4 38
#define MX31_INT_MSHC1 39
#define MX31_INT_MSHC2 40
#define MX31_INT_IPU_ERR 41
#define MX31_INT_IPU_SYN 42
#define MX31_INT_UART1 45
#define MX31_INT_UART4 46
#define MX31_INT_UART5 47
#define MX31_INT_ECT 48
#define MX31_INT_SCC_SCM 49
#define MX31_INT_SCC_SMN 50
#define MX31_INT_GPIO2 51
#define MX31_INT_GPIO1 52
#define MX31_INT_CCM 53
#define MX31_INT_PCMCIA 54
#define MX31_INT_WDOG 55
#define MX31_INT_GPIO3 56
#define MX31_INT_EXT_POWER 58
#define MX31_INT_EXT_TEMPER 59
#define MX31_INT_EXT_SENSOR60 60
#define MX31_INT_EXT_SENSOR61 61
#define MX31_INT_EXT_WDOG 62
#define MX31_INT_EXT_TV 63
#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */
#define MX31_CHIP_REV_1_0 0x10
#define MX31_CHIP_REV_1_1 0x11
#define MX31_CHIP_REV_1_2 0x12
#define MX31_CHIP_REV_1_3 0x13
#define MX31_CHIP_REV_2_0 0x20
#define MX31_CHIP_REV_2_1 0x21
#define MX31_CHIP_REV_2_2 0x22
#define MX31_CHIP_REV_2_3 0x23
#define MX31_CHIP_REV_3_0 0x30
#define MX31_CHIP_REV_3_1 0x31
#define MX31_CHIP_REV_3_2 0x32
#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
#define MX31_SYSTEM_REV_NUM 3
/* these should go away */
#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
#define MXC_INT_FIRI MX31_INT_FIRI
#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
#define MXC_INT_MBX MX31_INT_MBX
#define MXC_INT_CSPI3 MX31_INT_CSPI3
#define MXC_INT_SIM2 MX31_INT_SIM2
#define MXC_INT_SIM1 MX31_INT_SIM1
#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
#define MXC_INT_USB1 MX31_INT_USB1
#define MXC_INT_USB2 MX31_INT_USB2
#define MXC_INT_USB3 MX31_INT_USB3
#define MXC_INT_USB4 MX31_INT_USB4
#define MXC_INT_MSHC2 MX31_INT_MSHC2
#define MXC_INT_UART4 MX31_INT_UART4
#define MXC_INT_UART5 MX31_INT_UART5
#define MXC_INT_CCM MX31_INT_CCM
#define MXC_INT_PCMCIA MX31_INT_PCMCIA

201
arch/arm/plat-mxc/include/mach/mx35.h
View File

@ -2,29 +2,196 @@
* IRAM
*/
#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
#define MX35_IRAM_SIZE SZ_128K
#define MX35_IRAM_SIZE SZ_128K
#define MXC_FEC_BASE_ADDR 0x50038000
#define MX35_OTG_BASE_ADDR 0x53ff4000
#define MX35_NFC_BASE_ADDR 0xBB000000
#define MX35_L2CC_BASE_ADDR 0x30000000
#define MX35_L2CC_SIZE SZ_1M
#define MX35_AIPS1_BASE_ADDR 0x43f00000
#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX35_AIPS1_SIZE SZ_1M
#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
#define MX35_SPBA0_BASE_ADDR 0x50000000
#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
#define MX35_SPBA0_SIZE SZ_1M
#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
#define MX35_FEC_BASE_ADDR 0x50038000
#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
#define MX35_AIPS2_BASE_ADDR 0x53f00000
#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX35_AIPS2_SIZE SZ_1M
#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
#define MX35_OTG_BASE_ADDR 0x53ff4000
#define MX35_ROMP_BASE_ADDR 0x60000000
#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
#define MX35_ROMP_SIZE SZ_1M
#define MX35_AVIC_BASE_ADDR 0x68000000
#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX35_AVIC_SIZE SZ_1M
/*
* Memory regions and CS
*/
#define MX35_IPU_MEM_BASE_ADDR 0x70000000
#define MX35_CSD0_BASE_ADDR 0x80000000
#define MX35_CSD1_BASE_ADDR 0x90000000
#define MX35_CS0_BASE_ADDR 0xa0000000
#define MX35_CS1_BASE_ADDR 0xa8000000
#define MX35_CS2_BASE_ADDR 0xb0000000
#define MX35_CS3_BASE_ADDR 0xb2000000
#define MX35_CS4_BASE_ADDR 0xb4000000
#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000
#define MX35_CS4_SIZE SZ_32M
#define MX35_CS5_BASE_ADDR 0xb6000000
#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000
#define MX35_CS5_SIZE SZ_32M
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define MX35_X_MEMC_BASE_ADDR 0xb8000000
#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
#define MX35_X_MEMC_SIZE SZ_64K
#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
#define MX35_NFC_BASE_ADDR 0xbb000000
#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
/*
* Interrupt numbers
*/
#define MXC_INT_OWIRE 2
#define MX35_INT_OWIRE 2
#define MX35_INT_I2C3 3
#define MX35_INT_I2C2 4
#define MX35_INT_RTIC 6
#define MX35_INT_MMC_SDHC1 7
#define MXC_INT_MMC_SDHC2 8
#define MXC_INT_MMC_SDHC3 9
#define MX35_INT_MMC_SDHC2 8
#define MX35_INT_MMC_SDHC3 9
#define MX35_INT_I2C 10
#define MX35_INT_SSI1 11
#define MX35_INT_SSI2 12
#define MXC_INT_GPU2D 16
#define MXC_INT_ASRC 17
#define MXC_INT_USBHS 35
#define MXC_INT_USBOTG 37
#define MXC_INT_ESAI 40
#define MXC_INT_CAN1 43
#define MXC_INT_CAN2 44
#define MXC_INT_MLB 46
#define MXC_INT_SPDIF 47
#define MXC_INT_FEC 57
#define MX35_INT_CSPI2 13
#define MX35_INT_CSPI1 14
#define MX35_INT_ATA 15
#define MX35_INT_GPU2D 16
#define MX35_INT_ASRC 17
#define MX35_INT_UART3 18
#define MX35_INT_IIM 19
#define MX35_INT_RNGA 22
#define MX35_INT_EVTMON 23
#define MX35_INT_KPP 24
#define MX35_INT_RTC 25
#define MX35_INT_PWM 26
#define MX35_INT_EPIT2 27
#define MX35_INT_EPIT1 28
#define MX35_INT_GPT 29
#define MX35_INT_POWER_FAIL 30
#define MX35_INT_UART2 32
#define MX35_INT_NANDFC 33
#define MX35_INT_SDMA 34
#define MX35_INT_USBHS 35
#define MX35_INT_USBOTG 37
#define MX35_INT_MSHC1 39
#define MX35_INT_ESAI 40
#define MX35_INT_IPU_ERR 41
#define MX35_INT_IPU_SYN 42
#define MX35_INT_CAN1 43
#define MX35_INT_CAN2 44
#define MX35_INT_UART1 45
#define MX35_INT_MLB 46
#define MX35_INT_SPDIF 47
#define MX35_INT_ECT 48
#define MX35_INT_SCC_SCM 49
#define MX35_INT_SCC_SMN 50
#define MX35_INT_GPIO2 51
#define MX35_INT_GPIO1 52
#define MX35_INT_WDOG 55
#define MX35_INT_GPIO3 56
#define MX35_INT_FEC 57
#define MX35_INT_EXT_POWER 58
#define MX35_INT_EXT_TEMPER 59
#define MX35_INT_EXT_SENSOR60 60
#define MX35_INT_EXT_SENSOR61 61
#define MX35_INT_EXT_WDOG 62
#define MX35_INT_EXT_TV 63
#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */
#define MX35_CHIP_REV_1_0 0x10
#define MX35_CHIP_REV_1_1 0x11
#define MX35_CHIP_REV_1_2 0x12
#define MX35_CHIP_REV_1_3 0x13
#define MX35_CHIP_REV_2_0 0x20
#define MX35_CHIP_REV_2_1 0x21
#define MX35_CHIP_REV_2_2 0x22
#define MX35_CHIP_REV_2_3 0x23
#define MX35_CHIP_REV_3_0 0x30
#define MX35_CHIP_REV_3_1 0x31
#define MX35_CHIP_REV_3_2 0x32
#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
#define MX35_SYSTEM_REV_NUM 3
/* these should go away */
#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
#define MXC_INT_OWIRE MX35_INT_OWIRE
#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
#define MXC_INT_GPU2D MX35_INT_GPU2D
#define MXC_INT_ASRC MX35_INT_ASRC
#define MXC_INT_USBHS MX35_INT_USBHS
#define MXC_INT_USBOTG MX35_INT_USBOTG
#define MXC_INT_ESAI MX35_INT_ESAI
#define MXC_INT_CAN1 MX35_INT_CAN1
#define MXC_INT_CAN2 MX35_INT_CAN2
#define MXC_INT_MLB MX35_INT_MLB
#define MXC_INT_SPDIF MX35_INT_SPDIF
#define MXC_INT_FEC MX35_INT_FEC

420
arch/arm/plat-mxc/include/mach/mx3x.h
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@ -34,120 +34,117 @@
* C0000000 64M PCMCIA/CF
*/
#define CS0_BASE_ADDR 0xA0000000
#define CS1_BASE_ADDR 0xA8000000
#define CS2_BASE_ADDR 0xB0000000
#define CS3_BASE_ADDR 0xB2000000
#define CS4_BASE_ADDR 0xB4000000
#define CS4_BASE_ADDR_VIRT 0xF4000000
#define CS4_SIZE SZ_32M
#define CS5_BASE_ADDR 0xB6000000
#define CS5_BASE_ADDR_VIRT 0xF6000000
#define CS5_SIZE SZ_32M
#define PCMCIA_MEM_BASE_ADDR 0xBC000000
/*
* L2CC
*/
#define L2CC_BASE_ADDR 0x30000000
#define L2CC_SIZE SZ_1M
#define MX3x_L2CC_BASE_ADDR 0x30000000
#define MX3x_L2CC_SIZE SZ_1M
/*
* AIPS 1
*/
#define AIPS1_BASE_ADDR 0x43F00000
#define AIPS1_BASE_ADDR_VIRT 0xFC000000
#define AIPS1_SIZE SZ_1M
#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
#define MX3x_AIPS1_BASE_ADDR 0x43f00000
#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX3x_AIPS1_SIZE SZ_1M
#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
/*
* SPBA global module enabled #0
*/
#define SPBA0_BASE_ADDR 0x50000000
#define SPBA0_BASE_ADDR_VIRT 0xFC100000
#define SPBA0_SIZE SZ_1M
#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
#define MX3x_SPBA0_BASE_ADDR 0x50000000
#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
#define MX3x_SPBA0_SIZE SZ_1M
#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
/*
* AIPS 2
*/
#define AIPS2_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR_VIRT 0xFC200000
#define AIPS2_SIZE SZ_1M
#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
#define MX3x_AIPS2_BASE_ADDR 0x53f00000
#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX3x_AIPS2_SIZE SZ_1M
#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
/*
* ROMP and AVIC
*/
#define ROMP_BASE_ADDR 0x60000000
#define ROMP_BASE_ADDR_VIRT 0xFC500000
#define ROMP_SIZE SZ_1M
#define MX3x_ROMP_BASE_ADDR 0x60000000
#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
#define MX3x_ROMP_SIZE SZ_1M
#define AVIC_BASE_ADDR 0x68000000
#define AVIC_BASE_ADDR_VIRT 0xFC400000
#define AVIC_SIZE SZ_1M
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define X_MEMC_BASE_ADDR 0xB8000000
#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
#define X_MEMC_SIZE SZ_64K
#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
#define MX3x_AVIC_BASE_ADDR 0x68000000
#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX3x_AVIC_SIZE SZ_1M
/*
* Memory regions and CS
*/
#define IPU_MEM_BASE_ADDR 0x70000000
#define CSD0_BASE_ADDR 0x80000000
#define CSD1_BASE_ADDR 0x90000000
#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
#define MX3x_CSD0_BASE_ADDR 0x80000000
#define MX3x_CSD1_BASE_ADDR 0x90000000
#define MX3x_CS0_BASE_ADDR 0xa0000000
#define MX3x_CS1_BASE_ADDR 0xa8000000
#define MX3x_CS2_BASE_ADDR 0xb0000000
#define MX3x_CS3_BASE_ADDR 0xb2000000
#define MX3x_CS4_BASE_ADDR 0xb4000000
#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000
#define MX3x_CS4_SIZE SZ_32M
#define MX3x_CS5_BASE_ADDR 0xb6000000
#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000
#define MX3x_CS5_SIZE SZ_32M
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
#define MX3x_X_MEMC_SIZE SZ_64K
#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
/*!
* This macro defines the physical to virtual address mapping for all the
@ -202,74 +199,207 @@
/*
* Interrupt numbers
*/
#define MXC_INT_I2C3 3
#define MXC_INT_I2C2 4
#define MXC_INT_RTIC 6
#define MXC_INT_I2C 10
#define MXC_INT_CSPI2 13
#define MXC_INT_CSPI1 14
#define MXC_INT_ATA 15
#define MXC_INT_UART3 18
#define MXC_INT_IIM 19
#define MXC_INT_RNGA 22
#define MXC_INT_EVTMON 23
#define MXC_INT_KPP 24
#define MXC_INT_RTC 25
#define MXC_INT_PWM 26
#define MXC_INT_EPIT2 27
#define MXC_INT_EPIT1 28
#define MXC_INT_GPT 29
#define MXC_INT_POWER_FAIL 30
#define MXC_INT_UART2 32
#define MXC_INT_NANDFC 33
#define MXC_INT_SDMA 34
#define MXC_INT_MSHC1 39
#define MXC_INT_IPU_ERR 41
#define MXC_INT_IPU_SYN 42
#define MXC_INT_UART1 45
#define MXC_INT_ECT 48
#define MXC_INT_SCC_SCM 49
#define MXC_INT_SCC_SMN 50
#define MXC_INT_GPIO2 51
#define MXC_INT_GPIO1 52
#define MXC_INT_WDOG 55
#define MXC_INT_GPIO3 56
#define MXC_INT_EXT_POWER 58
#define MXC_INT_EXT_TEMPER 59
#define MXC_INT_EXT_SENSOR60 60
#define MXC_INT_EXT_SENSOR61 61
#define MXC_INT_EXT_WDOG 62
#define MXC_INT_EXT_TV 63
#define MX3x_INT_I2C3 3
#define MX3x_INT_I2C2 4
#define MX3x_INT_RTIC 6
#define MX3x_INT_I2C 10
#define MX3x_INT_CSPI2 13
#define MX3x_INT_CSPI1 14
#define MX3x_INT_ATA 15
#define MX3x_INT_UART3 18
#define MX3x_INT_IIM 19
#define MX3x_INT_RNGA 22
#define MX3x_INT_EVTMON 23
#define MX3x_INT_KPP 24
#define MX3x_INT_RTC 25
#define MX3x_INT_PWM 26
#define MX3x_INT_EPIT2 27
#define MX3x_INT_EPIT1 28
#define MX3x_INT_GPT 29
#define MX3x_INT_POWER_FAIL 30
#define MX3x_INT_UART2 32
#define MX3x_INT_NANDFC 33
#define MX3x_INT_SDMA 34
#define MX3x_INT_MSHC1 39
#define MX3x_INT_IPU_ERR 41
#define MX3x_INT_IPU_SYN 42
#define MX3x_INT_UART1 45
#define MX3x_INT_ECT 48
#define MX3x_INT_SCC_SCM 49
#define MX3x_INT_SCC_SMN 50
#define MX3x_INT_GPIO2 51
#define MX3x_INT_GPIO1 52
#define MX3x_INT_WDOG 55
#define MX3x_INT_GPIO3 56
#define MX3x_INT_EXT_POWER 58
#define MX3x_INT_EXT_TEMPER 59
#define MX3x_INT_EXT_SENSOR60 60
#define MX3x_INT_EXT_SENSOR61 61
#define MX3x_INT_EXT_WDOG 62
#define MX3x_INT_EXT_TV 63
#define PROD_SIGNATURE 0x1 /* For MX31 */
#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_3 0x13
#define CHIP_REV_2_0 0x20
#define CHIP_REV_2_1 0x21
#define CHIP_REV_2_2 0x22
#define CHIP_REV_2_3 0x23
#define CHIP_REV_3_0 0x30
#define CHIP_REV_3_1 0x31
#define CHIP_REV_3_2 0x32
#define MX3x_CHIP_REV_1_0 0x10
#define MX3x_CHIP_REV_1_1 0x11
#define MX3x_CHIP_REV_1_2 0x12
#define MX3x_CHIP_REV_1_3 0x13
#define MX3x_CHIP_REV_2_0 0x20
#define MX3x_CHIP_REV_2_1 0x21
#define MX3x_CHIP_REV_2_2 0x22
#define MX3x_CHIP_REV_2_3 0x23
#define MX3x_CHIP_REV_3_0 0x30
#define MX3x_CHIP_REV_3_1 0x31
#define MX3x_CHIP_REV_3_2 0x32
#define SYSTEM_REV_MIN CHIP_REV_1_0
#define SYSTEM_REV_NUM 3
#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
#define MX3x_SYSTEM_REV_NUM 3
/* Mandatory defines used globally */
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern unsigned int system_rev;
extern unsigned int mx31_cpu_rev;
extern void mx31_read_cpu_rev(void);
static inline int mx31_revision(void)
{
return system_rev;
return mx31_cpu_rev;
}
#endif
#endif /* __ASM_ARCH_MXC_MX31_H__ */
/* these should go away */
#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
#define L2CC_SIZE MX3x_L2CC_SIZE
#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
#define AIPS1_SIZE MX3x_AIPS1_SIZE
#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
#define SPBA0_SIZE MX3x_SPBA0_SIZE
#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
#define AIPS2_SIZE MX3x_AIPS2_SIZE
#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
#define ROMP_SIZE MX3x_ROMP_SIZE
#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
#define AVIC_SIZE MX3x_AVIC_SIZE
#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
#define CS4_SIZE MX3x_CS4_SIZE
#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
#define CS5_SIZE MX3x_CS5_SIZE
#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
#define MXC_INT_I2C3 MX3x_INT_I2C3
#define MXC_INT_I2C2 MX3x_INT_I2C2
#define MXC_INT_RTIC MX3x_INT_RTIC
#define MXC_INT_I2C MX3x_INT_I2C
#define MXC_INT_CSPI2 MX3x_INT_CSPI2
#define MXC_INT_CSPI1 MX3x_INT_CSPI1
#define MXC_INT_ATA MX3x_INT_ATA
#define MXC_INT_UART3 MX3x_INT_UART3
#define MXC_INT_IIM MX3x_INT_IIM
#define MXC_INT_RNGA MX3x_INT_RNGA
#define MXC_INT_EVTMON MX3x_INT_EVTMON
#define MXC_INT_KPP MX3x_INT_KPP
#define MXC_INT_RTC MX3x_INT_RTC
#define MXC_INT_PWM MX3x_INT_PWM
#define MXC_INT_EPIT2 MX3x_INT_EPIT2
#define MXC_INT_EPIT1 MX3x_INT_EPIT1
#define MXC_INT_GPT MX3x_INT_GPT
#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
#define MXC_INT_UART2 MX3x_INT_UART2
#define MXC_INT_NANDFC MX3x_INT_NANDFC
#define MXC_INT_SDMA MX3x_INT_SDMA
#define MXC_INT_MSHC1 MX3x_INT_MSHC1
#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
#define MXC_INT_UART1 MX3x_INT_UART1
#define MXC_INT_ECT MX3x_INT_ECT
#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
#define MXC_INT_GPIO2 MX3x_INT_GPIO2
#define MXC_INT_GPIO1 MX3x_INT_GPIO1
#define MXC_INT_WDOG MX3x_INT_WDOG
#define MXC_INT_GPIO3 MX3x_INT_GPIO3
#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
#endif /* __ASM_ARCH_MXC_MX31_H__ */

7
arch/arm/plat-mxc/include/mach/ulpi.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_ULPI_H
#define __MACH_ULPI_H
extern struct otg_io_access_ops mxc_ulpi_access_ops;
#endif /* __MACH_ULPI_H */

2
arch/arm/plat-mxc/include/mach/uncompress.h
View File

@ -83,6 +83,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
case MACH_TYPE_MX27ADS:
case MACH_TYPE_PCM038:
case MACH_TYPE_MX21ADS:
case MACH_TYPE_PCA100:
uart_base = MX2X_UART1_BASE_ADDR;
break;
case MACH_TYPE_MX31LITE:
@ -94,6 +95,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
case MACH_TYPE_MX31ADS:
case MACH_TYPE_MX35_3DS:
case MACH_TYPE_PCM043:
case MACH_TYPE_LILLY1131:
uart_base = MX3X_UART1_BASE_ADDR;
break;
case MACH_TYPE_MAGX_ZN5:

36
arch/arm/plat-mxc/iomux-v3.c
View File

@ -31,19 +31,11 @@
static void __iomem *base;
static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
/*
* setups a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
* setups a single pad in the iomuxer
*/
int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
{
unsigned int pad_ofs = pad->pad_ctrl_ofs;
if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
return -EBUSY;
if (pad->mux_ctrl_ofs)
__raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
@ -66,37 +58,13 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
for (i = 0; i < count; i++) {
ret = mxc_iomux_v3_setup_pad(p);
if (ret)
goto setup_error;
return ret;
p++;
}
return 0;
setup_error:
mxc_iomux_v3_release_multiple_pads(pad_list, i);
return ret;
}
EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
void mxc_iomux_v3_release_pad(struct pad_desc *pad)
{
unsigned int pad_ofs = pad->pad_ctrl_ofs;
clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map);
}
EXPORT_SYMBOL(mxc_iomux_v3_release_pad);
void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
{
struct pad_desc *p = pad_list;
int i;
for (i = 0; i < count; i++) {
mxc_iomux_v3_release_pad(p);
p++;
}
}
EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
{
base = iomux_v3_base;

113
arch/arm/plat-mxc/ulpi.c Normal file
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/*
* Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
* Copyright 2009 Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/usb/otg.h>
#include <mach/ulpi.h>
/* ULPIVIEW register bits */
#define ULPIVW_WU (1 << 31) /* Wakeup */
#define ULPIVW_RUN (1 << 30) /* read/write run */
#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */
#define ULPIVW_SS (1 << 27) /* SyncState */
#define ULPIVW_PORT_MASK 0x07 /* Port field */
#define ULPIVW_PORT_SHIFT 24
#define ULPIVW_ADDR_MASK 0xff /* data address field */
#define ULPIVW_ADDR_SHIFT 16
#define ULPIVW_RDATA_MASK 0xff /* read data field */
#define ULPIVW_RDATA_SHIFT 8
#define ULPIVW_WDATA_MASK 0xff /* write data field */
#define ULPIVW_WDATA_SHIFT 0
static int ulpi_poll(void __iomem *view, u32 bit)
{
int timeout = 10000;
while (timeout--) {
u32 data = __raw_readl(view);
if (!(data & bit))
return 0;
cpu_relax();
};
printk(KERN_WARNING "timeout polling for ULPI device\n");
return -ETIMEDOUT;
}
static int ulpi_read(struct otg_transceiver *otg, u32 reg)
{
int ret;
void __iomem *view = otg->io_priv;
/* make sure interface is running */
if (!(__raw_readl(view) & ULPIVW_SS)) {
__raw_writel(ULPIVW_WU, view);
/* wait for wakeup */
ret = ulpi_poll(view, ULPIVW_WU);
if (ret)
return ret;
}
/* read the register */
__raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
/* wait for completion */
ret = ulpi_poll(view, ULPIVW_RUN);
if (ret)
return ret;
return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
}
static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
{
int ret;
void __iomem *view = otg->io_priv;
/* make sure the interface is running */
if (!(__raw_readl(view) & ULPIVW_SS)) {
__raw_writel(ULPIVW_WU, view);
/* wait for wakeup */
ret = ulpi_poll(view, ULPIVW_WU);
if (ret)
return ret;
}
__raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
(reg << ULPIVW_ADDR_SHIFT) |
((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
/* wait for completion */
return ulpi_poll(view, ULPIVW_RUN);
}
struct otg_io_access_ops mxc_ulpi_access_ops = {
.read = ulpi_read,
.write = ulpi_write,
};
EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);