iwlagn: move PCI power related functions to the PCI layer
Continue to popule the PCI layer and the iwl_bus_ops with the power related stuff. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
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@ -81,13 +81,6 @@
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/* RSSI to dBm */
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#define IWLAGN_RSSI_OFFSET 44
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/* PCI registers */
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#define PCI_CFG_RETRY_TIMEOUT 0x041
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/* PCI register values */
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#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
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#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
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#define IWLAGN_DEFAULT_TX_RETRY 15
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/* Limit range of txpower output target to be between these values */
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@ -997,8 +997,6 @@ void iwl_apm_stop(struct iwl_priv *priv)
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int iwl_apm_init(struct iwl_priv *priv)
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{
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int ret = 0;
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u16 lctl;
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IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
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/*
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@ -1027,27 +1025,7 @@ int iwl_apm_init(struct iwl_priv *priv)
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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/*
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* HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
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* Check if BIOS (or OS) enabled L1-ASPM on this device.
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* If so (likely), disable L0S, so device moves directly L0->L1;
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* costs negligible amount of power savings.
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* If not (unlikely), enable L0S, so there is at least some
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* power savings, even without L1.
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*/
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lctl = iwl_pcie_link_ctl(priv);
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if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
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PCI_CFG_LINK_CTRL_VAL_L1_EN) {
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/* L1-ASPM enabled; disable(!) L0S */
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iwl_set_bit(priv, CSR_GIO_REG,
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CSR_GIO_REG_VAL_L0S_ENABLED);
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IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
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} else {
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/* L1-ASPM disabled; enable(!) L0S */
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iwl_clear_bit(priv, CSR_GIO_REG,
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CSR_GIO_REG_VAL_L0S_ENABLED);
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IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
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}
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priv->bus.ops->apm_config(&priv->bus);
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/* Configure analog phase-lock-loop before activating to D0A */
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if (priv->cfg->base_params->pll_cfg_val)
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@ -470,20 +470,6 @@ int iwl_send_cmd_pdu_async(struct iwl_priv *priv, u8 id, u16 len,
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int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
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/*****************************************************
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* PCI *
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*****************************************************/
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static inline u16 iwl_pcie_link_ctl(struct iwl_priv *priv)
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{
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int pos;
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u16 pci_lnk_ctl;
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pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP);
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pci_read_config_word(priv->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
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return pci_lnk_ctl;
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}
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void iwl_bg_watchdog(unsigned long data);
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u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval);
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__le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
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@ -1193,6 +1193,9 @@ struct iwl_bus;
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/**
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* struct iwl_bus_ops - bus specific operations
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* @get_pm_support: must returns true if the bus can go to sleep
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* @apm_config: will be called during the config of the APM configuration
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* @set_drv_data: set the priv pointer to the bus layer
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* @get_dev: returns the device struct
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* @write8: write a byte to register at offset ofs
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@ -1200,6 +1203,8 @@ struct iwl_bus;
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* @wread32: read a dword at register at offset ofs
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*/
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struct iwl_bus_ops {
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bool (*get_pm_support)(struct iwl_bus *bus);
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void (*apm_config)(struct iwl_bus *bus);
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void (*set_drv_data)(struct iwl_bus *bus, void *priv);
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struct device *(*get_dev)(const struct iwl_bus *bus);
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void (*write8)(struct iwl_bus *bus, u32 ofs, u8 val);
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@ -66,6 +66,12 @@
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#include "iwl-pci.h"
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#include "iwl-agn.h"
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#include "iwl-core.h"
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#include "iwl-io.h"
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/* PCI registers */
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#define PCI_CFG_RETRY_TIMEOUT 0x041
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#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
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#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
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struct iwl_pci_bus {
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/* basic pci-network driver stuff */
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@ -81,6 +87,50 @@ struct iwl_pci_bus {
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#define IWL_BUS_GET_PCI_DEV(_iwl_bus) \
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((IWL_BUS_GET_PCI_BUS(_iwl_bus))->pci_dev)
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static u16 iwl_pciexp_link_ctrl(struct iwl_bus *bus)
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{
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int pos;
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u16 pci_lnk_ctl;
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struct pci_dev *pci_dev = IWL_BUS_GET_PCI_DEV(bus);
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pos = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
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pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
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return pci_lnk_ctl;
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}
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static bool iwl_pci_is_pm_supported(struct iwl_bus *bus)
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{
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u16 lctl = iwl_pciexp_link_ctrl(bus);
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return !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
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}
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static void iwl_pci_apm_config(struct iwl_bus *bus)
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{
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/*
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* HW bug W/A for instability in PCIe bus L0S->L1 transition.
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* Check if BIOS (or OS) enabled L1-ASPM on this device.
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* If so (likely), disable L0S, so device moves directly L0->L1;
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* costs negligible amount of power savings.
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* If not (unlikely), enable L0S, so there is at least some
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* power savings, even without L1.
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*/
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u16 lctl = iwl_pciexp_link_ctrl(bus);
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if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
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PCI_CFG_LINK_CTRL_VAL_L1_EN) {
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/* L1-ASPM enabled; disable(!) L0S */
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iwl_set_bit(bus->priv, CSR_GIO_REG,
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CSR_GIO_REG_VAL_L0S_ENABLED);
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IWL_DEBUG_POWER(bus->priv, "L1 Enabled; Disabling L0S\n");
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} else {
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/* L1-ASPM disabled; enable(!) L0S */
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iwl_clear_bit(bus->priv, CSR_GIO_REG,
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CSR_GIO_REG_VAL_L0S_ENABLED);
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IWL_DEBUG_POWER(bus->priv, "L1 Disabled; Enabling L0S\n");
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}
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}
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static void iwl_pci_set_drv_data(struct iwl_bus *bus, void *drv_priv)
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{
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pci_set_drvdata(IWL_BUS_GET_PCI_DEV(bus), drv_priv);
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@ -108,6 +158,8 @@ static u32 iwl_pci_read32(struct iwl_bus *bus, u32 ofs)
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}
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static struct iwl_bus_ops pci_ops = {
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.get_pm_support = iwl_pci_is_pm_supported,
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.apm_config = iwl_pci_apm_config,
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.set_drv_data = iwl_pci_set_drv_data,
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.get_dev = iwl_pci_get_dev,
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.write8 = iwl_pci_write8,
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@ -245,7 +245,7 @@ static void iwl_static_sleep_cmd(struct iwl_priv *priv,
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}
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}
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if (priv->power_data.pci_pm)
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if (priv->power_data.bus_pm)
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cmd->flags |= IWL_POWER_PCI_PM_MSK;
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else
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cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
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@ -260,7 +260,7 @@ static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
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{
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memset(cmd, 0, sizeof(*cmd));
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if (priv->power_data.pci_pm)
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if (priv->power_data.bus_pm)
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cmd->flags |= IWL_POWER_PCI_PM_MSK;
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IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
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@ -296,7 +296,7 @@ static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
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cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
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IWL_POWER_FAST_PD; /* no use seeing frames for others */
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if (priv->power_data.pci_pm)
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if (priv->power_data.bus_pm)
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cmd->flags |= IWL_POWER_PCI_PM_MSK;
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if (priv->cfg->base_params->shadow_reg_enable)
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@ -425,9 +425,7 @@ int iwl_power_update_mode(struct iwl_priv *priv, bool force)
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/* initialize to default */
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void iwl_power_initialize(struct iwl_priv *priv)
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{
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u16 lctl = iwl_pcie_link_ctl(priv);
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priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
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priv->power_data.bus_pm = priv->bus.ops->get_pm_support(&priv->bus);
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priv->power_data.debug_sleep_level_override = -1;
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@ -43,7 +43,7 @@ struct iwl_power_mgr {
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struct iwl_powertable_cmd sleep_cmd;
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struct iwl_powertable_cmd sleep_cmd_next;
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int debug_sleep_level_override;
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bool pci_pm;
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bool bus_pm;
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};
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int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
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