Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6:
[SPARC64]: Define TASK_SIZE_OF()
[SPARC64]: flush_ptrace_access() needs preemption disable.
[SPARC64]: Update defconfig.
[SPARC64]: Fix allnoconfig build, ptrace.c missing CONFIG_COMPAT checks.
[SPARC64]: Fix __get_cpu_var in preemption-enabled area.
[SPARC64]: Fix sparse warnings in arch/sparc64/kernel/signal.c
[SPARC64]: Fix most sparse warnings in arch/sparc64/kernel/sys_sparc.c
[SPARC64]: Fix sparse warnings in arch/sparc64/kernel/time.c
[SPARC64]: Fix sparse warnings in arch/sparc64/kernel/ptrace.c
[SPARC64]: Fix sparse warnings in arch/sparc64/kernel/irq.c
[SPARC64]: Fix sparse warnings in arch/sparc64/kernel/iommu.c
[SPARC64]: Fix sparse errors in arch/sparc64/kernel/traps.c
[SPARC64]: Fix sparse warnings in arch/sparc64/kernel/{cpu,setup}.c
[SPARC64]: Adjust {TLBTEMP,TSBMAP}_BASE.
[SPARC64]: Make save_stack_trace() more efficient.
This commit is contained in:
Linus Torvalds
commit
d55a4528f7
|
|
@ -1,7 +1,7 @@
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|||
#
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||||
# Automatically generated make config: don't edit
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# Linux kernel version: 2.6.25-rc1
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# Sun Feb 17 22:44:12 2008
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# Linux kernel version: 2.6.25-rc3
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# Wed Mar 26 04:33:35 2008
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||||
#
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||||
CONFIG_SPARC=y
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||||
CONFIG_SPARC64=y
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||||
|
|
@ -55,9 +55,11 @@ CONFIG_POSIX_MQUEUE=y
|
|||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_LOG_BUF_SHIFT=18
|
||||
# CONFIG_CGROUPS is not set
|
||||
CONFIG_GROUP_SCHED=y
|
||||
CONFIG_FAIR_GROUP_SCHED=y
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||||
CONFIG_FAIR_USER_SCHED=y
|
||||
# CONFIG_FAIR_CGROUP_SCHED is not set
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_USER_SCHED=y
|
||||
# CONFIG_CGROUP_SCHED is not set
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_RELAY=y
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||||
CONFIG_NAMESPACES=y
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||||
|
|
@ -482,6 +484,7 @@ CONFIG_SCSI_LOWLEVEL=y
|
|||
# CONFIG_SCSI_IPS is not set
|
||||
# CONFIG_SCSI_INITIO is not set
|
||||
# CONFIG_SCSI_INIA100 is not set
|
||||
# CONFIG_SCSI_MVSAS is not set
|
||||
# CONFIG_SCSI_STEX is not set
|
||||
# CONFIG_SCSI_SYM53C8XX_2 is not set
|
||||
# CONFIG_SCSI_QLOGIC_1280 is not set
|
||||
|
|
@ -810,6 +813,7 @@ CONFIG_HWMON=y
|
|||
# CONFIG_SENSORS_ADM1031 is not set
|
||||
# CONFIG_SENSORS_ADM9240 is not set
|
||||
# CONFIG_SENSORS_ADT7470 is not set
|
||||
# CONFIG_SENSORS_ADT7473 is not set
|
||||
# CONFIG_SENSORS_ATXP1 is not set
|
||||
# CONFIG_SENSORS_DS1621 is not set
|
||||
# CONFIG_SENSORS_I5K_AMB is not set
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
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|||
#include <asm/spitfire.h>
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#include <asm/oplib.h>
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#include "entry.h"
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DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
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struct cpu_iu_info {
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|
@ -65,8 +67,6 @@ static struct cpu_iu_info linux_sparc_chips[] = {
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char *sparc_cpu_type;
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char *sparc_fpu_type;
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unsigned int fsr_storage;
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|
||||
static void __init sun4v_cpu_probe(void)
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{
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switch (sun4v_chip_type) {
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|
|
@ -94,8 +94,10 @@ void __init cpu_probe(void)
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unsigned long ver, fpu_vers, manuf, impl, fprs;
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int i;
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||||
if (tlb_type == hypervisor)
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return sun4v_cpu_probe();
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||||
if (tlb_type == hypervisor) {
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||||
sun4v_cpu_probe();
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return;
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}
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fprs = fprs_read();
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fprs_write(FPRS_FEF);
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|
|
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|||
|
|
@ -1705,6 +1705,36 @@ __flushw_user:
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2: retl
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nop
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/* Flush %fp and %i7 to the stack for all register
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* windows active inside of the cpu. This allows
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* show_stack_trace() to avoid using an expensive
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* 'flushw'.
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*/
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.globl stack_trace_flush
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.type stack_trace_flush,#function
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stack_trace_flush:
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rdpr %pstate, %o0
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wrpr %o0, PSTATE_IE, %pstate
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rdpr %cwp, %g1
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rdpr %canrestore, %g2
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sub %g1, 1, %g3
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1: brz,pn %g2, 2f
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sub %g2, 1, %g2
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wrpr %g3, %cwp
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stx %fp, [%sp + STACK_BIAS + RW_V9_I6]
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stx %i7, [%sp + STACK_BIAS + RW_V9_I7]
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ba,pt %xcc, 1b
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sub %g3, 1, %g3
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|
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2: wrpr %g1, %cwp
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wrpr %o0, %pstate
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|
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retl
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||||
nop
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.size stack_trace_flush,.-stack_trace_flush
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||||
|
||||
#ifdef CONFIG_SMP
|
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.globl hard_smp_processor_id
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||||
hard_smp_processor_id:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,196 @@
|
|||
#ifndef _ENTRY_H
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#define _ENTRY_H
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|
||||
#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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|
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extern char *sparc_cpu_type;
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extern char *sparc_fpu_type;
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|
||||
extern void __init per_cpu_patch(void);
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extern void __init sun4v_patch(void);
|
||||
extern void __init boot_cpu_id_too_large(int cpu);
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||||
extern unsigned int dcache_parity_tl1_occurred;
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extern unsigned int icache_parity_tl1_occurred;
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|
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extern asmlinkage void update_perfctrs(void);
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extern asmlinkage void sparc_breakpoint(struct pt_regs *regs);
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extern void timer_interrupt(int irq, struct pt_regs *regs);
|
||||
|
||||
extern void do_notify_resume(struct pt_regs *regs,
|
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unsigned long orig_i0,
|
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int restart_syscall,
|
||||
unsigned long thread_info_flags);
|
||||
|
||||
extern asmlinkage void syscall_trace(struct pt_regs *regs,
|
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int syscall_exit_p);
|
||||
|
||||
extern void bad_trap_tl1(struct pt_regs *regs, long lvl);
|
||||
|
||||
extern void do_fpe_common(struct pt_regs *regs);
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extern void do_fpieee(struct pt_regs *regs);
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extern void do_fpother(struct pt_regs *regs);
|
||||
extern void do_tof(struct pt_regs *regs);
|
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extern void do_div0(struct pt_regs *regs);
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||||
extern void do_illegal_instruction(struct pt_regs *regs);
|
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extern void mem_address_unaligned(struct pt_regs *regs,
|
||||
unsigned long sfar,
|
||||
unsigned long sfsr);
|
||||
extern void sun4v_do_mna(struct pt_regs *regs,
|
||||
unsigned long addr,
|
||||
unsigned long type_ctx);
|
||||
extern void do_privop(struct pt_regs *regs);
|
||||
extern void do_privact(struct pt_regs *regs);
|
||||
extern void do_cee(struct pt_regs *regs);
|
||||
extern void do_cee_tl1(struct pt_regs *regs);
|
||||
extern void do_dae_tl1(struct pt_regs *regs);
|
||||
extern void do_iae_tl1(struct pt_regs *regs);
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||||
extern void do_div0_tl1(struct pt_regs *regs);
|
||||
extern void do_fpdis_tl1(struct pt_regs *regs);
|
||||
extern void do_fpieee_tl1(struct pt_regs *regs);
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||||
extern void do_fpother_tl1(struct pt_regs *regs);
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||||
extern void do_ill_tl1(struct pt_regs *regs);
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||||
extern void do_irq_tl1(struct pt_regs *regs);
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extern void do_lddfmna_tl1(struct pt_regs *regs);
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extern void do_stdfmna_tl1(struct pt_regs *regs);
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extern void do_paw(struct pt_regs *regs);
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extern void do_paw_tl1(struct pt_regs *regs);
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extern void do_vaw(struct pt_regs *regs);
|
||||
extern void do_vaw_tl1(struct pt_regs *regs);
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extern void do_tof_tl1(struct pt_regs *regs);
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||||
extern void do_getpsr(struct pt_regs *regs);
|
||||
|
||||
extern void spitfire_insn_access_exception(struct pt_regs *regs,
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||||
unsigned long sfsr,
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||||
unsigned long sfar);
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||||
extern void spitfire_insn_access_exception_tl1(struct pt_regs *regs,
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||||
unsigned long sfsr,
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||||
unsigned long sfar);
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||||
extern void spitfire_data_access_exception(struct pt_regs *regs,
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||||
unsigned long sfsr,
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||||
unsigned long sfar);
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||||
extern void spitfire_data_access_exception_tl1(struct pt_regs *regs,
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||||
unsigned long sfsr,
|
||||
unsigned long sfar);
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||||
extern void spitfire_access_error(struct pt_regs *regs,
|
||||
unsigned long status_encoded,
|
||||
unsigned long afar);
|
||||
|
||||
extern void cheetah_fecc_handler(struct pt_regs *regs,
|
||||
unsigned long afsr,
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||||
unsigned long afar);
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||||
extern void cheetah_cee_handler(struct pt_regs *regs,
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unsigned long afsr,
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||||
unsigned long afar);
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||||
extern void cheetah_deferred_handler(struct pt_regs *regs,
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||||
unsigned long afsr,
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||||
unsigned long afar);
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||||
extern void cheetah_plus_parity_error(int type, struct pt_regs *regs);
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||||
|
||||
extern void sun4v_insn_access_exception(struct pt_regs *regs,
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||||
unsigned long addr,
|
||||
unsigned long type_ctx);
|
||||
extern void sun4v_insn_access_exception_tl1(struct pt_regs *regs,
|
||||
unsigned long addr,
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||||
unsigned long type_ctx);
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||||
extern void sun4v_data_access_exception(struct pt_regs *regs,
|
||||
unsigned long addr,
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||||
unsigned long type_ctx);
|
||||
extern void sun4v_data_access_exception_tl1(struct pt_regs *regs,
|
||||
unsigned long addr,
|
||||
unsigned long type_ctx);
|
||||
extern void sun4v_resum_error(struct pt_regs *regs,
|
||||
unsigned long offset);
|
||||
extern void sun4v_resum_overflow(struct pt_regs *regs);
|
||||
extern void sun4v_nonresum_error(struct pt_regs *regs,
|
||||
unsigned long offset);
|
||||
extern void sun4v_nonresum_overflow(struct pt_regs *regs);
|
||||
|
||||
extern unsigned long sun4v_err_itlb_vaddr;
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||||
extern unsigned long sun4v_err_itlb_ctx;
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extern unsigned long sun4v_err_itlb_pte;
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extern unsigned long sun4v_err_itlb_error;
|
||||
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extern void sun4v_itlb_error_report(struct pt_regs *regs, int tl);
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||||
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||||
extern unsigned long sun4v_err_dtlb_vaddr;
|
||||
extern unsigned long sun4v_err_dtlb_ctx;
|
||||
extern unsigned long sun4v_err_dtlb_pte;
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extern unsigned long sun4v_err_dtlb_error;
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||||
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||||
extern void sun4v_dtlb_error_report(struct pt_regs *regs, int tl);
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extern void hypervisor_tlbop_error(unsigned long err,
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||||
unsigned long op);
|
||||
extern void hypervisor_tlbop_error_xcall(unsigned long err,
|
||||
unsigned long op);
|
||||
|
||||
/* WARNING: The error trap handlers in assembly know the precise
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||||
* layout of the following structure.
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||||
*
|
||||
* C-level handlers in traps.c use this information to log the
|
||||
* error and then determine how to recover (if possible).
|
||||
*/
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||||
struct cheetah_err_info {
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||||
/*0x00*/u64 afsr;
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||||
/*0x08*/u64 afar;
|
||||
|
||||
/* D-cache state */
|
||||
/*0x10*/u64 dcache_data[4]; /* The actual data */
|
||||
/*0x30*/u64 dcache_index; /* D-cache index */
|
||||
/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
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||||
/*0x40*/u64 dcache_utag; /* D-cache microtag */
|
||||
/*0x48*/u64 dcache_stag; /* D-cache snooptag */
|
||||
|
||||
/* I-cache state */
|
||||
/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
|
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/*0x90*/u64 icache_index; /* I-cache index */
|
||||
/*0x98*/u64 icache_tag; /* I-cache phys tag */
|
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/*0xa0*/u64 icache_utag; /* I-cache microtag */
|
||||
/*0xa8*/u64 icache_stag; /* I-cache snooptag */
|
||||
/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
|
||||
/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
|
||||
|
||||
/* E-cache state */
|
||||
/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
|
||||
/*0xe0*/u64 ecache_index; /* E-cache index */
|
||||
/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
|
||||
|
||||
/*0xf0*/u64 __pad[32 - 30];
|
||||
};
|
||||
#define CHAFSR_INVALID ((u64)-1L)
|
||||
|
||||
/* This is allocated at boot time based upon the largest hardware
|
||||
* cpu ID in the system. We allocate two entries per cpu, one for
|
||||
* TL==0 logging and one for TL >= 1 logging.
|
||||
*/
|
||||
extern struct cheetah_err_info *cheetah_error_log;
|
||||
|
||||
/* UPA nodes send interrupt packet to UltraSparc with first data reg
|
||||
* value low 5 (7 on Starfire) bits holding the IRQ identifier being
|
||||
* delivered. We must translate this into a non-vector IRQ so we can
|
||||
* set the softint on this cpu.
|
||||
*
|
||||
* To make processing these packets efficient and race free we use
|
||||
* an array of irq buckets below. The interrupt vector handler in
|
||||
* entry.S feeds incoming packets into per-cpu pil-indexed lists.
|
||||
*
|
||||
* If you make changes to ino_bucket, please update hand coded assembler
|
||||
* of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
|
||||
*/
|
||||
struct ino_bucket {
|
||||
/*0x00*/unsigned long __irq_chain_pa;
|
||||
|
||||
/* Virtual interrupt number assigned to this INO. */
|
||||
/*0x08*/unsigned int __virt_irq;
|
||||
/*0x0c*/unsigned int __pad;
|
||||
};
|
||||
|
||||
extern struct ino_bucket *ivector_table;
|
||||
extern unsigned long ivector_table_pa;
|
||||
|
||||
extern void handler_irq(int irq, struct pt_regs *regs);
|
||||
extern void init_irqwork_curcpu(void);
|
||||
extern void __cpuinit sun4v_register_mondo_queues(int this_cpu);
|
||||
|
||||
#endif /* _ENTRY_H */
|
||||
|
|
@ -626,7 +626,7 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
iommu_map_failed:
|
||||
for_each_sg(sglist, s, nelems, i) {
|
||||
if (s->dma_length != 0) {
|
||||
unsigned long vaddr, npages, entry, i;
|
||||
unsigned long vaddr, npages, entry, j;
|
||||
iopte_t *base;
|
||||
|
||||
vaddr = s->dma_address & IO_PAGE_MASK;
|
||||
|
|
@ -637,8 +637,8 @@ iommu_map_failed:
|
|||
>> IO_PAGE_SHIFT;
|
||||
base = iommu->page_table + entry;
|
||||
|
||||
for (i = 0; i < npages; i++)
|
||||
iopte_make_dummy(iommu, base + i);
|
||||
for (j = 0; j < npages; j++)
|
||||
iopte_make_dummy(iommu, base + j);
|
||||
|
||||
s->dma_address = DMA_ERROR_CODE;
|
||||
s->dma_length = 0;
|
||||
|
|
@ -803,7 +803,7 @@ static void dma_4u_sync_sg_for_cpu(struct device *dev,
|
|||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
}
|
||||
|
||||
const struct dma_ops sun4u_dma_ops = {
|
||||
static const struct dma_ops sun4u_dma_ops = {
|
||||
.alloc_coherent = dma_4u_alloc_coherent,
|
||||
.free_coherent = dma_4u_free_coherent,
|
||||
.map_single = dma_4u_map_single,
|
||||
|
|
|
|||
|
|
@ -44,27 +44,10 @@
|
|||
#include <asm/hypervisor.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
/* UPA nodes send interrupt packet to UltraSparc with first data reg
|
||||
* value low 5 (7 on Starfire) bits holding the IRQ identifier being
|
||||
* delivered. We must translate this into a non-vector IRQ so we can
|
||||
* set the softint on this cpu.
|
||||
*
|
||||
* To make processing these packets efficient and race free we use
|
||||
* an array of irq buckets below. The interrupt vector handler in
|
||||
* entry.S feeds incoming packets into per-cpu pil-indexed lists.
|
||||
*
|
||||
* If you make changes to ino_bucket, please update hand coded assembler
|
||||
* of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
|
||||
*/
|
||||
struct ino_bucket {
|
||||
/*0x00*/unsigned long __irq_chain_pa;
|
||||
|
||||
/* Virtual interrupt number assigned to this INO. */
|
||||
/*0x08*/unsigned int __virt_irq;
|
||||
/*0x0c*/unsigned int __pad;
|
||||
};
|
||||
#include "entry.h"
|
||||
|
||||
#define NUM_IVECS (IMAP_INR + 1)
|
||||
|
||||
struct ino_bucket *ivector_table;
|
||||
unsigned long ivector_table_pa;
|
||||
|
||||
|
|
|
|||
|
|
@ -35,6 +35,9 @@
|
|||
#include <asm/spitfire.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cpudata.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include "entry.h"
|
||||
|
||||
/* #define ALLOW_INIT_TRACING */
|
||||
|
||||
|
|
@ -67,6 +70,8 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
|
|||
if (tlb_type == hypervisor)
|
||||
return;
|
||||
|
||||
preempt_disable();
|
||||
|
||||
#ifdef DCACHE_ALIASING_POSSIBLE
|
||||
/* If bit 13 of the kernel address we used to access the
|
||||
* user page is the same as the virtual address that page
|
||||
|
|
@ -105,6 +110,8 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
|
|||
for (; start < end; start += icache_line_size)
|
||||
flushi(start);
|
||||
}
|
||||
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
enum sparc_regset {
|
||||
|
|
@ -382,6 +389,7 @@ static const struct user_regset_view user_sparc64_view = {
|
|||
.regsets = sparc64_regsets, .n = ARRAY_SIZE(sparc64_regsets)
|
||||
};
|
||||
|
||||
#ifdef CONFIG_COMPAT
|
||||
static int genregs32_get(struct task_struct *target,
|
||||
const struct user_regset *regset,
|
||||
unsigned int pos, unsigned int count,
|
||||
|
|
@ -676,14 +684,18 @@ static const struct user_regset_view user_sparc32_view = {
|
|||
.name = "sparc", .e_machine = EM_SPARC,
|
||||
.regsets = sparc32_regsets, .n = ARRAY_SIZE(sparc32_regsets)
|
||||
};
|
||||
#endif /* CONFIG_COMPAT */
|
||||
|
||||
const struct user_regset_view *task_user_regset_view(struct task_struct *task)
|
||||
{
|
||||
#ifdef CONFIG_COMPAT
|
||||
if (test_tsk_thread_flag(task, TIF_32BIT))
|
||||
return &user_sparc32_view;
|
||||
#endif
|
||||
return &user_sparc64_view;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_COMPAT
|
||||
struct compat_fps {
|
||||
unsigned int regs[32];
|
||||
unsigned int fsr;
|
||||
|
|
@ -798,6 +810,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_COMPAT */
|
||||
|
||||
struct fps {
|
||||
unsigned int regs[64];
|
||||
|
|
@ -807,11 +820,14 @@ struct fps {
|
|||
long arch_ptrace(struct task_struct *child, long request, long addr, long data)
|
||||
{
|
||||
const struct user_regset_view *view = task_user_regset_view(child);
|
||||
struct pt_regs __user *pregs = (struct pt_regs __user *) addr;
|
||||
unsigned long addr2 = task_pt_regs(current)->u_regs[UREG_I4];
|
||||
struct fps __user *fps = (struct fps __user *) addr;
|
||||
struct pt_regs __user *pregs;
|
||||
struct fps __user *fps;
|
||||
int ret;
|
||||
|
||||
pregs = (struct pt_regs __user *) (unsigned long) addr;
|
||||
fps = (struct fps __user *) (unsigned long) addr;
|
||||
|
||||
switch (request) {
|
||||
case PTRACE_PEEKUSR:
|
||||
ret = (addr != 0) ? -EIO : 0;
|
||||
|
|
|
|||
|
|
@ -51,6 +51,8 @@
|
|||
#include <net/ipconfig.h>
|
||||
#endif
|
||||
|
||||
#include "entry.h"
|
||||
|
||||
/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
|
||||
* operations in asm/ns87303.h
|
||||
*/
|
||||
|
|
@ -335,9 +337,6 @@ void __init setup_arch(char **cmdline_p)
|
|||
|
||||
/* BUFFER is PAGE_SIZE bytes long. */
|
||||
|
||||
extern char *sparc_cpu_type;
|
||||
extern char *sparc_fpu_type;
|
||||
|
||||
extern void smp_info(struct seq_file *);
|
||||
extern void smp_bogo(struct seq_file *);
|
||||
extern void mmu_info(struct seq_file *);
|
||||
|
|
|
|||
|
|
@ -32,6 +32,9 @@
|
|||
#include <asm/siginfo.h>
|
||||
#include <asm/visasm.h>
|
||||
|
||||
#include "entry.h"
|
||||
#include "systbls.h"
|
||||
|
||||
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
|
||||
|
||||
/* {set, get}context() needed for 64-bit SparcLinux userland. */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* smp.c: Sparc64 SMP support.
|
||||
*
|
||||
* Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
|
||||
* Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
|
@ -30,6 +30,7 @@
|
|||
#include <asm/cpudata.h>
|
||||
#include <asm/hvtramp.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/timer.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/irq_regs.h>
|
||||
|
|
|
|||
|
|
@ -2,13 +2,15 @@
|
|||
#include <linux/stacktrace.h>
|
||||
#include <linux/thread_info.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/stacktrace.h>
|
||||
|
||||
void save_stack_trace(struct stack_trace *trace)
|
||||
{
|
||||
unsigned long ksp, fp, thread_base;
|
||||
struct thread_info *tp = task_thread_info(current);
|
||||
|
||||
flushw_all();
|
||||
stack_trace_flush();
|
||||
|
||||
__asm__ __volatile__(
|
||||
"mov %%fp, %0"
|
||||
: "=r" (ksp)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
/* $Id: sys_sparc.c,v 1.57 2002/02/09 19:49:30 davem Exp $
|
||||
* linux/arch/sparc64/kernel/sys_sparc.c
|
||||
/* linux/arch/sparc64/kernel/sys_sparc.c
|
||||
*
|
||||
* This file contains various random system calls that
|
||||
* have a non-standard calling sequence on the Linux/sparc
|
||||
|
|
@ -30,6 +29,9 @@
|
|||
#include <asm/perfctr.h>
|
||||
#include <asm/unistd.h>
|
||||
|
||||
#include "entry.h"
|
||||
#include "systbls.h"
|
||||
|
||||
/* #define DEBUG_UNIMP_SYSCALL */
|
||||
|
||||
asmlinkage unsigned long sys_getpagesize(void)
|
||||
|
|
@ -445,7 +447,8 @@ asmlinkage long sys_ipc(unsigned int call, int first, unsigned long second,
|
|||
goto out;
|
||||
case SEMTIMEDOP:
|
||||
err = sys_semtimedop(first, ptr, (unsigned)second,
|
||||
(const struct timespec __user *) fifth);
|
||||
(const struct timespec __user *)
|
||||
(unsigned long) fifth);
|
||||
goto out;
|
||||
case SEMGET:
|
||||
err = sys_semget(first, (int)second, (int)third);
|
||||
|
|
@ -788,7 +791,7 @@ asmlinkage long sys_utrap_install(utrap_entry_t type,
|
|||
} else {
|
||||
if ((utrap_handler_t)current_thread_info()->utraps[type] != new_p &&
|
||||
current_thread_info()->utraps[0] > 1) {
|
||||
long *p = current_thread_info()->utraps;
|
||||
unsigned long *p = current_thread_info()->utraps;
|
||||
|
||||
current_thread_info()->utraps =
|
||||
kmalloc((UT_TRAP_INSTRUCTION_31+1)*sizeof(long),
|
||||
|
|
@ -816,7 +819,8 @@ asmlinkage long sys_utrap_install(utrap_entry_t type,
|
|||
return 0;
|
||||
}
|
||||
|
||||
long sparc_memory_ordering(unsigned long model, struct pt_regs *regs)
|
||||
asmlinkage long sparc_memory_ordering(unsigned long model,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
if (model >= 3)
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
#ifndef _SYSTBLS_H
|
||||
#define _SYSTBLS_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/utsname.h>
|
||||
#include <asm/utrap.h>
|
||||
#include <asm/signal.h>
|
||||
|
||||
extern asmlinkage unsigned long sys_getpagesize(void);
|
||||
extern asmlinkage unsigned long sparc_brk(unsigned long brk);
|
||||
extern asmlinkage long sparc_pipe(struct pt_regs *regs);
|
||||
extern asmlinkage long sys_ipc(unsigned int call, int first,
|
||||
unsigned long second,
|
||||
unsigned long third,
|
||||
void __user *ptr, long fifth);
|
||||
extern asmlinkage long sparc64_newuname(struct new_utsname __user *name);
|
||||
extern asmlinkage long sparc64_personality(unsigned long personality);
|
||||
extern asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
|
||||
unsigned long prot, unsigned long flags,
|
||||
unsigned long fd, unsigned long off);
|
||||
extern asmlinkage long sys64_munmap(unsigned long addr, size_t len);
|
||||
extern asmlinkage unsigned long sys64_mremap(unsigned long addr,
|
||||
unsigned long old_len,
|
||||
unsigned long new_len,
|
||||
unsigned long flags,
|
||||
unsigned long new_addr);
|
||||
extern asmlinkage unsigned long c_sys_nis_syscall(struct pt_regs *regs);
|
||||
extern asmlinkage long sys_getdomainname(char __user *name, int len);
|
||||
extern asmlinkage long solaris_syscall(struct pt_regs *regs);
|
||||
extern asmlinkage long sunos_syscall(struct pt_regs *regs);
|
||||
extern asmlinkage long sys_utrap_install(utrap_entry_t type,
|
||||
utrap_handler_t new_p,
|
||||
utrap_handler_t new_d,
|
||||
utrap_handler_t __user *old_p,
|
||||
utrap_handler_t __user *old_d);
|
||||
extern asmlinkage long sparc_memory_ordering(unsigned long model,
|
||||
struct pt_regs *regs);
|
||||
extern asmlinkage long sys_rt_sigaction(int sig,
|
||||
const struct sigaction __user *act,
|
||||
struct sigaction __user *oact,
|
||||
void __user *restorer,
|
||||
size_t sigsetsize);
|
||||
extern asmlinkage long sys_perfctr(int opcode, unsigned long arg0,
|
||||
unsigned long arg1, unsigned long arg2);
|
||||
|
||||
extern asmlinkage void sparc64_set_context(struct pt_regs *regs);
|
||||
extern asmlinkage void sparc64_get_context(struct pt_regs *regs);
|
||||
extern asmlinkage long sys_sigpause(unsigned int set);
|
||||
extern asmlinkage long sys_sigsuspend(old_sigset_t set);
|
||||
extern void do_rt_sigreturn(struct pt_regs *regs);
|
||||
|
||||
#endif /* _SYSTBLS_H */
|
||||
|
|
@ -1,7 +1,6 @@
|
|||
/* $Id: time.c,v 1.42 2002/01/23 14:33:55 davem Exp $
|
||||
* time.c: UltraSparc timer and TOD clock support.
|
||||
/* time.c: UltraSparc timer and TOD clock support.
|
||||
*
|
||||
* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
|
||||
* Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
|
||||
* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
|
||||
*
|
||||
* Based largely on code which is:
|
||||
|
|
@ -48,6 +47,8 @@
|
|||
#include <asm/uaccess.h>
|
||||
#include <asm/irq_regs.h>
|
||||
|
||||
#include "entry.h"
|
||||
|
||||
DEFINE_SPINLOCK(mostek_lock);
|
||||
DEFINE_SPINLOCK(rtc_lock);
|
||||
void __iomem *mstk48t02_regs = NULL;
|
||||
|
|
@ -508,6 +509,37 @@ static int __init has_low_battery(void)
|
|||
return (data1 == data2); /* Was the write blocked? */
|
||||
}
|
||||
|
||||
static void __init mostek_set_system_time(void __iomem *mregs)
|
||||
{
|
||||
unsigned int year, mon, day, hour, min, sec;
|
||||
u8 tmp;
|
||||
|
||||
spin_lock_irq(&mostek_lock);
|
||||
|
||||
/* Traditional Mostek chip. */
|
||||
tmp = mostek_read(mregs + MOSTEK_CREG);
|
||||
tmp |= MSTK_CREG_READ;
|
||||
mostek_write(mregs + MOSTEK_CREG, tmp);
|
||||
|
||||
sec = MSTK_REG_SEC(mregs);
|
||||
min = MSTK_REG_MIN(mregs);
|
||||
hour = MSTK_REG_HOUR(mregs);
|
||||
day = MSTK_REG_DOM(mregs);
|
||||
mon = MSTK_REG_MONTH(mregs);
|
||||
year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
|
||||
|
||||
xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
|
||||
xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
|
||||
set_normalized_timespec(&wall_to_monotonic,
|
||||
-xtime.tv_sec, -xtime.tv_nsec);
|
||||
|
||||
tmp = mostek_read(mregs + MOSTEK_CREG);
|
||||
tmp &= ~MSTK_CREG_READ;
|
||||
mostek_write(mregs + MOSTEK_CREG, tmp);
|
||||
|
||||
spin_unlock_irq(&mostek_lock);
|
||||
}
|
||||
|
||||
/* Probe for the real time clock chip. */
|
||||
static void __init set_system_time(void)
|
||||
{
|
||||
|
|
@ -520,7 +552,6 @@ static void __init set_system_time(void)
|
|||
unsigned long dregs = 0UL;
|
||||
void __iomem *bregs = 0UL;
|
||||
#endif
|
||||
u8 tmp;
|
||||
|
||||
if (!mregs && !dregs && !bregs) {
|
||||
prom_printf("Something wrong, clock regs not mapped yet.\n");
|
||||
|
|
@ -528,20 +559,11 @@ static void __init set_system_time(void)
|
|||
}
|
||||
|
||||
if (mregs) {
|
||||
spin_lock_irq(&mostek_lock);
|
||||
mostek_set_system_time(mregs);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Traditional Mostek chip. */
|
||||
tmp = mostek_read(mregs + MOSTEK_CREG);
|
||||
tmp |= MSTK_CREG_READ;
|
||||
mostek_write(mregs + MOSTEK_CREG, tmp);
|
||||
|
||||
sec = MSTK_REG_SEC(mregs);
|
||||
min = MSTK_REG_MIN(mregs);
|
||||
hour = MSTK_REG_HOUR(mregs);
|
||||
day = MSTK_REG_DOM(mregs);
|
||||
mon = MSTK_REG_MONTH(mregs);
|
||||
year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
|
||||
} else if (bregs) {
|
||||
if (bregs) {
|
||||
unsigned char val = readb(bregs + 0x0e);
|
||||
unsigned int century;
|
||||
|
||||
|
|
@ -596,14 +618,6 @@ static void __init set_system_time(void)
|
|||
xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
|
||||
set_normalized_timespec(&wall_to_monotonic,
|
||||
-xtime.tv_sec, -xtime.tv_nsec);
|
||||
|
||||
if (mregs) {
|
||||
tmp = mostek_read(mregs + MOSTEK_CREG);
|
||||
tmp &= ~MSTK_CREG_READ;
|
||||
mostek_write(mregs + MOSTEK_CREG, tmp);
|
||||
|
||||
spin_unlock_irq(&mostek_lock);
|
||||
}
|
||||
}
|
||||
|
||||
/* davem suggests we keep this within the 4M locked kernel image */
|
||||
|
|
@ -1027,7 +1041,7 @@ void __init time_init(void)
|
|||
setup_clockevent_multiplier(clock);
|
||||
|
||||
sparc64_clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(0x7fffffffffffffff, &sparc64_clockevent);
|
||||
clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent);
|
||||
sparc64_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(0xF, &sparc64_clockevent);
|
||||
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@
|
|||
#endif
|
||||
#include <asm/prom.h>
|
||||
|
||||
#include "entry.h"
|
||||
|
||||
/* When an irrecoverable trap occurs at tl > 0, the trap entry
|
||||
* code logs the trap state registers at every level in the trap
|
||||
|
|
@ -77,11 +78,6 @@ static void dump_tl1_traplog(struct tl1_traplog *p)
|
|||
}
|
||||
}
|
||||
|
||||
void do_call_debug(struct pt_regs *regs)
|
||||
{
|
||||
notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
|
||||
}
|
||||
|
||||
void bad_trap(struct pt_regs *regs, long lvl)
|
||||
{
|
||||
char buffer[32];
|
||||
|
|
@ -550,41 +546,6 @@ static unsigned long ecache_flush_physbase;
|
|||
static unsigned long ecache_flush_linesize;
|
||||
static unsigned long ecache_flush_size;
|
||||
|
||||
/* WARNING: The error trap handlers in assembly know the precise
|
||||
* layout of the following structure.
|
||||
*
|
||||
* C-level handlers below use this information to log the error
|
||||
* and then determine how to recover (if possible).
|
||||
*/
|
||||
struct cheetah_err_info {
|
||||
/*0x00*/u64 afsr;
|
||||
/*0x08*/u64 afar;
|
||||
|
||||
/* D-cache state */
|
||||
/*0x10*/u64 dcache_data[4]; /* The actual data */
|
||||
/*0x30*/u64 dcache_index; /* D-cache index */
|
||||
/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
|
||||
/*0x40*/u64 dcache_utag; /* D-cache microtag */
|
||||
/*0x48*/u64 dcache_stag; /* D-cache snooptag */
|
||||
|
||||
/* I-cache state */
|
||||
/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
|
||||
/*0x90*/u64 icache_index; /* I-cache index */
|
||||
/*0x98*/u64 icache_tag; /* I-cache phys tag */
|
||||
/*0xa0*/u64 icache_utag; /* I-cache microtag */
|
||||
/*0xa8*/u64 icache_stag; /* I-cache snooptag */
|
||||
/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
|
||||
/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
|
||||
|
||||
/* E-cache state */
|
||||
/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
|
||||
/*0xe0*/u64 ecache_index; /* E-cache index */
|
||||
/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
|
||||
|
||||
/*0xf0*/u64 __pad[32 - 30];
|
||||
};
|
||||
#define CHAFSR_INVALID ((u64)-1L)
|
||||
|
||||
/* This table is ordered in priority of errors and matches the
|
||||
* AFAR overwrite policy as well.
|
||||
*/
|
||||
|
|
@ -758,10 +719,6 @@ static struct afsr_error_table __jalapeno_error_table[] = {
|
|||
static struct afsr_error_table *cheetah_error_table;
|
||||
static unsigned long cheetah_afsr_errors;
|
||||
|
||||
/* This is allocated at boot time based upon the largest hardware
|
||||
* cpu ID in the system. We allocate two entries per cpu, one for
|
||||
* TL==0 logging and one for TL >= 1 logging.
|
||||
*/
|
||||
struct cheetah_err_info *cheetah_error_log;
|
||||
|
||||
static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
|
||||
|
|
@ -2102,7 +2059,7 @@ void do_div0(struct pt_regs *regs)
|
|||
force_sig_info(SIGFPE, &info, current);
|
||||
}
|
||||
|
||||
void instruction_dump (unsigned int *pc)
|
||||
static void instruction_dump(unsigned int *pc)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -2115,7 +2072,7 @@ void instruction_dump (unsigned int *pc)
|
|||
printk("\n");
|
||||
}
|
||||
|
||||
static void user_instruction_dump (unsigned int __user *pc)
|
||||
static void user_instruction_dump(unsigned int __user *pc)
|
||||
{
|
||||
int i;
|
||||
unsigned int buf[9];
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@
|
|||
#include <asm/prom.h>
|
||||
#include <asm/sstate.h>
|
||||
#include <asm/mdesc.h>
|
||||
#include <asm/cpudata.h>
|
||||
|
||||
#define MAX_PHYS_ADDRESS (1UL << 42UL)
|
||||
#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
|
||||
|
|
@ -1273,10 +1274,6 @@ void __cpuinit sun4v_ktsb_register(void)
|
|||
|
||||
/* paging_init() sets up the page tables */
|
||||
|
||||
extern void cheetah_ecache_flush_init(void);
|
||||
extern void sun4v_patch_tlb_handlers(void);
|
||||
|
||||
extern void cpu_probe(void);
|
||||
extern void central_probe(void);
|
||||
|
||||
static unsigned long last_valid_pfn;
|
||||
|
|
|
|||
|
|
@ -23,10 +23,11 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers) = { 0, };
|
|||
|
||||
void flush_tlb_pending(void)
|
||||
{
|
||||
struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
|
||||
struct mmu_gather *mp;
|
||||
|
||||
preempt_disable();
|
||||
|
||||
mp = &__get_cpu_var(mmu_gathers);
|
||||
if (mp->tlb_nr) {
|
||||
flush_tsb_user(mp);
|
||||
|
||||
|
|
|
|||
|
|
@ -86,6 +86,8 @@ extern struct trap_per_cpu trap_block[NR_CPUS];
|
|||
extern void init_cur_cpu_trap(struct thread_info *);
|
||||
extern void setup_tba(void);
|
||||
extern int ncpus_probed;
|
||||
extern void __init cpu_probe(void);
|
||||
extern const struct seq_operations cpuinfo_op;
|
||||
|
||||
extern unsigned long real_hard_smp_processor_id(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,26 +1,27 @@
|
|||
/* $Id: dcu.h,v 1.2 2001/03/01 23:23:33 davem Exp $ */
|
||||
#ifndef _SPARC64_DCU_H
|
||||
#define _SPARC64_DCU_H
|
||||
|
||||
#include <linux/const.h>
|
||||
|
||||
/* UltraSparc-III Data Cache Unit Control Register */
|
||||
#define DCU_CP 0x0002000000000000 /* Physical Cache Enable w/o mmu*/
|
||||
#define DCU_CV 0x0001000000000000 /* Virtual Cache Enable w/o mmu */
|
||||
#define DCU_ME 0x0000800000000000 /* NC-store Merging Enable */
|
||||
#define DCU_RE 0x0000400000000000 /* RAW bypass Enable */
|
||||
#define DCU_PE 0x0000200000000000 /* PCache Enable */
|
||||
#define DCU_HPE 0x0000100000000000 /* HW prefetch Enable */
|
||||
#define DCU_SPE 0x0000080000000000 /* SW prefetch Enable */
|
||||
#define DCU_SL 0x0000040000000000 /* Secondary load steering Enab */
|
||||
#define DCU_WE 0x0000020000000000 /* WCache enable */
|
||||
#define DCU_PM 0x000001fe00000000 /* PA Watchpoint Byte Mask */
|
||||
#define DCU_VM 0x00000001fe000000 /* VA Watchpoint Byte Mask */
|
||||
#define DCU_PR 0x0000000001000000 /* PA Watchpoint Read Enable */
|
||||
#define DCU_PW 0x0000000000800000 /* PA Watchpoint Write Enable */
|
||||
#define DCU_VR 0x0000000000400000 /* VA Watchpoint Read Enable */
|
||||
#define DCU_VW 0x0000000000200000 /* VA Watchpoint Write Enable */
|
||||
#define DCU_DM 0x0000000000000008 /* DMMU Enable */
|
||||
#define DCU_IM 0x0000000000000004 /* IMMU Enable */
|
||||
#define DCU_DC 0x0000000000000002 /* Data Cache Enable */
|
||||
#define DCU_IC 0x0000000000000001 /* Instruction Cache Enable */
|
||||
#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
|
||||
#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
|
||||
#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
|
||||
#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
|
||||
#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
|
||||
#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
|
||||
#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
|
||||
#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
|
||||
#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
|
||||
#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
|
||||
#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */
|
||||
#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
|
||||
#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
|
||||
#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
|
||||
#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
|
||||
#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
|
||||
#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
|
||||
#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */
|
||||
#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */
|
||||
|
||||
#endif /* _SPARC64_DCU_H */
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ extern unsigned char virt_irq_alloc(unsigned int dev_handle,
|
|||
extern void virt_irq_free(unsigned int virt_irq);
|
||||
#endif
|
||||
|
||||
extern void __init init_IRQ(void);
|
||||
extern void fixup_irqs(void);
|
||||
|
||||
static inline void set_softint(unsigned long bits)
|
||||
|
|
|
|||
|
|
@ -23,9 +23,9 @@
|
|||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
|
||||
* The page copy blockops can use 0x2000000 to 0x4000000.
|
||||
* The TSB is mapped in the 0x4000000 to 0x6000000 range.
|
||||
/* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
|
||||
* The page copy blockops can use 0x6000000 to 0x8000000.
|
||||
* The TSB is mapped in the 0x8000000 to 0xa000000 range.
|
||||
* The PROM resides in an area spanning 0xf0000000 to 0x100000000.
|
||||
* The vmalloc area spans 0x100000000 to 0x200000000.
|
||||
* Since modules need to be in the lowest 32-bits of the address space,
|
||||
|
|
@ -33,8 +33,8 @@
|
|||
* There is a single static kernel PMD which maps from 0x0 to address
|
||||
* 0x400000000.
|
||||
*/
|
||||
#define TLBTEMP_BASE _AC(0x0000000002000000,UL)
|
||||
#define TSBMAP_BASE _AC(0x0000000004000000,UL)
|
||||
#define TLBTEMP_BASE _AC(0x0000000006000000,UL)
|
||||
#define TSBMAP_BASE _AC(0x0000000008000000,UL)
|
||||
#define MODULES_VADDR _AC(0x0000000010000000,UL)
|
||||
#define MODULES_LEN _AC(0x00000000e0000000,UL)
|
||||
#define MODULES_END _AC(0x00000000f0000000,UL)
|
||||
|
|
@ -761,6 +761,8 @@ extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
|
|||
extern void pgtable_cache_init(void);
|
||||
extern void sun4v_register_fault_status(void);
|
||||
extern void sun4v_ktsb_register(void);
|
||||
extern void __init cheetah_ecache_flush_init(void);
|
||||
extern void sun4v_patch_tlb_handlers(void);
|
||||
|
||||
extern unsigned long cmdline_memory_size;
|
||||
|
||||
|
|
|
|||
|
|
@ -37,6 +37,9 @@
|
|||
#endif
|
||||
|
||||
#define TASK_SIZE ((unsigned long)-VPTE_SIZE)
|
||||
#define TASK_SIZE_OF(tsk) \
|
||||
(test_tsk_thread_flag(tsk,TIF_32BIT) ? \
|
||||
(1UL << 32UL) : TASK_SIZE)
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef _SPARC64_STACKTRACE_H
|
||||
#define _SPARC64_STACKTRACE_H
|
||||
|
||||
extern void stack_trace_flush(void);
|
||||
|
||||
#endif /* _SPARC64_STACKTRACE_H */
|
||||
|
|
@ -1,14 +1,13 @@
|
|||
/* $Id: timer.h,v 1.3 2000/05/09 17:40:15 davem Exp $
|
||||
* timer.h: System timer definitions for sun5.
|
||||
/* timer.h: System timer definitions for sun5.
|
||||
*
|
||||
* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
|
||||
* Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
|
||||
*/
|
||||
|
||||
#ifndef _SPARC64_TIMER_H
|
||||
#define _SPARC64_TIMER_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
struct sparc64_tick_ops {
|
||||
unsigned long (*get_tick)(void);
|
||||
|
|
@ -25,5 +24,7 @@ struct sparc64_tick_ops {
|
|||
extern struct sparc64_tick_ops *tick_ops;
|
||||
|
||||
extern unsigned long sparc64_get_clock_tick(unsigned int cpu);
|
||||
extern void __devinit setup_sparc64_timer(void);
|
||||
extern void __init time_init(void);
|
||||
|
||||
#endif /* _SPARC64_TIMER_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue