PCI: add PCI-X/PCI-Express read control interfaces
This patch introduces an interface to read and write PCI-X / PCI-Express maximum read byte count values from PCI config space. There is a second function that returns the maximum _designed_ read byte count, which marks the maximum value for a device, since some drivers try to set MMRBC to the highest allowed value and rely on such a function. Based on patch set by Stephen Hemminger <shemminger@linux-foundation.org> Cc: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Peter Oruba <peter.oruba@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -1374,6 +1374,166 @@ pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
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}
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#endif
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/**
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* pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
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* @dev: PCI device to query
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*
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* Returns mmrbc: maximum designed memory read count in bytes
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* or appropriate error value.
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*/
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int pcix_get_max_mmrbc(struct pci_dev *dev)
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{
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int ret, err, cap;
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u32 stat;
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (!cap)
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return -EINVAL;
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err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
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if (err)
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return -EINVAL;
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ret = (stat & PCI_X_STATUS_MAX_READ) >> 12;
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return ret;
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}
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EXPORT_SYMBOL(pcix_get_max_mmrbc);
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/**
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* pcix_get_mmrbc - get PCI-X maximum memory read byte count
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* @dev: PCI device to query
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*
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* Returns mmrbc: maximum memory read count in bytes
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* or appropriate error value.
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*/
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int pcix_get_mmrbc(struct pci_dev *dev)
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{
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int ret, cap;
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u32 cmd;
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (!cap)
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return -EINVAL;
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ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
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if (!ret)
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ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
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return ret;
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}
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EXPORT_SYMBOL(pcix_get_mmrbc);
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/**
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* pcix_set_mmrbc - set PCI-X maximum memory read byte count
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* @dev: PCI device to query
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* @mmrbc: maximum memory read count in bytes
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* valid values are 512, 1024, 2048, 4096
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*
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* If possible sets maximum memory read byte count, some bridges have erratas
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* that prevent this.
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*/
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int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
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{
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int cap, err = -EINVAL;
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u32 stat, cmd, v, o;
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if (mmrbc < 512 || mmrbc > 4096 || (mmrbc & (mmrbc-1)))
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goto out;
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v = ffs(mmrbc) - 10;
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (!cap)
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goto out;
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err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
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if (err)
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goto out;
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if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
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return -E2BIG;
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err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
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if (err)
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goto out;
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o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
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if (o != v) {
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if (v > o && dev->bus &&
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(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
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return -EIO;
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cmd &= ~PCI_X_CMD_MAX_READ;
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cmd |= v << 2;
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err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
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}
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out:
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return err;
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}
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EXPORT_SYMBOL(pcix_set_mmrbc);
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/**
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* pcie_get_readrq - get PCI Express read request size
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* @dev: PCI device to query
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*
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* Returns maximum memory read request in bytes
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* or appropriate error value.
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*/
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int pcie_get_readrq(struct pci_dev *dev)
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{
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int ret, cap;
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u16 ctl;
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cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (!cap)
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return -EINVAL;
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ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
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if (!ret)
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ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
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return ret;
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}
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EXPORT_SYMBOL(pcie_get_readrq);
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/**
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* pcie_set_readrq - set PCI Express maximum memory read request
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* @dev: PCI device to query
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* @count: maximum memory read count in bytes
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* valid values are 128, 256, 512, 1024, 2048, 4096
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*
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* If possible sets maximum read byte count
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*/
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int pcie_set_readrq(struct pci_dev *dev, int rq)
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{
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int cap, err = -EINVAL;
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u16 ctl, v;
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if (rq < 128 || rq > 4096 || (rq & (rq-1)))
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goto out;
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v = (ffs(rq) - 8) << 12;
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cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (!cap)
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goto out;
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err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
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if (err)
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goto out;
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if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
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ctl &= ~PCI_EXP_DEVCTL_READRQ;
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ctl |= v;
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err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
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}
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out:
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return err;
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}
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EXPORT_SYMBOL(pcie_set_readrq);
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/**
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* pci_select_bars - Make BAR mask from the type of resource
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* @dev: the PCI device for which BAR mask is made
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@ -627,6 +627,22 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
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#endif /* CONFIG_X86_IO_APIC */
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/*
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* Some settings of MMRBC can lead to data corruption so block changes.
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* See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
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*/
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static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
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{
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unsigned char revid;
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pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
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if (dev->subordinate && revid <= 0x12) {
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printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X MMRBC\n",
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revid);
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dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
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/*
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* FIXME: it is questionable that quirk_via_acpi
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@ -112,6 +112,7 @@ enum pcie_reset_state {
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typedef unsigned short __bitwise pci_bus_flags_t;
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enum pci_bus_flags {
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PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
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PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
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};
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struct pci_cap_saved_state {
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@ -549,6 +550,10 @@ void pci_intx(struct pci_dev *dev, int enable);
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void pci_msi_off(struct pci_dev *dev);
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int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
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int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
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int pcix_get_max_mmrbc(struct pci_dev *dev);
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int pcix_get_mmrbc(struct pci_dev *dev);
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int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
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int pcie_set_readrq(struct pci_dev *dev, int rq);
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void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
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int __must_check pci_assign_resource(struct pci_dev *dev, int i);
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int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
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