dl2k: BMCR_t fixes
broken use of bitfields; FUBAR on big-endian (and not valid C, strictly speaking). Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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b665982409
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d50956af74
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@ -1455,7 +1455,6 @@ mii_get_media (struct net_device *dev)
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{
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ANAR_t negotiate;
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BMSR_t bmsr;
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BMCR_t bmcr;
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MSCR_t mscr;
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MSSR_t mssr;
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int phy_addr;
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@ -1508,15 +1507,18 @@ mii_get_media (struct net_device *dev)
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}
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/* else tx_flow, rx_flow = user select */
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} else {
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bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
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if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
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printk (KERN_INFO "Operating at 100 Mbps, ");
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} else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
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printk (KERN_INFO "Operating at 10 Mbps, ");
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} else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
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__u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
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switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
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case MII_BMCR_SPEED_1000:
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printk (KERN_INFO "Operating at 1000 Mbps, ");
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break;
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case MII_BMCR_SPEED_100:
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printk (KERN_INFO "Operating at 100 Mbps, ");
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break;
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case 0:
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printk (KERN_INFO "Operating at 10 Mbps, ");
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}
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if (bmcr.bits.duplex_mode) {
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if (bmcr & MII_BMCR_DUPLEX_MODE) {
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printk ("Full duplex\n");
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} else {
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printk ("Half duplex\n");
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@ -1538,7 +1540,7 @@ static int
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mii_set_media (struct net_device *dev)
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{
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PHY_SCR_t pscr;
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BMCR_t bmcr;
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__u16 bmcr;
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BMSR_t bmsr;
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ANAR_t anar;
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int phy_addr;
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@ -1567,11 +1569,8 @@ mii_set_media (struct net_device *dev)
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/* Soft reset PHY */
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mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
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bmcr.image = 0;
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bmcr.bits.an_enable = 1;
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bmcr.bits.restart_an = 1;
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bmcr.bits.reset = 1;
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mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
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bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
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mii_write (dev, phy_addr, MII_BMCR, bmcr);
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mdelay(1);
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} else {
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/* Force speed setting */
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@ -1581,35 +1580,30 @@ mii_set_media (struct net_device *dev)
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mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
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/* 2) PHY Reset */
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bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
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bmcr.bits.reset = 1;
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mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
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bmcr = mii_read (dev, phy_addr, MII_BMCR);
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bmcr |= MII_BMCR_RESET;
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mii_write (dev, phy_addr, MII_BMCR, bmcr);
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/* 3) Power Down */
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bmcr.image = 0x1940; /* must be 0x1940 */
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mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
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bmcr = 0x1940; /* must be 0x1940 */
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mii_write (dev, phy_addr, MII_BMCR, bmcr);
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mdelay (100); /* wait a certain time */
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/* 4) Advertise nothing */
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mii_write (dev, phy_addr, MII_ANAR, 0);
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/* 5) Set media and Power Up */
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bmcr.image = 0;
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bmcr.bits.power_down = 1;
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bmcr = MII_BMCR_POWER_DOWN;
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if (np->speed == 100) {
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bmcr.bits.speed100 = 1;
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bmcr.bits.speed1000 = 0;
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bmcr |= MII_BMCR_SPEED_100;
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printk (KERN_INFO "Manual 100 Mbps, ");
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} else if (np->speed == 10) {
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bmcr.bits.speed100 = 0;
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bmcr.bits.speed1000 = 0;
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printk (KERN_INFO "Manual 10 Mbps, ");
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}
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if (np->full_duplex) {
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bmcr.bits.duplex_mode = 1;
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bmcr |= MII_BMCR_DUPLEX_MODE;
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printk ("Full duplex\n");
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} else {
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bmcr.bits.duplex_mode = 0;
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printk ("Half duplex\n");
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}
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#if 0
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@ -1618,7 +1612,7 @@ mii_set_media (struct net_device *dev)
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mscr.bits.cfg_enable = 1;
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mscr.bits.cfg_value = 0;
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#endif
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mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
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mii_write (dev, phy_addr, MII_BMCR, bmcr);
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mdelay(10);
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}
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return 0;
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@ -1629,7 +1623,6 @@ mii_get_media_pcs (struct net_device *dev)
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{
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ANAR_PCS_t negotiate;
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BMSR_t bmsr;
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BMCR_t bmcr;
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int phy_addr;
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struct netdev_private *np;
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@ -1661,9 +1654,9 @@ mii_get_media_pcs (struct net_device *dev)
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}
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/* else tx_flow, rx_flow = user select */
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} else {
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bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
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__u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
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printk (KERN_INFO "Operating at 1000 Mbps, ");
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if (bmcr.bits.duplex_mode) {
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if (bmcr & MII_BMCR_DUPLEX_MODE) {
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printk ("Full duplex\n");
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} else {
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printk ("Half duplex\n");
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@ -1684,7 +1677,7 @@ mii_get_media_pcs (struct net_device *dev)
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static int
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mii_set_media_pcs (struct net_device *dev)
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{
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BMCR_t bmcr;
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__u16 bmcr;
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ESR_t esr;
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ANAR_PCS_t anar;
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int phy_addr;
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@ -1707,29 +1700,24 @@ mii_set_media_pcs (struct net_device *dev)
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/* Soft reset PHY */
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mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
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bmcr.image = 0;
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bmcr.bits.an_enable = 1;
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bmcr.bits.restart_an = 1;
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bmcr.bits.reset = 1;
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mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
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bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
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MII_BMCR_RESET;
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mii_write (dev, phy_addr, MII_BMCR, bmcr);
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mdelay(1);
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} else {
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/* Force speed setting */
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/* PHY Reset */
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bmcr.image = 0;
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bmcr.bits.reset = 1;
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mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
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bmcr = MII_BMCR_RESET;
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mii_write (dev, phy_addr, MII_BMCR, bmcr);
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mdelay(10);
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bmcr.image = 0;
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bmcr.bits.an_enable = 0;
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if (np->full_duplex) {
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bmcr.bits.duplex_mode = 1;
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bmcr = MII_BMCR_DUPLEX_MODE;
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printk (KERN_INFO "Manual full duplex\n");
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} else {
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bmcr.bits.duplex_mode = 0;
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bmcr = 0;
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printk (KERN_INFO "Manual half duplex\n");
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}
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mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
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mii_write (dev, phy_addr, MII_BMCR, bmcr);
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mdelay(10);
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/* Advertise nothing */
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@ -298,23 +298,6 @@ enum _pcs_reg {
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};
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/* Basic Mode Control Register */
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typedef union t_MII_BMCR {
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u16 image;
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struct {
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u16 _bit_5_0:6; // bit 5:0
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u16 speed1000:1; // bit 6
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u16 col_test_enable:1; // bit 7
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u16 duplex_mode:1; // bit 8
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u16 restart_an:1; // bit 9
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u16 isolate:1; // bit 10
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u16 power_down:1; // bit 11
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u16 an_enable:1; // bit 12
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u16 speed100:1; // bit 13
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u16 loopback:1; // bit 14
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u16 reset:1; // bit 15
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} bits;
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} BMCR_t, *PBMCR_t;
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enum _mii_bmcr {
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MII_BMCR_RESET = 0x8000,
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MII_BMCR_LOOP_BACK = 0x4000,
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