Merge master.kernel.org:/home/rmk/linux-2.6-serial
* master.kernel.org:/home/rmk/linux-2.6-serial: [SERIAL] Provide Cirrus EP93xx AMBA PL010 serial support. [SERIAL] amba-pl010: allow platforms to specify modem control method [SERIAL] Remove obsoleted au1x00_uart driver [SERIAL] Small time UART configuration fix for AU1100 processor
This commit is contained in:
commit
d4965b3e2f
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@ -30,7 +30,9 @@
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/delay.h>
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#include <linux/termios.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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@ -360,6 +362,68 @@ void __init ep93xx_init_irq(void)
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/*************************************************************************
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* EP93xx peripheral handling
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*************************************************************************/
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#define EP93XX_UART_MCR_OFFSET (0x0100)
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static void ep93xx_uart_set_mctrl(struct amba_device *dev,
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void __iomem *base, unsigned int mctrl)
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{
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unsigned int mcr;
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mcr = 0;
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if (!(mctrl & TIOCM_RTS))
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mcr |= 2;
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if (!(mctrl & TIOCM_DTR))
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mcr |= 1;
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__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
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}
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static struct amba_pl010_data ep93xx_uart_data = {
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.set_mctrl = ep93xx_uart_set_mctrl,
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};
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static struct amba_device uart1_device = {
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.dev = {
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.bus_id = "apb:uart1",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART1_PHYS_BASE,
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.end = EP93XX_UART1_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART1, NO_IRQ },
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.periphid = 0x00041010,
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};
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static struct amba_device uart2_device = {
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.dev = {
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.bus_id = "apb:uart2",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART2_PHYS_BASE,
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.end = EP93XX_UART2_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART2, NO_IRQ },
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.periphid = 0x00041010,
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};
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static struct amba_device uart3_device = {
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.dev = {
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.bus_id = "apb:uart3",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART3_PHYS_BASE,
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.end = EP93XX_UART3_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART3, NO_IRQ },
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.periphid = 0x00041010,
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};
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void __init ep93xx_init_devices(void)
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{
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unsigned int v;
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@ -371,4 +435,8 @@ void __init ep93xx_init_devices(void)
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v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
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__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
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__raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
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amba_device_register(&uart1_device, &iomem_resource);
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amba_device_register(&uart2_device, &iomem_resource);
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amba_device_register(&uart3_device, &iomem_resource);
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}
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@ -15,7 +15,9 @@
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/termios.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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@ -28,6 +30,8 @@
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#include "common.h"
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static struct amba_pl010_data integrator_uart_data;
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static struct amba_device rtc_device = {
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.dev = {
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.bus_id = "mb:15",
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@ -44,6 +48,7 @@ static struct amba_device rtc_device = {
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static struct amba_device uart0_device = {
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.dev = {
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.bus_id = "mb:16",
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.platform_data = &integrator_uart_data,
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},
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.res = {
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.start = INTEGRATOR_UART0_BASE,
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@ -57,6 +62,7 @@ static struct amba_device uart0_device = {
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static struct amba_device uart1_device = {
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.dev = {
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.bus_id = "mb:17",
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.platform_data = &integrator_uart_data,
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},
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.res = {
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.start = INTEGRATOR_UART1_BASE,
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@ -115,6 +121,46 @@ static int __init integrator_init(void)
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arch_initcall(integrator_init);
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/*
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* On the Integrator platform, the port RTS and DTR are provided by
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* bits in the following SC_CTRLS register bits:
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* RTS DTR
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* UART0 7 6
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* UART1 5 4
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*/
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#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
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#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
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static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
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{
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unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
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if (dev == &uart0_device) {
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rts_mask = 1 << 4;
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dtr_mask = 1 << 5;
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} else {
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rts_mask = 1 << 6;
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dtr_mask = 1 << 7;
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}
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if (mctrl & TIOCM_RTS)
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ctrlc |= rts_mask;
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else
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ctrls |= rts_mask;
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if (mctrl & TIOCM_DTR)
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ctrlc |= dtr_mask;
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else
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ctrls |= dtr_mask;
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__raw_writel(ctrls, SC_CTRLS);
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__raw_writel(ctrlc, SC_CTRLC);
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}
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static struct amba_pl010_data integrator_uart_data = {
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.set_mctrl = integrator_uart_set_mctrl,
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};
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#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET
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static DEFINE_SPINLOCK(cm_lock);
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@ -94,7 +94,7 @@ void __init plat_setup(void)
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argptr = prom_getcmdline();
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#if defined(CONFIG_SERIAL_AU1X00_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE)
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#ifdef CONFIG_SERIAL_8250_CONSOLE
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if ((argptr = strstr(argptr, "console=")) == NULL) {
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argptr = prom_getcmdline();
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strcat(argptr, " console=ttyS0,115200");
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@ -51,7 +51,7 @@ static struct plat_serial8250_port au1x00_data[] = {
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#elif defined(CONFIG_SOC_AU1100)
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PORT(UART0_ADDR, AU1100_UART0_INT),
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PORT(UART1_ADDR, AU1100_UART1_INT),
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PORT(UART2_ADDR, AU1100_UART2_INT),
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/* The internal UART2 does not exist on the AU1100 processor. */
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PORT(UART3_ADDR, AU1100_UART3_INT),
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#elif defined(CONFIG_SOC_AU1550)
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PORT(UART0_ADDR, AU1550_UART0_INT),
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@ -620,22 +620,6 @@ config SERIAL_SH_SCI_CONSOLE
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depends on SERIAL_SH_SCI=y
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select SERIAL_CORE_CONSOLE
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config SERIAL_AU1X00
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bool "Enable Au1x00 UART Support"
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depends on MIPS && SOC_AU1X00
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select SERIAL_CORE
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help
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If you have an Alchemy AU1X00 processor (MIPS based) and you want
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to use serial ports, say Y. Otherwise, say N.
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config SERIAL_AU1X00_CONSOLE
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bool "Enable Au1x00 serial console"
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depends on SERIAL_AU1X00
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select SERIAL_CORE_CONSOLE
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help
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If you have an Alchemy AU1X00 processor (MIPS based) and you want
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to use a console on a serial port, say Y. Otherwise, say N.
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config SERIAL_CORE
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tristate
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@ -41,7 +41,6 @@ obj-$(CONFIG_SERIAL_COLDFIRE) += mcfserial.o
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obj-$(CONFIG_V850E_UART) += v850e_uart.o
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obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
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obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o
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obj-$(CONFIG_SERIAL_AU1X00) += au1x00_uart.o
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obj-$(CONFIG_SERIAL_DZ) += dz.o
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obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
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obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
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@ -51,8 +51,6 @@
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#include <linux/amba/serial.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/hardware.h>
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#define UART_NR 2
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@ -65,26 +63,16 @@
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#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
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#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
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#define UART_DUMMY_RSR_RX /*256*/0
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#define UART_DUMMY_RSR_RX 256
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#define UART_PORT_SIZE 64
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/*
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* On the Integrator platform, the port RTS and DTR are provided by
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* bits in the following SC_CTRLS register bits:
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* RTS DTR
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* UART0 7 6
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* UART1 5 4
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*/
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#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
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#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
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/*
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* We wrap our port structure around the generic uart_port.
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*/
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struct uart_amba_port {
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struct uart_port port;
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unsigned int dtr_mask;
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unsigned int rts_mask;
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struct amba_device *dev;
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struct amba_pl010_data *data;
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unsigned int old_status;
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};
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@ -300,20 +288,9 @@ static unsigned int pl010_get_mctrl(struct uart_port *port)
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static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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unsigned int ctrls = 0, ctrlc = 0;
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if (mctrl & TIOCM_RTS)
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ctrlc |= uap->rts_mask;
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else
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ctrls |= uap->rts_mask;
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if (mctrl & TIOCM_DTR)
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ctrlc |= uap->dtr_mask;
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else
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ctrls |= uap->dtr_mask;
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__raw_writel(ctrls, SC_CTRLS);
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__raw_writel(ctrlc, SC_CTRLC);
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if (uap->data)
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uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
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}
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static void pl010_break_ctl(struct uart_port *port, int break_state)
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@ -539,38 +516,7 @@ static struct uart_ops amba_pl010_pops = {
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.verify_port = pl010_verify_port,
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};
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static struct uart_amba_port amba_ports[UART_NR] = {
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{
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.port = {
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.membase = (void *)IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.mapbase = INTEGRATOR_UART0_BASE,
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.iotype = UPIO_MEM,
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.irq = IRQ_UARTINT0,
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.uartclk = 14745600,
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.fifosize = 16,
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.ops = &amba_pl010_pops,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 0,
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},
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.dtr_mask = 1 << 5,
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.rts_mask = 1 << 4,
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},
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{
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.port = {
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.membase = (void *)IO_ADDRESS(INTEGRATOR_UART1_BASE),
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.mapbase = INTEGRATOR_UART1_BASE,
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.iotype = UPIO_MEM,
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.irq = IRQ_UARTINT1,
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.uartclk = 14745600,
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.fifosize = 16,
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.ops = &amba_pl010_pops,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 1,
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},
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.dtr_mask = 1 << 7,
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.rts_mask = 1 << 6,
|
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}
|
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};
|
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static struct uart_amba_port *amba_ports[UART_NR];
|
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|
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#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
|
||||
|
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|
@ -588,7 +534,7 @@ static void pl010_console_putchar(struct uart_port *port, int ch)
|
|||
static void
|
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pl010_console_write(struct console *co, const char *s, unsigned int count)
|
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{
|
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struct uart_port *port = &amba_ports[co->index].port;
|
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struct uart_port *port = &amba_ports[co->index]->port;
|
||||
unsigned int status, old_cr;
|
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|
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/*
|
||||
|
@ -651,7 +597,7 @@ static int __init pl010_console_setup(struct console *co, char *options)
|
|||
*/
|
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if (co->index >= UART_NR)
|
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co->index = 0;
|
||||
port = &amba_ports[co->index].port;
|
||||
port = &amba_ports[co->index]->port;
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
@ -672,24 +618,6 @@ static struct console amba_console = {
|
|||
.data = &amba_reg,
|
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};
|
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|
||||
static int __init amba_console_init(void)
|
||||
{
|
||||
/*
|
||||
* All port initializations are done statically
|
||||
*/
|
||||
register_console(&amba_console);
|
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return 0;
|
||||
}
|
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console_initcall(amba_console_init);
|
||||
|
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static int __init amba_late_console_init(void)
|
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{
|
||||
if (!(amba_console.flags & CON_ENABLED))
|
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register_console(&amba_console);
|
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return 0;
|
||||
}
|
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late_initcall(amba_late_console_init);
|
||||
|
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#define AMBA_CONSOLE &amba_console
|
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#else
|
||||
#define AMBA_CONSOLE NULL
|
||||
|
@ -707,30 +635,76 @@ static struct uart_driver amba_reg = {
|
|||
|
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static int pl010_probe(struct amba_device *dev, void *id)
|
||||
{
|
||||
int i;
|
||||
struct uart_amba_port *port;
|
||||
void __iomem *base;
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < UART_NR; i++) {
|
||||
if (amba_ports[i].port.mapbase != dev->res.start)
|
||||
continue;
|
||||
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
|
||||
if (amba_ports[i] == NULL)
|
||||
break;
|
||||
|
||||
amba_ports[i].port.dev = &dev->dev;
|
||||
uart_add_one_port(&amba_reg, &amba_ports[i].port);
|
||||
amba_set_drvdata(dev, &amba_ports[i]);
|
||||
break;
|
||||
if (i == ARRAY_SIZE(amba_ports)) {
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
return 0;
|
||||
port = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
|
||||
if (!port) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
base = ioremap(dev->res.start, PAGE_SIZE);
|
||||
if (!base) {
|
||||
ret = -ENOMEM;
|
||||
goto free;
|
||||
}
|
||||
|
||||
port->port.dev = &dev->dev;
|
||||
port->port.mapbase = dev->res.start;
|
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port->port.membase = base;
|
||||
port->port.iotype = UPIO_MEM;
|
||||
port->port.irq = dev->irq[0];
|
||||
port->port.uartclk = 14745600;
|
||||
port->port.fifosize = 16;
|
||||
port->port.ops = &amba_pl010_pops;
|
||||
port->port.flags = UPF_BOOT_AUTOCONF;
|
||||
port->port.line = i;
|
||||
port->dev = dev;
|
||||
port->data = dev->dev.platform_data;
|
||||
|
||||
amba_ports[i] = port;
|
||||
|
||||
amba_set_drvdata(dev, port);
|
||||
ret = uart_add_one_port(&amba_reg, &port->port);
|
||||
if (ret) {
|
||||
amba_set_drvdata(dev, NULL);
|
||||
amba_ports[i] = NULL;
|
||||
iounmap(base);
|
||||
free:
|
||||
kfree(port);
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pl010_remove(struct amba_device *dev)
|
||||
{
|
||||
struct uart_amba_port *uap = amba_get_drvdata(dev);
|
||||
|
||||
if (uap)
|
||||
uart_remove_one_port(&amba_reg, &uap->port);
|
||||
struct uart_amba_port *port = amba_get_drvdata(dev);
|
||||
int i;
|
||||
|
||||
amba_set_drvdata(dev, NULL);
|
||||
|
||||
uart_remove_one_port(&amba_reg, &port->port);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
|
||||
if (amba_ports[i] == port)
|
||||
amba_ports[i] = NULL;
|
||||
|
||||
iounmap(port->port.membase);
|
||||
kfree(port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -103,88 +103,6 @@
|
|||
#define IVR_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_AU1X00
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#ifdef CONFIG_SOC_AU1000
|
||||
#define AU1000_SERIAL_PORT_DEFNS \
|
||||
{ .baud_base = 0, .port = UART0_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART0_ADDR, \
|
||||
.irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART1_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART1_ADDR, \
|
||||
.irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART2_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART2_ADDR, \
|
||||
.irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART3_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART3_ADDR, \
|
||||
.irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 },
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AU1500
|
||||
#define AU1000_SERIAL_PORT_DEFNS \
|
||||
{ .baud_base = 0, .port = UART0_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART0_ADDR, \
|
||||
.irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART3_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART3_ADDR, \
|
||||
.irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 },
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AU1100
|
||||
#define AU1000_SERIAL_PORT_DEFNS \
|
||||
{ .baud_base = 0, .port = UART0_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART0_ADDR, \
|
||||
.irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART1_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART1_ADDR, \
|
||||
.irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART3_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART3_ADDR, \
|
||||
.irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 },
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AU1550
|
||||
#define AU1000_SERIAL_PORT_DEFNS \
|
||||
{ .baud_base = 0, .port = UART0_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART0_ADDR, \
|
||||
.irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART1_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART1_ADDR, \
|
||||
.irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART3_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART3_ADDR, \
|
||||
.irq = AU1550_UART3_INT, .flags = STD_COM_FLAGS,\
|
||||
.iomem_reg_shift = 2 },
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AU1200
|
||||
#define AU1000_SERIAL_PORT_DEFNS \
|
||||
{ .baud_base = 0, .port = UART0_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART0_ADDR, \
|
||||
.irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 }, \
|
||||
{ .baud_base = 0, .port = UART1_ADDR, \
|
||||
.iomem_base = (unsigned char *)UART1_ADDR, \
|
||||
.irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
|
||||
.iomem_reg_shift = 2 },
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define AU1000_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
|
||||
#define STD_SERIAL_PORT_DEFNS \
|
||||
/* UART CLK PORT IRQ FLAGS */ \
|
||||
|
@ -331,7 +249,6 @@
|
|||
MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
|
||||
MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
|
||||
MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
|
||||
MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
|
||||
AU1000_SERIAL_PORT_DEFNS
|
||||
MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
|
||||
|
||||
#endif /* _ASM_SERIAL_H */
|
||||
|
|
|
@ -158,4 +158,10 @@
|
|||
#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
|
||||
#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct amba_pl010_data {
|
||||
void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue