ASoC: mcbsp: Add McBSP support for OMAP4
This patch adds McBSP support for the OMAP4 CPU Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ti.com> Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
parent
991e02b446
commit
d4686c654b
|
@ -102,6 +102,17 @@ static const int omap24xx_dma_reqs[][2] = {
|
||||||
static const int omap24xx_dma_reqs[][2] = {};
|
static const int omap24xx_dma_reqs[][2] = {};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_OMAP4)
|
||||||
|
static const int omap44xx_dma_reqs[][2] = {
|
||||||
|
{ OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX },
|
||||||
|
{ OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX },
|
||||||
|
{ OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX },
|
||||||
|
{ OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX },
|
||||||
|
};
|
||||||
|
#else
|
||||||
|
static const int omap44xx_dma_reqs[][2] = {};
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_OMAP2420)
|
#if defined(CONFIG_ARCH_OMAP2420)
|
||||||
static const unsigned long omap2420_mcbsp_port[][2] = {
|
static const unsigned long omap2420_mcbsp_port[][2] = {
|
||||||
{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
|
{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
|
||||||
|
@ -147,6 +158,21 @@ static const unsigned long omap34xx_mcbsp_port[][2] = {
|
||||||
static const unsigned long omap34xx_mcbsp_port[][2] = {};
|
static const unsigned long omap34xx_mcbsp_port[][2] = {};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_OMAP4)
|
||||||
|
static const unsigned long omap44xx_mcbsp_port[][2] = {
|
||||||
|
{ OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
|
||||||
|
OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
|
||||||
|
{ OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
|
||||||
|
OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
|
||||||
|
{ OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
|
||||||
|
OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
|
||||||
|
{ OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
|
||||||
|
OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
|
||||||
|
};
|
||||||
|
#else
|
||||||
|
static const unsigned long omap44xx_mcbsp_port[][2] = {};
|
||||||
|
#endif
|
||||||
|
|
||||||
static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
|
static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
|
||||||
{
|
{
|
||||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||||
|
@ -224,7 +250,7 @@ static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
|
||||||
* 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
|
* 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
|
||||||
* 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
|
* 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
|
||||||
*/
|
*/
|
||||||
if (cpu_is_omap343x()) {
|
if (cpu_is_omap343x() || cpu_is_omap44xx()) {
|
||||||
/*
|
/*
|
||||||
* Rule for the buffer size. We should not allow
|
* Rule for the buffer size. We should not allow
|
||||||
* smaller buffer than the FIFO size to avoid underruns
|
* smaller buffer than the FIFO size to avoid underruns
|
||||||
|
@ -332,6 +358,9 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
|
||||||
} else if (cpu_is_omap343x()) {
|
} else if (cpu_is_omap343x()) {
|
||||||
dma = omap24xx_dma_reqs[bus_id][substream->stream];
|
dma = omap24xx_dma_reqs[bus_id][substream->stream];
|
||||||
port = omap34xx_mcbsp_port[bus_id][substream->stream];
|
port = omap34xx_mcbsp_port[bus_id][substream->stream];
|
||||||
|
} else if (cpu_is_omap44xx()) {
|
||||||
|
dma = omap44xx_dma_reqs[bus_id][substream->stream];
|
||||||
|
port = omap44xx_mcbsp_port[bus_id][substream->stream];
|
||||||
} else {
|
} else {
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
|
@ -498,11 +527,11 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
|
||||||
regs->spcr2 |= XINTM(3) | FREE;
|
regs->spcr2 |= XINTM(3) | FREE;
|
||||||
regs->spcr1 |= RINTM(3);
|
regs->spcr1 |= RINTM(3);
|
||||||
/* RFIG and XFIG are not defined in 34xx */
|
/* RFIG and XFIG are not defined in 34xx */
|
||||||
if (!cpu_is_omap34xx()) {
|
if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
|
||||||
regs->rcr2 |= RFIG;
|
regs->rcr2 |= RFIG;
|
||||||
regs->xcr2 |= XFIG;
|
regs->xcr2 |= XFIG;
|
||||||
}
|
}
|
||||||
if (cpu_is_omap2430() || cpu_is_omap34xx()) {
|
if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
|
||||||
regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
|
regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
|
||||||
regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
|
regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
|
||||||
}
|
}
|
||||||
|
|
|
@ -50,6 +50,10 @@ enum omap_mcbsp_div {
|
||||||
#undef NUM_LINKS
|
#undef NUM_LINKS
|
||||||
#define NUM_LINKS 3
|
#define NUM_LINKS 3
|
||||||
#endif
|
#endif
|
||||||
|
#if defined(CONFIG_ARCH_OMAP4)
|
||||||
|
#undef NUM_LINKS
|
||||||
|
#define NUM_LINKS 4
|
||||||
|
#endif
|
||||||
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
|
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
|
||||||
#undef NUM_LINKS
|
#undef NUM_LINKS
|
||||||
#define NUM_LINKS 5
|
#define NUM_LINKS 5
|
||||||
|
|
Loading…
Reference in New Issue