crypto: atmel-aes - add support to GCM mode
This patch adds support to the GCM mode. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Cyrille Pitchen
Herbert Xu
parent
129f8bb6bb
commit
d4419548db
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@ -383,6 +383,7 @@ config CRYPTO_DEV_ATMEL_AES
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tristate "Support for Atmel AES hw accelerator"
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depends on AT_XDMAC || AT_HDMAC || COMPILE_TEST
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select CRYPTO_AES
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select CRYPTO_AEAD
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select CRYPTO_BLKCIPHER
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help
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Some Atmel processors have AES hw accelerator.
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@ -9,6 +9,7 @@
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#define AES_MR 0x04
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#define AES_MR_CYPHER_DEC (0 << 0)
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#define AES_MR_CYPHER_ENC (1 << 0)
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#define AES_MR_GTAGEN (1 << 1)
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#define AES_MR_DUALBUFF (1 << 3)
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#define AES_MR_PROCDLY_MASK (0xF << 4)
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#define AES_MR_PROCDLY_OFFSET 4
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@ -26,6 +27,7 @@
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#define AES_MR_OPMOD_OFB (0x2 << 12)
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#define AES_MR_OPMOD_CFB (0x3 << 12)
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#define AES_MR_OPMOD_CTR (0x4 << 12)
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#define AES_MR_OPMOD_GCM (0x5 << 12)
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#define AES_MR_LOD (0x1 << 15)
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#define AES_MR_CFBS_MASK (0x7 << 16)
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#define AES_MR_CFBS_128b (0x0 << 16)
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@ -44,6 +46,7 @@
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#define AES_ISR 0x1C
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#define AES_INT_DATARDY (1 << 0)
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#define AES_INT_URAD (1 << 8)
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#define AES_INT_TAGRDY (1 << 16)
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#define AES_ISR_URAT_MASK (0xF << 12)
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#define AES_ISR_URAT_IDR_WR_PROC (0x0 << 12)
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#define AES_ISR_URAT_ODR_RD_PROC (0x1 << 12)
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@ -57,6 +60,13 @@
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#define AES_ODATAR(x) (0x50 + ((x) * 0x04))
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#define AES_IVR(x) (0x60 + ((x) * 0x04))
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#define AES_AADLENR 0x70
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#define AES_CLENR 0x74
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#define AES_GHASHR(x) (0x78 + ((x) * 0x04))
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#define AES_TAGR(x) (0x88 + ((x) * 0x04))
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#define AES_CTRR 0x98
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#define AES_GCMHR(x) (0x9c + ((x) * 0x04))
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#define AES_HW_VERSION 0xFC
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#endif /* __ATMEL_AES_REGS_H__ */
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@ -36,6 +36,7 @@
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#include <crypto/scatterwalk.h>
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#include <crypto/algapi.h>
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#include <crypto/aes.h>
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#include <crypto/internal/aead.h>
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#include <linux/platform_data/crypto-atmel.h>
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#include <dt-bindings/dma/at91.h>
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#include "atmel-aes-regs.h"
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@ -53,8 +54,9 @@
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#define SIZE_IN_WORDS(x) ((x) >> 2)
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/* AES flags */
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/* Reserve bits [18:16] [14:12] [0] for mode (same as for AES_MR) */
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/* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */
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#define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
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#define AES_FLAGS_GTAGEN AES_MR_GTAGEN
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#define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
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#define AES_FLAGS_ECB AES_MR_OPMOD_ECB
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#define AES_FLAGS_CBC AES_MR_OPMOD_CBC
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@ -65,9 +67,11 @@
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#define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
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#define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
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#define AES_FLAGS_CTR AES_MR_OPMOD_CTR
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#define AES_FLAGS_GCM AES_MR_OPMOD_GCM
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#define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
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AES_FLAGS_ENCRYPT)
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AES_FLAGS_ENCRYPT | \
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AES_FLAGS_GTAGEN)
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#define AES_FLAGS_INIT BIT(2)
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#define AES_FLAGS_BUSY BIT(3)
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@ -83,6 +87,7 @@ struct atmel_aes_caps {
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bool has_dualbuff;
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bool has_cfb64;
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bool has_ctr32;
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bool has_gcm;
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u32 max_burst_size;
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};
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@ -113,6 +118,22 @@ struct atmel_aes_ctr_ctx {
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struct scatterlist dst[2];
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};
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struct atmel_aes_gcm_ctx {
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struct atmel_aes_base_ctx base;
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struct scatterlist src[2];
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struct scatterlist dst[2];
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u32 j0[AES_BLOCK_SIZE / sizeof(u32)];
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u32 tag[AES_BLOCK_SIZE / sizeof(u32)];
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u32 ghash[AES_BLOCK_SIZE / sizeof(u32)];
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size_t textlen;
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const u32 *ghash_in;
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u32 *ghash_out;
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atmel_aes_fn_t ghash_resume;
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};
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struct atmel_aes_reqctx {
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unsigned long mode;
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};
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@ -234,6 +255,12 @@ static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
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return len ? block_size - len : 0;
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}
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static inline struct aead_request *
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aead_request_cast(struct crypto_async_request *req)
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{
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return container_of(req, struct aead_request, base);
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}
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static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
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{
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struct atmel_aes_dev *aes_dd = NULL;
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@ -300,6 +327,11 @@ static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
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dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
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}
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static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
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{
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return (dd->flags & AES_FLAGS_ENCRYPT);
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}
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static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
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{
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clk_disable_unprepare(dd->iclk);
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@ -1226,6 +1258,409 @@ static struct crypto_alg aes_cfb64_alg = {
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};
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/* gcm aead functions */
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static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
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const u32 *data, size_t datalen,
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const u32 *ghash_in, u32 *ghash_out,
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atmel_aes_fn_t resume);
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static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd);
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static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd);
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static int atmel_aes_gcm_start(struct atmel_aes_dev *dd);
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static int atmel_aes_gcm_process(struct atmel_aes_dev *dd);
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static int atmel_aes_gcm_length(struct atmel_aes_dev *dd);
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static int atmel_aes_gcm_data(struct atmel_aes_dev *dd);
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static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd);
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static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd);
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static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd);
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static inline struct atmel_aes_gcm_ctx *
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atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx)
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{
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return container_of(ctx, struct atmel_aes_gcm_ctx, base);
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}
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static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
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const u32 *data, size_t datalen,
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const u32 *ghash_in, u32 *ghash_out,
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atmel_aes_fn_t resume)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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dd->data = (u32 *)data;
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dd->datalen = datalen;
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ctx->ghash_in = ghash_in;
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ctx->ghash_out = ghash_out;
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ctx->ghash_resume = resume;
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atmel_aes_write_ctrl(dd, false, NULL);
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return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init);
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}
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static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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/* Set the data length. */
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atmel_aes_write(dd, AES_AADLENR, dd->total);
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atmel_aes_write(dd, AES_CLENR, 0);
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/* If needed, overwrite the GCM Intermediate Hash Word Registers */
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if (ctx->ghash_in)
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atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in);
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return atmel_aes_gcm_ghash_finalize(dd);
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}
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static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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u32 isr;
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/* Write data into the Input Data Registers. */
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while (dd->datalen > 0) {
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atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
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dd->data += 4;
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dd->datalen -= AES_BLOCK_SIZE;
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isr = atmel_aes_read(dd, AES_ISR);
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if (!(isr & AES_INT_DATARDY)) {
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dd->resume = atmel_aes_gcm_ghash_finalize;
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atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
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return -EINPROGRESS;
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}
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}
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/* Read the computed hash from GHASHRx. */
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atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out);
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return ctx->ghash_resume(dd);
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}
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static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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struct aead_request *req = aead_request_cast(dd->areq);
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struct crypto_aead *tfm = crypto_aead_reqtfm(req);
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struct atmel_aes_reqctx *rctx = aead_request_ctx(req);
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size_t ivsize = crypto_aead_ivsize(tfm);
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size_t datalen, padlen;
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const void *iv = req->iv;
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u8 *data = dd->buf;
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int err;
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atmel_aes_set_mode(dd, rctx);
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err = atmel_aes_hw_init(dd);
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if (err)
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return atmel_aes_complete(dd, err);
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if (likely(ivsize == 12)) {
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memcpy(ctx->j0, iv, ivsize);
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ctx->j0[3] = cpu_to_be32(1);
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return atmel_aes_gcm_process(dd);
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}
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padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE);
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datalen = ivsize + padlen + AES_BLOCK_SIZE;
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if (datalen > dd->buflen)
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return atmel_aes_complete(dd, -EINVAL);
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memcpy(data, iv, ivsize);
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memset(data + ivsize, 0, padlen + sizeof(u64));
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((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8);
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return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen,
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NULL, ctx->j0, atmel_aes_gcm_process);
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}
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static int atmel_aes_gcm_process(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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struct aead_request *req = aead_request_cast(dd->areq);
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struct crypto_aead *tfm = crypto_aead_reqtfm(req);
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bool enc = atmel_aes_is_encrypt(dd);
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u32 authsize;
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/* Compute text length. */
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authsize = crypto_aead_authsize(tfm);
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ctx->textlen = req->cryptlen - (enc ? 0 : authsize);
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/*
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* According to tcrypt test suite, the GCM Automatic Tag Generation
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* fails when both the message and its associated data are empty.
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*/
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if (likely(req->assoclen != 0 || ctx->textlen != 0))
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dd->flags |= AES_FLAGS_GTAGEN;
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atmel_aes_write_ctrl(dd, false, NULL);
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return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length);
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}
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static int atmel_aes_gcm_length(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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struct aead_request *req = aead_request_cast(dd->areq);
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u32 j0_lsw, *j0 = ctx->j0;
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size_t padlen;
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/* Write incr32(J0) into IV. */
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j0_lsw = j0[3];
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j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1);
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atmel_aes_write_block(dd, AES_IVR(0), j0);
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j0[3] = j0_lsw;
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/* Set aad and text lengths. */
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atmel_aes_write(dd, AES_AADLENR, req->assoclen);
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atmel_aes_write(dd, AES_CLENR, ctx->textlen);
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/* Check whether AAD are present. */
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if (unlikely(req->assoclen == 0)) {
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dd->datalen = 0;
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return atmel_aes_gcm_data(dd);
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}
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/* Copy assoc data and add padding. */
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padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE);
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if (unlikely(req->assoclen + padlen > dd->buflen))
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return atmel_aes_complete(dd, -EINVAL);
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sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen);
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/* Write assoc data into the Input Data register. */
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dd->data = (u32 *)dd->buf;
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dd->datalen = req->assoclen + padlen;
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return atmel_aes_gcm_data(dd);
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}
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static int atmel_aes_gcm_data(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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struct aead_request *req = aead_request_cast(dd->areq);
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bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD);
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struct scatterlist *src, *dst;
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u32 isr, mr;
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/* Write AAD first. */
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while (dd->datalen > 0) {
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atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
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dd->data += 4;
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dd->datalen -= AES_BLOCK_SIZE;
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isr = atmel_aes_read(dd, AES_ISR);
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if (!(isr & AES_INT_DATARDY)) {
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dd->resume = atmel_aes_gcm_data;
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atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
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return -EINPROGRESS;
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}
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}
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/* GMAC only. */
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if (unlikely(ctx->textlen == 0))
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return atmel_aes_gcm_tag_init(dd);
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/* Prepare src and dst scatter lists to transfer cipher/plain texts */
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src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen);
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dst = ((req->src == req->dst) ? src :
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scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen));
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if (use_dma) {
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/* Update the Mode Register for DMA transfers. */
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mr = atmel_aes_read(dd, AES_MR);
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mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF);
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mr |= AES_MR_SMOD_IDATAR0;
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if (dd->caps.has_dualbuff)
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mr |= AES_MR_DUALBUFF;
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atmel_aes_write(dd, AES_MR, mr);
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return atmel_aes_dma_start(dd, src, dst, ctx->textlen,
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atmel_aes_gcm_tag_init);
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}
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return atmel_aes_cpu_start(dd, src, dst, ctx->textlen,
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atmel_aes_gcm_tag_init);
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}
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static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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struct aead_request *req = aead_request_cast(dd->areq);
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u64 *data = dd->buf;
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if (likely(dd->flags & AES_FLAGS_GTAGEN)) {
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if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) {
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dd->resume = atmel_aes_gcm_tag_init;
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atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY);
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return -EINPROGRESS;
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}
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return atmel_aes_gcm_finalize(dd);
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}
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/* Read the GCM Intermediate Hash Word Registers. */
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atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash);
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data[0] = cpu_to_be64(req->assoclen * 8);
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data[1] = cpu_to_be64(ctx->textlen * 8);
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return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE,
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ctx->ghash, ctx->ghash, atmel_aes_gcm_tag);
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}
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static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
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unsigned long flags;
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/*
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* Change mode to CTR to complete the tag generation.
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* Use J0 as Initialization Vector.
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||||
*/
|
||||
flags = dd->flags;
|
||||
dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN);
|
||||
dd->flags |= AES_FLAGS_CTR;
|
||||
atmel_aes_write_ctrl(dd, false, ctx->j0);
|
||||
dd->flags = flags;
|
||||
|
||||
atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash);
|
||||
return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize);
|
||||
}
|
||||
|
||||
static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd)
|
||||
{
|
||||
struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
|
||||
struct aead_request *req = aead_request_cast(dd->areq);
|
||||
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
||||
bool enc = atmel_aes_is_encrypt(dd);
|
||||
u32 offset, authsize, itag[4], *otag = ctx->tag;
|
||||
int err;
|
||||
|
||||
/* Read the computed tag. */
|
||||
if (likely(dd->flags & AES_FLAGS_GTAGEN))
|
||||
atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag);
|
||||
else
|
||||
atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag);
|
||||
|
||||
offset = req->assoclen + ctx->textlen;
|
||||
authsize = crypto_aead_authsize(tfm);
|
||||
if (enc) {
|
||||
scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1);
|
||||
err = 0;
|
||||
} else {
|
||||
scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0);
|
||||
err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0;
|
||||
}
|
||||
|
||||
return atmel_aes_complete(dd, err);
|
||||
}
|
||||
|
||||
static int atmel_aes_gcm_crypt(struct aead_request *req,
|
||||
unsigned long mode)
|
||||
{
|
||||
struct atmel_aes_base_ctx *ctx;
|
||||
struct atmel_aes_reqctx *rctx;
|
||||
struct atmel_aes_dev *dd;
|
||||
|
||||
ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
|
||||
ctx->block_size = AES_BLOCK_SIZE;
|
||||
|
||||
dd = atmel_aes_find_dev(ctx);
|
||||
if (!dd)
|
||||
return -ENODEV;
|
||||
|
||||
rctx = aead_request_ctx(req);
|
||||
rctx->mode = AES_FLAGS_GCM | mode;
|
||||
|
||||
return atmel_aes_handle_queue(dd, &req->base);
|
||||
}
|
||||
|
||||
static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
|
||||
unsigned int keylen)
|
||||
{
|
||||
struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
|
||||
|
||||
if (keylen != AES_KEYSIZE_256 &&
|
||||
keylen != AES_KEYSIZE_192 &&
|
||||
keylen != AES_KEYSIZE_128) {
|
||||
crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
memcpy(ctx->key, key, keylen);
|
||||
ctx->keylen = keylen;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm,
|
||||
unsigned int authsize)
|
||||
{
|
||||
/* Same as crypto_gcm_authsize() from crypto/gcm.c */
|
||||
switch (authsize) {
|
||||
case 4:
|
||||
case 8:
|
||||
case 12:
|
||||
case 13:
|
||||
case 14:
|
||||
case 15:
|
||||
case 16:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_aes_gcm_encrypt(struct aead_request *req)
|
||||
{
|
||||
return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
|
||||
}
|
||||
|
||||
static int atmel_aes_gcm_decrypt(struct aead_request *req)
|
||||
{
|
||||
return atmel_aes_gcm_crypt(req, 0);
|
||||
}
|
||||
|
||||
static int atmel_aes_gcm_init(struct crypto_aead *tfm)
|
||||
{
|
||||
struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm);
|
||||
|
||||
crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx));
|
||||
ctx->base.start = atmel_aes_gcm_start;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void atmel_aes_gcm_exit(struct crypto_aead *tfm)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static struct aead_alg aes_gcm_alg = {
|
||||
.setkey = atmel_aes_gcm_setkey,
|
||||
.setauthsize = atmel_aes_gcm_setauthsize,
|
||||
.encrypt = atmel_aes_gcm_encrypt,
|
||||
.decrypt = atmel_aes_gcm_decrypt,
|
||||
.init = atmel_aes_gcm_init,
|
||||
.exit = atmel_aes_gcm_exit,
|
||||
.ivsize = 12,
|
||||
.maxauthsize = AES_BLOCK_SIZE,
|
||||
|
||||
.base = {
|
||||
.cra_name = "gcm(aes)",
|
||||
.cra_driver_name = "atmel-gcm-aes",
|
||||
.cra_priority = ATMEL_AES_PRIORITY,
|
||||
.cra_flags = CRYPTO_ALG_ASYNC,
|
||||
.cra_blocksize = 1,
|
||||
.cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx),
|
||||
.cra_alignmask = 0xf,
|
||||
.cra_module = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
/* Probe functions */
|
||||
|
||||
static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
|
||||
|
|
@ -1334,6 +1769,9 @@ static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
|
|||
{
|
||||
int i;
|
||||
|
||||
if (dd->caps.has_gcm)
|
||||
crypto_unregister_aead(&aes_gcm_alg);
|
||||
|
||||
if (dd->caps.has_cfb64)
|
||||
crypto_unregister_alg(&aes_cfb64_alg);
|
||||
|
||||
|
|
@ -1357,8 +1795,16 @@ static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
|
|||
goto err_aes_cfb64_alg;
|
||||
}
|
||||
|
||||
if (dd->caps.has_gcm) {
|
||||
err = crypto_register_aead(&aes_gcm_alg);
|
||||
if (err)
|
||||
goto err_aes_gcm_alg;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_aes_gcm_alg:
|
||||
crypto_unregister_alg(&aes_cfb64_alg);
|
||||
err_aes_cfb64_alg:
|
||||
i = ARRAY_SIZE(aes_algs);
|
||||
err_aes_algs:
|
||||
|
|
@ -1373,6 +1819,7 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
|
|||
dd->caps.has_dualbuff = 0;
|
||||
dd->caps.has_cfb64 = 0;
|
||||
dd->caps.has_ctr32 = 0;
|
||||
dd->caps.has_gcm = 0;
|
||||
dd->caps.max_burst_size = 1;
|
||||
|
||||
/* keep only major version number */
|
||||
|
|
@ -1381,12 +1828,14 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
|
|||
dd->caps.has_dualbuff = 1;
|
||||
dd->caps.has_cfb64 = 1;
|
||||
dd->caps.has_ctr32 = 1;
|
||||
dd->caps.has_gcm = 1;
|
||||
dd->caps.max_burst_size = 4;
|
||||
break;
|
||||
case 0x200:
|
||||
dd->caps.has_dualbuff = 1;
|
||||
dd->caps.has_cfb64 = 1;
|
||||
dd->caps.has_ctr32 = 1;
|
||||
dd->caps.has_gcm = 1;
|
||||
dd->caps.max_burst_size = 4;
|
||||
break;
|
||||
case 0x130:
|
||||
|
|
|
|||
Loading…
Reference in New Issue