clk: bcm2835: add missing osc and per clocks
Add AVE0, DFT, GP0, GP1, GP2, SLIM, SMI, TEC, DPI, CAM0, CAM1, DSI0E, and DSI1E. PULSE is not added because it has an extra divider. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Martin Sperl
Eric Anholt
parent
728436956a
commit
d3d6f15fd3
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@ -117,6 +117,8 @@
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#define CM_SDCCTL 0x1a8
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#define CM_SDCDIV 0x1ac
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#define CM_ARMCTL 0x1b0
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#define CM_AVEOCTL 0x1b8
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#define CM_AVEODIV 0x1bc
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#define CM_EMMCCTL 0x1c0
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#define CM_EMMCDIV 0x1c4
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@ -1594,6 +1596,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.div_reg = CM_TSENSDIV,
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.int_bits = 5,
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.frac_bits = 0),
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[BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
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.name = "tec",
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.ctl_reg = CM_TECCTL,
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.div_reg = CM_TECDIV,
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.int_bits = 6,
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.frac_bits = 0),
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/* clocks with vpu parent mux */
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[BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
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@ -1608,6 +1616,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.div_reg = CM_ISPDIV,
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.int_bits = 4,
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.frac_bits = 8),
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/*
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* Secondary SDRAM clock. Used for low-voltage modes when the PLL
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* in the SDRAM controller can't be used.
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@ -1639,6 +1648,36 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.is_vpu_clock = true),
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/* clocks with per parent mux */
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[BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
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.name = "aveo",
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.ctl_reg = CM_AVEOCTL,
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.div_reg = CM_AVEODIV,
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.int_bits = 4,
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.frac_bits = 0),
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[BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
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.name = "cam0",
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.ctl_reg = CM_CAM0CTL,
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.div_reg = CM_CAM0DIV,
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.int_bits = 4,
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.frac_bits = 8),
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[BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
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.name = "cam1",
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.ctl_reg = CM_CAM1CTL,
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.div_reg = CM_CAM1DIV,
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.int_bits = 4,
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.frac_bits = 8),
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[BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
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.name = "dft",
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.ctl_reg = CM_DFTCTL,
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.div_reg = CM_DFTDIV,
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.int_bits = 5,
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.frac_bits = 0),
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[BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
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.name = "dpi",
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.ctl_reg = CM_DPICTL,
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.div_reg = CM_DPIDIV,
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.int_bits = 4,
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.frac_bits = 8),
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/* Arasan EMMC clock */
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[BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
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@ -1647,6 +1686,29 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.div_reg = CM_EMMCDIV,
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.int_bits = 4,
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.frac_bits = 8),
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/* General purpose (GPIO) clocks */
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[BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
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.name = "gp0",
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.ctl_reg = CM_GP0CTL,
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.div_reg = CM_GP0DIV,
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.int_bits = 12,
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.frac_bits = 12,
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.is_mash_clock = true),
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[BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
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.name = "gp1",
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.ctl_reg = CM_GP1CTL,
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.div_reg = CM_GP1DIV,
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.int_bits = 12,
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.frac_bits = 12,
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.is_mash_clock = true),
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[BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
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.name = "gp2",
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.ctl_reg = CM_GP2CTL,
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.div_reg = CM_GP2DIV,
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.int_bits = 12,
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.frac_bits = 12),
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/* HDMI state machine */
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[BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
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.name = "hsm",
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@ -1668,12 +1730,26 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.int_bits = 12,
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.frac_bits = 12,
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.is_mash_clock = true),
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[BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
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.name = "slim",
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.ctl_reg = CM_SLIMCTL,
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.div_reg = CM_SLIMDIV,
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.int_bits = 12,
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.frac_bits = 12,
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.is_mash_clock = true),
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[BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
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.name = "smi",
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.ctl_reg = CM_SMICTL,
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.div_reg = CM_SMIDIV,
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.int_bits = 4,
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.frac_bits = 8),
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[BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
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.name = "uart",
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.ctl_reg = CM_UARTCTL,
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.div_reg = CM_UARTDIV,
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.int_bits = 10,
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.frac_bits = 12),
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/* TV encoder clock. Only operating frequency is 108Mhz. */
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[BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
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.name = "vec",
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@ -1682,6 +1758,20 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.int_bits = 4,
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.frac_bits = 0),
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/* dsi clocks */
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[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
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.name = "dsi0e",
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.ctl_reg = CM_DSI0ECTL,
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.div_reg = CM_DSI0EDIV,
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.int_bits = 4,
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.frac_bits = 8),
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[BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
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.name = "dsi1e",
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.ctl_reg = CM_DSI1ECTL,
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.div_reg = CM_DSI1EDIV,
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.int_bits = 4,
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.frac_bits = 8),
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/* the gates */
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/*
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@ -50,3 +50,17 @@
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#define BCM2835_PLLA_CCP2 33
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#define BCM2835_PLLD_DSI0 34
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#define BCM2835_PLLD_DSI1 35
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#define BCM2835_CLOCK_AVEO 36
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#define BCM2835_CLOCK_DFT 37
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#define BCM2835_CLOCK_GP0 38
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#define BCM2835_CLOCK_GP1 39
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#define BCM2835_CLOCK_GP2 40
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#define BCM2835_CLOCK_SLIM 41
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#define BCM2835_CLOCK_SMI 42
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#define BCM2835_CLOCK_TEC 43
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#define BCM2835_CLOCK_DPI 44
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#define BCM2835_CLOCK_CAM0 45
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#define BCM2835_CLOCK_CAM1 46
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#define BCM2835_CLOCK_DSI0E 47
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#define BCM2835_CLOCK_DSI1E 48
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