dt-bindings: dma: ti: Add document for K3 UDMA
New binding document for Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P). UDMA-P is introduced as part of the K3 architecture and can be found in AM654 and j721e. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20191223110458.30766-10-peter.ujfalusi@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Peter Ujfalusi
Vinod Koul
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings
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maintainers:
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- Peter Ujfalusi <peter.ujfalusi@ti.com>
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description: |
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The UDMA-P is intended to perform similar (but significantly upgraded)
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functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
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module supports the transmission and reception of various packet types.
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The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
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data structure compliant packets to/from smaller data blocks that are natively
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compatible with the specific requirements of each connected peripheral.
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Multiple Tx and Rx channels are provided within the DMA which allow multiple
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segmentation or reassembly operations to be ongoing. The DMA controller
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maintains state information for each of the channels which allows packet
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segmentation and reassembly operations to be time division multiplexed between
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channels in order to share the underlying DMA hardware. An external DMA
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scheduler is used to control the ordering and rate at which this multiplexing
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occurs for Transmit operations. The ordering and rate of Receive operations
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is indirectly controlled by the order in which blocks are pushed into the DMA
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on the Rx PSI-L interface.
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The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
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channels. Channels in the UDMA-P can be configured to be either Packet-Based
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or Third-Party channels on a channel by channel basis.
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All transfers within NAVSS is done between PSI-L source and destination
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threads.
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The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
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legacy, non PSI-L native peripherals. In the later case a special, small PDMA
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is tasked to act as a bridge between the PSI-L fabric and the legacy
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peripheral.
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PDMAs can be configured via UDMAP peer registers to match with the
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configuration of the legacy peripheral.
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allOf:
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- $ref: "../dma-controller.yaml#"
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properties:
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"#dma-cells":
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const: 1
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description: |
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The cell is the PSI-L thread ID of the remote (to UDMAP) end.
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Valid ranges for thread ID depends on the data movement direction:
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for source thread IDs (rx): 0 - 0x7fff
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for destination thread IDs (tx): 0x8000 - 0xffff
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Please refer to the device documentation for the PSI-L thread map and also
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the PSI-L peripheral chapter for the correct thread ID.
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compatible:
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enum:
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- ti,am654-navss-main-udmap
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- ti,am654-navss-mcu-udmap
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- ti,j721e-navss-main-udmap
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- ti,j721e-navss-mcu-udmap
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: gcfg
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- const: rchanrt
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- const: tchanrt
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msi-parent: true
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ti,sci:
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description: phandle to TI-SCI compatible System controller node
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allOf:
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- $ref: /schemas/types.yaml#/definitions/phandle
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ti,sci-dev-id:
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description: TI-SCI device id of UDMAP
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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ti,ringacc:
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description: phandle to the ring accelerator node
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allOf:
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- $ref: /schemas/types.yaml#/definitions/phandle
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ti,sci-rm-range-tchan:
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description: |
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Array of UDMA tchan resource subtypes for resource allocation for this
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host
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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# Should be enough
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maxItems: 255
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ti,sci-rm-range-rchan:
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description: |
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Array of UDMA rchan resource subtypes for resource allocation for this
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host
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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# Should be enough
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maxItems: 255
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ti,sci-rm-range-rflow:
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description: |
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Array of UDMA rflow resource subtypes for resource allocation for this
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host
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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# Should be enough
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maxItems: 255
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required:
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- compatible
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- "#dma-cells"
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- reg
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- reg-names
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- msi-parent
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- ti,sci
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- ti,sci-dev-id
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- ti,ringacc
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- ti,sci-rm-range-tchan
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- ti,sci-rm-range-rchan
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- ti,sci-rm-range-rflow
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examples:
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- |+
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cbass_main {
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#address-cells = <2>;
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#size-cells = <2>;
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cbass_main_navss: navss@30800000 {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-coherent;
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dma-ranges;
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ranges;
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ti,sci-dev-id = <118>;
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main_udmap: dma-controller@31150000 {
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compatible = "ti,am654-navss-main-udmap";
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reg = <0x0 0x31150000 0x0 0x100>,
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<0x0 0x34000000 0x0 0x100000>,
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<0x0 0x35000000 0x0 0x100000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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#dma-cells = <1>;
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ti,ringacc = <&ringacc>;
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msi-parent = <&inta_main_udmass>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <188>;
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ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
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<0x2>; /* TX_CHAN */
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ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
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<0x5>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
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};
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};
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mcasp0: mcasp@02B00000 {
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dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
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dma-names = "tx", "rx";
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};
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crypto: crypto@4E00000 {
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compatible = "ti,sa2ul-crypto";
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dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>;
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dma-names = "tx", "rx1", "rx2";
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};
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};
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