spi: atmel: add support for changing message transfer speed
The only speed available was max_speed (the maximum speed declared for a device). This patch adds the support for spi_tranfer->speed_hz parameter. We can now set a different speed for each spi message. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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@ -694,6 +694,54 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
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*plen = len;
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}
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static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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u32 scbr, csr;
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unsigned long bus_hz;
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/* v1 chips start out at half the peripheral bus speed. */
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bus_hz = clk_get_rate(as->clk);
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if (!atmel_spi_is_v2(as))
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bus_hz /= 2;
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/*
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* Calculate the lowest divider that satisfies the
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* constraint, assuming div32/fdiv/mbz == 0.
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*/
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if (xfer->speed_hz)
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scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
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else
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/*
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* This can happend if max_speed is null.
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* In this case, we set the lowest possible speed
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*/
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scbr = 0xff;
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/*
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* If the resulting divider doesn't fit into the
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* register bitfield, we can't satisfy the constraint.
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*/
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if (scbr >= (1 << SPI_SCBR_SIZE)) {
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dev_err(&spi->dev,
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"setup: %d Hz too slow, scbr %u; min %ld Hz\n",
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xfer->speed_hz, scbr, bus_hz/255);
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return -EINVAL;
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}
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if (scbr == 0) {
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dev_err(&spi->dev,
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"setup: %d Hz too high, scbr %u; max %ld Hz\n",
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xfer->speed_hz, scbr, bus_hz);
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return -EINVAL;
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}
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csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
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csr = SPI_BFINS(SCBR, scbr, csr);
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spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
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return 0;
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}
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/*
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* Submit next transfer for PDC.
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* lock is held, spi irq is blocked
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@ -731,6 +779,8 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master,
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spi_writel(as, RCR, len);
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spi_writel(as, TCR, len);
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atmel_spi_set_xfer_speed(as, msg->spi, xfer);
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dev_dbg(&msg->spi->dev,
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" start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
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xfer, xfer->len, xfer->tx_buf,
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@ -823,6 +873,7 @@ static void atmel_spi_dma_next_xfer(struct spi_master *master,
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as->current_transfer = xfer;
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len = xfer->len;
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atmel_spi_set_xfer_speed(as, msg->spi, xfer);
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}
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if (atmel_spi_use_dma(as, xfer)) {
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@ -1264,9 +1315,8 @@ static int atmel_spi_setup(struct spi_device *spi)
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{
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struct atmel_spi *as;
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struct atmel_spi_device *asd;
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u32 scbr, csr;
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u32 csr;
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unsigned int bits = spi->bits_per_word;
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unsigned long bus_hz;
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unsigned int npcs_pin;
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int ret;
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@ -1290,33 +1340,7 @@ static int atmel_spi_setup(struct spi_device *spi)
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return -EINVAL;
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}
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/* v1 chips start out at half the peripheral bus speed. */
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bus_hz = clk_get_rate(as->clk);
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if (!atmel_spi_is_v2(as))
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bus_hz /= 2;
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if (spi->max_speed_hz) {
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/*
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* Calculate the lowest divider that satisfies the
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* constraint, assuming div32/fdiv/mbz == 0.
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*/
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scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
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/*
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* If the resulting divider doesn't fit into the
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* register bitfield, we can't satisfy the constraint.
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*/
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if (scbr >= (1 << SPI_SCBR_SIZE)) {
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dev_dbg(&spi->dev,
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"setup: %d Hz too slow, scbr %u; min %ld Hz\n",
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spi->max_speed_hz, scbr, bus_hz/255);
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return -EINVAL;
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}
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} else
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/* speed zero means "as slow as possible" */
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scbr = 0xff;
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csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
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csr = SPI_BF(BITS, bits - 8);
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if (spi->mode & SPI_CPOL)
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csr |= SPI_BIT(CPOL);
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if (!(spi->mode & SPI_CPHA))
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@ -1363,8 +1387,8 @@ static int atmel_spi_setup(struct spi_device *spi)
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asd->csr = csr;
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dev_dbg(&spi->dev,
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"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
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bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
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"setup: bpw %u mode 0x%x -> csr%d %08x\n",
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bits, spi->mode, spi->chip_select, csr);
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if (!atmel_spi_is_v2(as))
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spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
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@ -1414,12 +1438,6 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
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}
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}
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/* FIXME implement these protocol options!! */
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if (xfer->speed_hz < spi->max_speed_hz) {
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dev_dbg(&spi->dev, "can't change speed in transfer\n");
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return -ENOPROTOOPT;
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}
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/*
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* DMA map early, for performance (empties dcache ASAP) and
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* better fault reporting.
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