ALSA: virtuoso: configure correct master clock frequency on the CS2000
The clock output of the CS2000, which is used as master clock for the DACs, was using half the actual master clock frequency for some reason. Using the theoretically correct frequency seems also to work in practice. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -467,7 +467,7 @@ static void xonar_st_init(struct oxygen *chip)
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oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
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OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_I2S |
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OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
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OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
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OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
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xonar_st_init_i2c(chip);
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@ -635,41 +635,40 @@ static void update_cs2000_rate(struct oxygen *chip, unsigned int rate)
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u8 rate_mclk, reg;
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switch (rate) {
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/* XXX Why is the I2S A MCLK half the actual I2S MCLK? */
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case 32000:
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rate_mclk = OXYGEN_RATE_32000 | OXYGEN_I2S_MCLK_256;
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rate_mclk = OXYGEN_RATE_32000 | OXYGEN_I2S_MCLK_512;
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break;
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case 44100:
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if (data->os_128)
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rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_256;
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rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_512;
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else
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rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_128;
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rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_256;
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break;
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default: /* 48000 */
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if (data->os_128)
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rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_256;
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rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_512;
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else
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rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_128;
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rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_256;
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break;
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case 64000:
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rate_mclk = OXYGEN_RATE_32000 | OXYGEN_I2S_MCLK_256;
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rate_mclk = OXYGEN_RATE_32000 | OXYGEN_I2S_MCLK_512;
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break;
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case 88200:
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rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_256;
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rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_512;
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break;
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case 96000:
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rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_256;
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rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_512;
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break;
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case 176400:
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rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_256;
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rate_mclk = OXYGEN_RATE_44100 | OXYGEN_I2S_MCLK_512;
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break;
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case 192000:
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rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_256;
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rate_mclk = OXYGEN_RATE_48000 | OXYGEN_I2S_MCLK_512;
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break;
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}
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oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT, rate_mclk,
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OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_MCLK_MASK);
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if ((rate_mclk & OXYGEN_I2S_MCLK_MASK) <= OXYGEN_I2S_MCLK_128)
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if ((rate_mclk & OXYGEN_I2S_MCLK_MASK) <= OXYGEN_I2S_MCLK_256)
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reg = CS2000_REF_CLK_DIV_1;
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else
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reg = CS2000_REF_CLK_DIV_2;
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