locking,arch,avr32: Fold atomic_ops
Many of the atomic op implementations are the same except for one instruction; fold the lot into a few CPP macros and reduce LoC. This also prepares for easy addition of new ops. Requires the asm_op because of eor. AVR32 is a bit special in that its ADD/SUB instructions are not symmetric. Its SUB instruction allows for an 21bit immediate. Signed-off-by: Peter Zijlstra <peterz@infradead.org> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Link: http://lkml.kernel.org/r/20140531141445.GD16155@laptop.programming.kicks-ass.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Peter Zijlstra
Ingo Molnar
parent
92ba1f530b
commit
d325209b60
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@ -22,31 +22,44 @@
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#define atomic_read(v) (*(volatile int *)&(v)->counter)
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#define atomic_set(v, i) (((v)->counter) = i)
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/*
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* atomic_sub_return - subtract the atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically subtracts @i from @v. Returns the resulting value.
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*/
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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int result;
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asm volatile(
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"/* atomic_sub_return */\n"
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"1: ssrf 5\n"
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" ld.w %0, %2\n"
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" sub %0, %3\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(result), "=o"(v->counter)
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: "m"(v->counter), "rKs21"(i)
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: "cc");
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return result;
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#define ATOMIC_OP_RETURN(op, asm_op, asm_con) \
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static inline int __atomic_##op##_return(int i, atomic_t *v) \
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{ \
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int result; \
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\
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asm volatile( \
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"/* atomic_" #op "_return */\n" \
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"1: ssrf 5\n" \
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" ld.w %0, %2\n" \
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" " #asm_op " %0, %3\n" \
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" stcond %1, %0\n" \
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" brne 1b" \
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: "=&r" (result), "=o" (v->counter) \
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: "m" (v->counter), #asm_con (i) \
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: "cc"); \
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\
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return result; \
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}
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ATOMIC_OP_RETURN(sub, sub, rKs21)
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ATOMIC_OP_RETURN(add, add, r)
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#undef ATOMIC_OP_RETURN
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/*
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* Probably found the reason why we want to use sub with the signed 21-bit
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* limit, it uses one less register than the add instruction that can add up to
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* 32-bit values.
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*
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* Both instructions are 32-bit, to use a 16-bit instruction the immediate is
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* very small; 4 bit.
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*
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* sub 32-bit, type IV, takes a register and subtracts a 21-bit immediate.
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* add 32-bit, type II, adds two register values together.
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*/
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#define IS_21BIT_CONST(i) \
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(__builtin_constant_p(i) && ((i) >= -1048575) && ((i) <= 1048576))
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/*
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* atomic_add_return - add integer to atomic variable
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* @i: integer value to add
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@ -56,51 +69,25 @@ static inline int atomic_sub_return(int i, atomic_t *v)
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*/
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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int result;
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if (IS_21BIT_CONST(i))
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return __atomic_sub_return(-i, v);
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if (__builtin_constant_p(i) && (i >= -1048575) && (i <= 1048576))
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result = atomic_sub_return(-i, v);
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else
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asm volatile(
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"/* atomic_add_return */\n"
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"1: ssrf 5\n"
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" ld.w %0, %1\n"
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" add %0, %3\n"
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" stcond %2, %0\n"
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" brne 1b"
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: "=&r"(result), "=o"(v->counter)
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: "m"(v->counter), "r"(i)
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: "cc", "memory");
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return result;
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return __atomic_add_return(i, v);
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}
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/*
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* atomic_sub_unless - sub unless the number is a given value
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* atomic_sub_return - subtract the atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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* @a: the amount to subtract from v...
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* @u: ...unless v is equal to u.
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*
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* Atomically subtract @a from @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static inline void atomic_sub_unless(atomic_t *v, int a, int u)
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* Atomically subtracts @i from @v. Returns the resulting value.
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*/
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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int tmp;
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if (IS_21BIT_CONST(i))
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return __atomic_sub_return(i, v);
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asm volatile(
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"/* atomic_sub_unless */\n"
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"1: ssrf 5\n"
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" ld.w %0, %2\n"
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" cp.w %0, %4\n"
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" breq 1f\n"
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" sub %0, %3\n"
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" stcond %1, %0\n"
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" brne 1b\n"
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"1:"
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: "=&r"(tmp), "=o"(v->counter)
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: "m"(v->counter), "rKs21"(a), "rKs21"(u)
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: "cc", "memory");
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return __atomic_add_return(-i, v);
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}
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/*
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@ -116,9 +103,21 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int tmp, old = atomic_read(v);
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if (__builtin_constant_p(a) && (a >= -1048575) && (a <= 1048576))
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atomic_sub_unless(v, -a, u);
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else {
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if (IS_21BIT_CONST(a)) {
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asm volatile(
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"/* __atomic_sub_unless */\n"
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"1: ssrf 5\n"
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" ld.w %0, %2\n"
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" cp.w %0, %4\n"
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" breq 1f\n"
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" sub %0, %3\n"
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" stcond %1, %0\n"
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" brne 1b\n"
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"1:"
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: "=&r"(tmp), "=o"(v->counter)
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: "m"(v->counter), "rKs21"(-a), "rKs21"(u)
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: "cc", "memory");
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} else {
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asm volatile(
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"/* __atomic_add_unless */\n"
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"1: ssrf 5\n"
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@ -137,6 +136,8 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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return old;
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}
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#undef IS_21BIT_CONST
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/*
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* atomic_sub_if_positive - conditionally subtract integer from atomic variable
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* @i: integer value to subtract
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