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clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel 

The MUX clock of dpi1_sel should select the closet clock for itself.
We could add this flag to enable this function of MUX in CCF.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
chunhui dai 2019-02-25 10:09:10 +08:00 committed by Stephen Boyd
parent b026a7eca1
commit d3174bc836
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/mediatek/clk-mt2701.c
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@ -535,8 +535,8 @@ static const struct mtk_composite top_muxes[] = {
0x0080, 8, 2, 15), 0x0080, 8, 2, 15),
MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
0x0080, 16, 3, 23), 0x0080, 16, 3, 23),
MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
0x0080, 24, 2, 31), 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
0x0090, 0, 3, 7), 0x0090, 0, 3, 7),