MIPS: ath79: Handle more MISC IRQs
The AR724X SoCs have more IRQ sources hooked into the MISC IRQ controller. The patch adds support for them. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2440/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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else if (pending & MISC_INT_TIMER)
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else if (pending & MISC_INT_TIMER)
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generic_handle_irq(ATH79_MISC_IRQ_TIMER);
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generic_handle_irq(ATH79_MISC_IRQ_TIMER);
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else if (pending & MISC_INT_TIMER2)
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generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
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else if (pending & MISC_INT_TIMER3)
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generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
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else if (pending & MISC_INT_TIMER4)
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generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
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else if (pending & MISC_INT_OHCI)
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else if (pending & MISC_INT_OHCI)
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generic_handle_irq(ATH79_MISC_IRQ_OHCI);
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generic_handle_irq(ATH79_MISC_IRQ_OHCI);
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@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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else if (pending & MISC_INT_WDOG)
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else if (pending & MISC_INT_WDOG)
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generic_handle_irq(ATH79_MISC_IRQ_WDOG);
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generic_handle_irq(ATH79_MISC_IRQ_WDOG);
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else if (pending & MISC_INT_ETHSW)
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generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
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else
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else
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spurious_interrupt();
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spurious_interrupt();
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}
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}
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@ -130,6 +130,10 @@
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#define AR724X_RESET_REG_RESET_MODULE 0x1c
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#define AR724X_RESET_REG_RESET_MODULE 0x1c
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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#define MISC_INT_TIMER3 BIT(9)
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#define MISC_INT_TIMER2 BIT(8)
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#define MISC_INT_DMA BIT(7)
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#define MISC_INT_DMA BIT(7)
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#define MISC_INT_OHCI BIT(6)
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#define MISC_INT_OHCI BIT(6)
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#define MISC_INT_PERFC BIT(5)
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#define MISC_INT_PERFC BIT(5)
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@ -30,6 +30,10 @@
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#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
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#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
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#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
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#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
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#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
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#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
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#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
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#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
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#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
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#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
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#include_next <irq.h>
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#include_next <irq.h>
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