This patchset adds support for federated systems where multiple memory
controllers can exist and see each other over multiple PCI domains. This basically means that AMD node ids can be more than 8 now and the code handling this is taught to incorporate PCI domain into those IDs. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQ7tvQAAoJEBLB8Bhh3lVKAdcP/iiHMUvovmwYL4H/PUUrBmKH JZnESlNIxWwRsecIQSqJO+O0SQa489cnpBV59yEMrs7Cu2sOhi7/ubbwzngzannS ab/M1GhaXn8UJ8N9NzUnxJ0KW/1cbtN1J3YgyqJ7zx9m058l3KDpDkuIyCejzRGR cFQHZUgjIUL7LNaAQmGZnAgsVbVUv+yzZhzeYxXQ2h6445H10pd6JEb6/aZTUFlL nYv2ypWdBXr27Mc8FkKdftiFw4dLUEQsNgFbBVJZtKbi4WrSTloP3dWjwo8KCtFz 1QgvsKlNOIl5DEXl0sSoTc8Jhi05eqPANke2oTu46fSwoHGKP2atmcroSdiHmDDM vH6X5K6bs1fNMxqyAjvHUnbUs2aupBMjIxobZaKBLM+arK4sSt+elRGZMZxHtjgh tHeMpVvkXDAtNX+C9frDSiFEkj2NNvuCJc8naXdQ1cDNLuanP7dnTfS3ZcHQShoI FBzz0RbRkXKXcE1sQRfzT5dmt2gdgDzFjqN4rz4fEOM3+1MFRZ/B/cKLcZ25abvc 3uweD6e6XSfFnnpz8xkr6eek3CpwHPiNYQWLXq9ick7BW5fjcHiU0Fo2rJO6G8tq vRqGU6P81sHlGrE0sLMiaYv9NqTYEERuKO05WSP9ryn3tdGebvpy116DeD5w/olo MTcWtwp69J+Eoqr7bb9z =ZzvJ -----END PGP SIGNATURE----- Merge tag 'numascale' into x86/platform This patchset adds support for federated systems where multiple memory controllers can exist and see each other over multiple PCI domains. This basically means that AMD node ids can be more than 8 now and the code handling this is taught to incorporate PCI domain into those IDs. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
H. Peter Anvin
commit
d29a4a5fe8
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@ -81,6 +81,23 @@ static inline struct amd_northbridge *node_to_amd_nb(int node)
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return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
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}
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static inline u16 amd_get_node_id(struct pci_dev *pdev)
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{
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struct pci_dev *misc;
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int i;
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for (i = 0; i != amd_nb_num(); i++) {
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misc = node_to_amd_nb(i)->misc;
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if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
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PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
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return i;
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}
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WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
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return 0;
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}
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#else
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#define amd_nb_num(x) 0
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@ -943,7 +943,7 @@ extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
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extern int get_tsc_mode(unsigned long adr);
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extern int set_tsc_mode(unsigned int val);
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extern int amd_get_nb_id(int cpu);
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extern u16 amd_get_nb_id(int cpu);
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struct aperfmperf {
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u64 aperf, mperf;
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@ -364,9 +364,9 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
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#endif
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}
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int amd_get_nb_id(int cpu)
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u16 amd_get_nb_id(int cpu)
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{
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int id = 0;
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u16 id = 0;
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#ifdef CONFIG_SMP
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id = per_cpu(cpu_llc_id, cpu);
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#endif
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@ -31,7 +31,7 @@ static struct ecc_settings **ecc_stngs;
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*
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*FIXME: Produce a better mapping/linearisation.
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*/
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struct scrubrate {
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static const struct scrubrate {
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u32 scrubval; /* bit pattern for scrub rate */
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u32 bandwidth; /* bandwidth consumed (bytes/sec) */
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} scrubrates[] = {
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@ -239,7 +239,7 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
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* DRAM base/limit associated with node_id
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*/
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static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr,
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unsigned nid)
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u8 nid)
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{
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u64 addr;
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@ -265,7 +265,7 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
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u64 sys_addr)
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{
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struct amd64_pvt *pvt;
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unsigned node_id;
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u8 node_id;
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u32 intlv_en, bits;
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/*
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@ -939,7 +939,8 @@ static u64 get_error_address(struct mce *m)
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struct amd64_pvt *pvt;
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u64 cc6_base, tmp_addr;
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u32 tmp;
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u8 mce_nid, intlv_en;
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u16 mce_nid;
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u8 intlv_en;
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if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
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return addr;
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@ -979,10 +980,29 @@ static u64 get_error_address(struct mce *m)
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return addr;
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}
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static struct pci_dev *pci_get_related_function(unsigned int vendor,
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unsigned int device,
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struct pci_dev *related)
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{
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struct pci_dev *dev = NULL;
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while ((dev = pci_get_device(vendor, device, dev))) {
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if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
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(dev->bus->number == related->bus->number) &&
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(PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
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break;
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}
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return dev;
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}
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static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
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{
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struct amd_northbridge *nb;
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struct pci_dev *misc, *f1 = NULL;
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struct cpuinfo_x86 *c = &boot_cpu_data;
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int off = range << 3;
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u32 llim;
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amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
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amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
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@ -996,30 +1016,32 @@ static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
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amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
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amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
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/* Factor in CC6 save area by reading dst node's limit reg */
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if (c->x86 == 0x15) {
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struct pci_dev *f1 = NULL;
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u8 nid = dram_dst_node(pvt, range);
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u32 llim;
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/* F15h: factor in CC6 save area by reading dst node's limit reg */
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if (c->x86 != 0x15)
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return;
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f1 = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x18 + nid, 1));
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if (WARN_ON(!f1))
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return;
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nb = node_to_amd_nb(dram_dst_node(pvt, range));
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if (WARN_ON(!nb))
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return;
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amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
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misc = nb->misc;
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f1 = pci_get_related_function(misc->vendor, PCI_DEVICE_ID_AMD_15H_NB_F1, misc);
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if (WARN_ON(!f1))
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return;
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pvt->ranges[range].lim.lo &= GENMASK(0, 15);
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amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
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/* {[39:27],111b} */
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pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
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pvt->ranges[range].lim.lo &= GENMASK(0, 15);
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pvt->ranges[range].lim.hi &= GENMASK(0, 7);
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/* {[39:27],111b} */
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pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
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/* [47:40] */
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pvt->ranges[range].lim.hi |= llim >> 13;
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pvt->ranges[range].lim.hi &= GENMASK(0, 7);
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pci_dev_put(f1);
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}
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/* [47:40] */
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pvt->ranges[range].lim.hi |= llim >> 13;
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pci_dev_put(f1);
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}
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static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
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@ -1305,7 +1327,7 @@ static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
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}
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/* Convert the sys_addr to the normalized DCT address */
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static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, unsigned range,
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static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
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u64 sys_addr, bool hi_rng,
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u32 dct_sel_base_addr)
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{
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@ -1381,7 +1403,7 @@ static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
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* -EINVAL: NOT FOUND
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* 0..csrow = Chip-Select Row
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*/
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static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct)
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static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
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{
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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@ -1672,23 +1694,6 @@ static struct amd64_family_type amd64_family_types[] = {
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},
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};
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static struct pci_dev *pci_get_related_function(unsigned int vendor,
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unsigned int device,
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struct pci_dev *related)
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{
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struct pci_dev *dev = NULL;
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dev = pci_get_device(vendor, device, dev);
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while (dev) {
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if ((dev->bus->number == related->bus->number) &&
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(PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
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break;
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dev = pci_get_device(vendor, device, dev);
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}
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return dev;
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}
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/*
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* These are tables of eigenvectors (one per line) which can be used for the
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* construction of the syndrome tables. The modified syndrome search algorithm
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@ -1696,7 +1701,7 @@ static struct pci_dev *pci_get_related_function(unsigned int vendor,
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*
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* Algorithm courtesy of Ross LaFetra from AMD.
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*/
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static u16 x4_vectors[] = {
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static const u16 x4_vectors[] = {
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0x2f57, 0x1afe, 0x66cc, 0xdd88,
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0x11eb, 0x3396, 0x7f4c, 0xeac8,
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0x0001, 0x0002, 0x0004, 0x0008,
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@ -1735,7 +1740,7 @@ static u16 x4_vectors[] = {
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0x19a9, 0x2efe, 0xb5cc, 0x6f88,
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};
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static u16 x8_vectors[] = {
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static const u16 x8_vectors[] = {
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0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
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0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
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0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
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@ -1757,7 +1762,7 @@ static u16 x8_vectors[] = {
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0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
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};
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static int decode_syndrome(u16 syndrome, u16 *vectors, unsigned num_vecs,
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static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs,
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unsigned v_dim)
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{
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unsigned int i, err_sym;
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@ -2181,7 +2186,7 @@ static int init_csrows(struct mem_ctl_info *mci)
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}
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/* get all cores on this DCT */
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static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid)
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static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
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{
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int cpu;
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@ -2191,7 +2196,7 @@ static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid)
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}
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/* check MCG_CTL on all the cpus on this node */
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static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid)
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static bool amd64_nb_mce_bank_enabled_on_node(u16 nid)
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{
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cpumask_var_t mask;
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int cpu, nbe;
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@ -2224,7 +2229,7 @@ out:
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return ret;
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}
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static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on)
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static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on)
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{
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cpumask_var_t cmask;
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int cpu;
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@ -2262,7 +2267,7 @@ static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on)
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return 0;
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}
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static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid,
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struct pci_dev *F3)
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{
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bool ret = true;
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@ -2314,7 +2319,7 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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return ret;
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}
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static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
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struct pci_dev *F3)
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{
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u32 value, mask = 0x3; /* UECC/CECC enable */
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@ -2353,7 +2358,7 @@ static const char *ecc_msg =
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"'ecc_enable_override'.\n"
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" (Note that use of the override may cause unknown side effects.)\n";
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static bool ecc_enabled(struct pci_dev *F3, u8 nid)
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static bool ecc_enabled(struct pci_dev *F3, u16 nid)
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{
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u32 value;
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u8 ecc_en = 0;
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@ -2474,7 +2479,7 @@ static int amd64_init_one_instance(struct pci_dev *F2)
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struct mem_ctl_info *mci = NULL;
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struct edac_mc_layer layers[2];
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int err = 0, ret;
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u8 nid = get_node_id(F2);
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u16 nid = amd_get_node_id(F2);
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ret = -ENOMEM;
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pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
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@ -2566,7 +2571,7 @@ err_ret:
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static int amd64_probe_one_instance(struct pci_dev *pdev,
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const struct pci_device_id *mc_type)
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{
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u8 nid = get_node_id(pdev);
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u16 nid = amd_get_node_id(pdev);
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struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
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struct ecc_settings *s;
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int ret = 0;
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@ -2616,7 +2621,7 @@ static void amd64_remove_one_instance(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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u8 nid = get_node_id(pdev);
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u16 nid = amd_get_node_id(pdev);
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struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
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struct ecc_settings *s = ecc_stngs[nid];
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|
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@ -292,12 +292,6 @@
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/* MSRs */
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#define MSR_MCGCTL_NBE BIT(4)
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/* AMD sets the first MC device at device ID 0x18. */
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static inline u8 get_node_id(struct pci_dev *pdev)
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{
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return PCI_SLOT(pdev->devfn) - 0x18;
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}
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enum amd_families {
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K8_CPUS = 0,
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F10_CPUS,
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@ -340,7 +334,7 @@ struct amd64_pvt {
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/* pci_device handles which we utilize */
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struct pci_dev *F1, *F2, *F3;
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unsigned mc_node_id; /* MC index of this MC node */
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u16 mc_node_id; /* MC index of this MC node */
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int ext_model; /* extended model value of this node */
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int channel_count;
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@ -393,7 +387,7 @@ struct err_info {
|
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u32 offset;
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};
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static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
|
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static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
|
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{
|
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u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
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@ -403,7 +397,7 @@ static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
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return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
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}
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static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
|
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static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
|
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{
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u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
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||||
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||||
|
|
|
|||
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