[ARM] pxa/dma: add debugfs entries
Add some debug information for PXA DMA : - descriptors queued - channels state - global state -- Since V1: reverted to old register access (no more dma_readl() or dma_writel()). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
This commit is contained in:
Robert Jarzmik
Eric Miao
parent
d46f5e4a20
commit
d294948c2c
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@ -17,22 +17,266 @@
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/dma-mapping.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/memory.h>
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#include <mach/hardware.h>
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#include <mach/dma.h>
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#define DMA_DEBUG_NAME "pxa_dma"
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#define DMA_MAX_REQUESTERS 64
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struct dma_channel {
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char *name;
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pxa_dma_prio prio;
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void (*irq_handler)(int, void *);
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void *data;
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spinlock_t lock;
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};
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static struct dma_channel *dma_channels;
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static int num_dma_channels;
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/*
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* Debug fs
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*/
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#include <linux/uaccess.h>
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#include <linux/seq_file.h>
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static struct dentry *dbgfs_root, *dbgfs_state, **dbgfs_chan;
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static int dbg_show_requester_chan(struct seq_file *s, void *p)
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{
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int pos = 0;
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int chan = (int)s->private;
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int i;
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u32 drcmr;
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pos += seq_printf(s, "DMA channel %d requesters list :\n", chan);
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for (i = 0; i < DMA_MAX_REQUESTERS; i++) {
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drcmr = DRCMR(i);
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if ((drcmr & DRCMR_CHLNUM) == chan)
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pos += seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i,
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!!(drcmr & DRCMR_MAPVLD));
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}
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return pos;
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}
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static inline int dbg_burst_from_dcmd(u32 dcmd)
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{
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int burst = (dcmd >> 16) & 0x3;
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return burst ? 4 << burst : 0;
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}
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static int is_phys_valid(unsigned long addr)
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{
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return pfn_valid(__phys_to_pfn(addr));
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}
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#define DCSR_STR(flag) (dcsr & DCSR_##flag ? #flag" " : "")
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#define DCMD_STR(flag) (dcmd & DCMD_##flag ? #flag" " : "")
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static int dbg_show_descriptors(struct seq_file *s, void *p)
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{
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int pos = 0;
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int chan = (int)s->private;
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int i, max_show = 20, burst, width;
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u32 dcmd;
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unsigned long phys_desc;
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struct pxa_dma_desc *desc;
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unsigned long flags;
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spin_lock_irqsave(&dma_channels[chan].lock, flags);
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phys_desc = DDADR(chan);
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pos += seq_printf(s, "DMA channel %d descriptors :\n", chan);
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pos += seq_printf(s, "[%03d] First descriptor unknown\n", 0);
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for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
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desc = phys_to_virt(phys_desc);
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dcmd = desc->dcmd;
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burst = dbg_burst_from_dcmd(dcmd);
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width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
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pos += seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
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i, phys_desc, desc);
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pos += seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
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pos += seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
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pos += seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
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pos += seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d"
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" width=%d len=%d)\n",
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dcmd,
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DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR),
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DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG),
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DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN),
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DCMD_STR(ENDIAN), burst, width,
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dcmd & DCMD_LENGTH);
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phys_desc = desc->ddadr;
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}
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if (i == max_show)
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pos += seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
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i, phys_desc);
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else
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pos += seq_printf(s, "[%03d] Desc at %08lx is %s\n",
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i, phys_desc, phys_desc == DDADR_STOP ?
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"DDADR_STOP" : "invalid");
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spin_unlock_irqrestore(&dma_channels[chan].lock, flags);
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return pos;
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}
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static int dbg_show_chan_state(struct seq_file *s, void *p)
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{
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int pos = 0;
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int chan = (int)s->private;
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u32 dcsr, dcmd;
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int burst, width;
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static char *str_prio[] = { "high", "normal", "low" };
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dcsr = DCSR(chan);
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dcmd = DCMD(chan);
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burst = dbg_burst_from_dcmd(dcmd);
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width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
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pos += seq_printf(s, "DMA channel %d\n", chan);
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pos += seq_printf(s, "\tPriority : %s\n",
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str_prio[dma_channels[chan].prio]);
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pos += seq_printf(s, "\tUnaligned transfer bit: %s\n",
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DALGN & (1 << chan) ? "yes" : "no");
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pos += seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
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dcsr, DCSR_STR(RUN), DCSR_STR(NODESC),
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DCSR_STR(STOPIRQEN), DCSR_STR(EORIRQEN),
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DCSR_STR(EORJMPEN), DCSR_STR(EORSTOPEN),
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DCSR_STR(SETCMPST), DCSR_STR(CLRCMPST),
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DCSR_STR(CMPST), DCSR_STR(EORINTR), DCSR_STR(REQPEND),
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DCSR_STR(STOPSTATE), DCSR_STR(ENDINTR),
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DCSR_STR(STARTINTR), DCSR_STR(BUSERR));
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pos += seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d"
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" len=%d)\n",
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dcmd,
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DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR),
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DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG),
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DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN),
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DCMD_STR(ENDIAN), burst, width, dcmd & DCMD_LENGTH);
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pos += seq_printf(s, "\tDSADR = %08x\n", DSADR(chan));
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pos += seq_printf(s, "\tDTADR = %08x\n", DTADR(chan));
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pos += seq_printf(s, "\tDDADR = %08x\n", DDADR(chan));
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return pos;
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}
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static int dbg_show_state(struct seq_file *s, void *p)
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{
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int pos = 0;
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/* basic device status */
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pos += seq_printf(s, "DMA engine status\n");
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pos += seq_printf(s, "\tChannel number: %d\n", num_dma_channels);
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return pos;
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}
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#define DBGFS_FUNC_DECL(name) \
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static int dbg_open_##name(struct inode *inode, struct file *file) \
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{ \
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return single_open(file, dbg_show_##name, inode->i_private); \
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} \
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static const struct file_operations dbg_fops_##name = { \
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.owner = THIS_MODULE, \
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.open = dbg_open_##name, \
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.llseek = seq_lseek, \
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.read = seq_read, \
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.release = single_release, \
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}
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DBGFS_FUNC_DECL(state);
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DBGFS_FUNC_DECL(chan_state);
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DBGFS_FUNC_DECL(descriptors);
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DBGFS_FUNC_DECL(requester_chan);
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static struct dentry *pxa_dma_dbg_alloc_chan(int ch, struct dentry *chandir)
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{
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char chan_name[11];
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struct dentry *chan, *chan_state = NULL, *chan_descr = NULL;
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struct dentry *chan_reqs = NULL;
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void *dt;
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scnprintf(chan_name, sizeof(chan_name), "%d", ch);
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chan = debugfs_create_dir(chan_name, chandir);
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dt = (void *)ch;
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if (chan)
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chan_state = debugfs_create_file("state", 0400, chan, dt,
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&dbg_fops_chan_state);
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if (chan_state)
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chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
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&dbg_fops_descriptors);
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if (chan_descr)
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chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
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&dbg_fops_requester_chan);
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if (!chan_reqs)
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goto err_state;
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return chan;
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err_state:
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debugfs_remove_recursive(chan);
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return NULL;
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}
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static void pxa_dma_init_debugfs(void)
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{
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int i;
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struct dentry *chandir;
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dbgfs_root = debugfs_create_dir(DMA_DEBUG_NAME, NULL);
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if (IS_ERR(dbgfs_root) || !dbgfs_root)
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goto err_root;
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dbgfs_state = debugfs_create_file("state", 0400, dbgfs_root, NULL,
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&dbg_fops_state);
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if (!dbgfs_state)
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goto err_state;
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dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels,
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GFP_KERNEL);
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if (!dbgfs_state)
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goto err_alloc;
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chandir = debugfs_create_dir("channels", dbgfs_root);
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if (!chandir)
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goto err_chandir;
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for (i = 0; i < num_dma_channels; i++) {
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dbgfs_chan[i] = pxa_dma_dbg_alloc_chan(i, chandir);
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if (!dbgfs_chan[i])
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goto err_chans;
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}
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return;
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err_chans:
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err_chandir:
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kfree(dbgfs_chan);
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err_alloc:
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err_state:
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debugfs_remove_recursive(dbgfs_root);
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err_root:
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pr_err("pxa_dma: debugfs is not available\n");
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}
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static void __exit pxa_dma_cleanup_debugfs(void)
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{
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debugfs_remove_recursive(dbgfs_root);
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}
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#else
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static inline void pxa_dma_init_debugfs(void) {}
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static inline void pxa_dma_cleanup_debugfs(void) {}
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#endif
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int pxa_request_dma (char *name, pxa_dma_prio prio,
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void (*irq_handler)(int, void *),
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void *data)
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@ -130,6 +374,7 @@ int __init pxa_init_dma(int irq, int num_ch)
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for (i = 0; i < num_ch; i++) {
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DCSR(i) = 0;
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dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
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spin_lock_init(&dma_channels[i].lock);
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}
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ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
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@ -138,7 +383,9 @@ int __init pxa_init_dma(int irq, int num_ch)
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kfree(dma_channels);
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return ret;
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}
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num_dma_channels = num_ch;
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pxa_dma_init_debugfs();
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return 0;
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}
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