usb: fixes for v5.2-rc5
A single fix to take into account the PHY width during initialization of dwc2 driver. This change allows deviceTree to pass PHY width if necessary. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> -----BEGIN PGP SIGNATURE----- iQJRBAABCAA7FiEElLzh7wn96CXwjh2IzL64meEamQYFAl0LTUodHGZlbGlwZS5i YWxiaUBsaW51eC5pbnRlbC5jb20ACgkQzL64meEamQZQ9Q/8D4uLWzTwmPEukuPb 6ctQPU+UKK9nzuSIG8dAYkMrzvRXs5tdUjEz2khCiqYjVdR0+Xu0lAQryD8loJY8 375K6VzrEuVgRwiNdcXQklLdEpv7aT9nfbi1L61l6V+7MLkNAsQ/HHDgaCDCIcIz Oe3yYToFYyQO4hZR3TZHlgnE+kCJQx/3JHa2JRRu8sxvMRNWfJ6WwPBbTXEzM33Z x0Bl7RZ8YCUoLBYw4VIlGJSEPvza3XKcJi1qk7kK34i1bQSNAkQl94wZc3ZwUPTB XhUxafs3byHOWqe392Qc7nmfP2RZMxcCPOwmX/fi5Hu1C8JKgEII+iPOhL+NISxv TjtbMxl/Lk6jgf2K8vfSDDKLnq66g4IHNkvArnU8QACvymvYeKqsD63t5CRU+9d9 6UeW54QXLnn5jfV2PNQLGmm8aprfwu0wvSvYCF7ykTNlzmVovVhctG3OjAAj7kGJ OnaYlkPa936kGKGba4XtFcaSbfjLbq5lqNa8ebnAIDo9zIOZRGsEgkd8UZ7cj7hK VEmrCU1hV+VLDtNdKakcTmvlDIYwFApEacZiPQ+o2axIbaE5JmWMIGzu2ZgCnyQE bqBg216s8RewdF1bcnvL6PX6OlyFkG9X3r1D+x+HXo1eXIfxlZiVqZFCPTpqX3g8 Ymy5uacPA8JijPftDj/7rFBHFb0= =qmku -----END PGP SIGNATURE----- Merge tag 'fixes-for-v5.2-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-linus Felipe writes: usb: fixes for v5.2-rc5 A single fix to take into account the PHY width during initialization of dwc2 driver. This change allows deviceTree to pass PHY width if necessary. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> * tag 'fixes-for-v5.2-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb: usb: dwc2: Use generic PHY width in params setup
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commit
d28bdaff5e
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@ -253,6 +253,15 @@ static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
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val = (hsotg->hw_params.utmi_phy_data_width ==
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GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
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if (hsotg->phy) {
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/*
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* If using the generic PHY framework, check if the PHY bus
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* width is 8-bit and set the phyif appropriately.
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*/
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if (phy_get_bus_width(hsotg->phy) == 8)
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val = 8;
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}
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hsotg->params.phy_utmi_width = val;
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}
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@ -271,15 +271,6 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
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hsotg->plat = dev_get_platdata(hsotg->dev);
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if (hsotg->phy) {
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/*
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* If using the generic PHY framework, check if the PHY bus
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* width is 8-bit and set the phyif appropriately.
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*/
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if (phy_get_bus_width(hsotg->phy) == 8)
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hsotg->params.phy_utmi_width = 8;
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}
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/* Clock */
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hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
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if (IS_ERR(hsotg->clk)) {
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