V4L/DVB (9110): cx18: Add default behavior of checking and retrying PCI MMIO accesses
cx18: Add default behavior of checking and retrying PCI MMIO accesses. The concept of checking and retrying PCI MMIO accesses for better reliability in older motherboards was suggested by Steve Toth <stoth@linuxtv.org>. This change implements MMIO retries and the retry_mmio module parameter that is enabled by default. Limited experiments have shown this is more reliable than the mmio_ndelay parameter. mmio_ndelay has insignificant effect with retries enabled. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Andy Walls
Mauro Carvalho Chehab
parent
7f98767852
commit
d267d85101
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@ -42,6 +42,12 @@ int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
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return 0;
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}
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int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
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{
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cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
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return 0;
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}
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u8 cx18_av_read(struct cx18 *cx, u16 addr)
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{
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u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
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@ -55,6 +61,11 @@ u32 cx18_av_read4(struct cx18 *cx, u16 addr)
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return cx18_read_reg(cx, 0xc40000 + addr);
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}
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u32 cx18_av_read4_noretry(struct cx18 *cx, u16 addr)
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{
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return cx18_read_reg_noretry(cx, 0xc40000 + addr);
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}
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int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
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u8 or_value)
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{
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@ -301,8 +301,10 @@ struct cx18_av_state {
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/* cx18_av-core.c */
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int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
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int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
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int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
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u8 cx18_av_read(struct cx18 *cx, u16 addr);
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u32 cx18_av_read4(struct cx18 *cx, u16 addr);
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u32 cx18_av_read4_noretry(struct cx18 *cx, u16 addr);
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int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
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int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
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int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg);
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@ -50,7 +50,7 @@ int cx18_av_loadfw(struct cx18 *cx)
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cx18_av_write4(cx, 0x8100, 0x00010000);
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/* Put the 8051 in reset and enable firmware upload */
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cx18_av_write4(cx, CXADEC_DL_CTL, 0x0F000000);
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cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
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ptr = fw->data;
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size = fw->size;
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@ -59,22 +59,28 @@ int cx18_av_loadfw(struct cx18 *cx)
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u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
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u32 value = 0;
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int retries2;
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int unrec_err = 0;
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for (retries2 = 0; retries2 < 5; retries2++) {
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cx18_av_write4(cx, CXADEC_DL_CTL, dl_control);
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for (retries2 = 0; retries2 < CX18_MAX_MMIO_RETRIES;
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retries2++) {
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cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
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dl_control);
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udelay(10);
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value = cx18_av_read4(cx, CXADEC_DL_CTL);
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value = cx18_av_read4_noretry(cx,
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CXADEC_DL_CTL);
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if (value == dl_control)
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break;
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/* Check if we can correct the byte by changing
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the address. We can only write the lower
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address byte of the address. */
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if ((value & 0x3F00) != (dl_control & 0x3F00)) {
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retries2 = 5;
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unrec_err = 1;
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break;
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}
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}
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if (retries2 >= 5)
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cx18_log_write_retries(cx, retries2,
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cx->reg_mem + 0xc40000 + CXADEC_DL_CTL);
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if (unrec_err || retries2 >= CX18_MAX_MMIO_RETRIES)
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break;
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}
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if (i == size)
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@ -96,6 +96,7 @@ static int enc_pcm_buffers = CX18_DEFAULT_ENC_PCM_BUFFERS;
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static int cx18_pci_latency = 1;
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int cx18_retry_mmio = 1;
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int cx18_debug;
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module_param_array(tuner, int, &tuner_c, 0644);
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@ -106,6 +107,7 @@ module_param_string(pal, pal, sizeof(pal), 0644);
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module_param_string(secam, secam, sizeof(secam), 0644);
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module_param_string(ntsc, ntsc, sizeof(ntsc), 0644);
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module_param_named(debug, cx18_debug, int, 0644);
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module_param_named(retry_mmio, cx18_retry_mmio, int, 0644);
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module_param(cx18_pci_latency, int, 0644);
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module_param(cx18_first_minor, int, 0644);
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@ -147,6 +149,9 @@ MODULE_PARM_DESC(debug,
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MODULE_PARM_DESC(cx18_pci_latency,
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"Change the PCI latency to 64 if lower: 0 = No, 1 = Yes,\n"
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"\t\t\tDefault: Yes");
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MODULE_PARM_DESC(retry_mmio,
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"Check and retry memory mapped IO accesses\n"
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"\t\t\tDefault: 1 [Yes]");
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MODULE_PARM_DESC(mmio_ndelay,
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"Delay (ns) for each CX23418 memory mapped IO access.\n"
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"\t\t\tTry larger values that are close to a multiple of the\n"
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@ -827,6 +832,7 @@ err:
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if (retval == 0)
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retval = -ENODEV;
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CX18_ERR("Error %d on initialization\n", retval);
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cx18_log_statistics(cx);
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kfree(cx18_cards[cx18_cards_active]);
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cx18_cards[cx18_cards_active] = NULL;
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@ -931,6 +937,7 @@ static void cx18_remove(struct pci_dev *pci_dev)
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pci_disable_device(cx->dev);
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cx18_log_statistics(cx);
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CX18_INFO("Removed %s, card #%d\n", cx->card_name, cx->num);
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}
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@ -171,6 +171,7 @@
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#define CX18_MAX_PGM_INDEX (400)
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extern int cx18_retry_mmio; /* enable check & retry of mmio accesses */
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extern int cx18_debug;
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@ -344,6 +345,13 @@ struct cx18_i2c_algo_callback_data {
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int bus_index; /* 0 or 1 for the cx23418's 1st or 2nd I2C bus */
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};
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#define CX18_MAX_MMIO_RETRIES 10
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struct cx18_mmio_stats {
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atomic_t retried_write[CX18_MAX_MMIO_RETRIES+1];
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atomic_t retried_read[CX18_MAX_MMIO_RETRIES+1];
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};
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/* Struct to hold info about cx18 cards */
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struct cx18 {
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int num; /* board number, -1 during init! */
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@ -433,6 +441,9 @@ struct cx18 {
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u32 gpio_val;
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struct mutex gpio_lock;
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/* Statistics */
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struct cx18_mmio_stats mmio_stats;
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/* v4l2 and User settings */
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/* codec settings */
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@ -24,6 +24,131 @@
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#include "cx18-io.h"
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#include "cx18-irq.h"
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void cx18_log_statistics(struct cx18 *cx)
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{
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int i;
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if (!(cx18_debug & CX18_DBGFLG_INFO))
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return;
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for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
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CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
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atomic_read(&cx->mmio_stats.retried_write[i]));
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for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
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CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
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atomic_read(&cx->mmio_stats.retried_read[i]));
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return;
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}
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void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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cx18_raw_writel_noretry(cx, val, addr);
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if (val == cx18_raw_readl_noretry(cx, addr))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u32 val;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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val = cx18_raw_readl_noretry(cx, addr);
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if (val != 0xffffffff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u16 val;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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val = cx18_raw_readw_noretry(cx, addr);
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if (val != 0xffff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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cx18_writel_noretry(cx, val, addr);
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if (val == cx18_readl_noretry(cx, addr))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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cx18_writew_noretry(cx, val, addr);
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if (val == cx18_readw_noretry(cx, addr))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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cx18_writeb_noretry(cx, val, addr);
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if (val == cx18_readb_noretry(cx, addr))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u32 val;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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val = cx18_readl_noretry(cx, addr);
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if (val != 0xffffffff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u16 val;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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val = cx18_readw_noretry(cx, addr);
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if (val != 0xffff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u8 val;
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for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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val = cx18_readb_noretry(cx, addr);
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if (val != 0xff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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void cx18_memcpy_fromio(struct cx18 *cx, void *to,
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const void __iomem *from, unsigned int len)
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{
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@ -127,13 +252,3 @@ void cx18_setup_page(struct cx18 *cx, u32 addr)
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val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
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cx18_write_reg(cx, val, 0xD000F8);
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}
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/* Tries to recover from the CX23418 responding improperly on the PCI bus */
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int cx18_pci_try_recover(struct cx18 *cx)
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{
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u16 status;
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pci_read_config_word(cx->dev, PCI_STATUS, &status);
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pci_write_config_word(cx->dev, PCI_STATUS, status);
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return 0;
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}
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@ -31,102 +31,343 @@ static inline void cx18_io_delay(struct cx18 *cx)
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ndelay(cx->options.mmio_ndelay);
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}
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/*
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* Readback and retry of MMIO access for reliability:
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* The concept was suggested by Steve Toth <stoth@linuxtv.org>.
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* The implmentation is the fault of Andy Walls <awalls@radix.net>.
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*/
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/* Statistics gathering */
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static inline
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void cx18_log_write_retries(struct cx18 *cx, int i, const void *addr)
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{
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if (i > CX18_MAX_MMIO_RETRIES)
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i = CX18_MAX_MMIO_RETRIES;
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atomic_inc(&cx->mmio_stats.retried_write[i]);
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return;
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}
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static inline
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void cx18_log_read_retries(struct cx18 *cx, int i, const void *addr)
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{
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if (i > CX18_MAX_MMIO_RETRIES)
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i = CX18_MAX_MMIO_RETRIES;
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atomic_inc(&cx->mmio_stats.retried_read[i]);
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return;
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}
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void cx18_log_statistics(struct cx18 *cx);
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/* Non byteswapping memory mapped IO */
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static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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static inline
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void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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__raw_writel(val, addr);
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cx18_io_delay(cx);
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}
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static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
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void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr);
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static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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if (cx18_retry_mmio)
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cx18_raw_writel_retry(cx, val, addr);
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else
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cx18_raw_writel_noretry(cx, val, addr);
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}
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static inline
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u32 cx18_raw_readl_noretry(struct cx18 *cx, const void __iomem *addr)
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{
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u32 ret = __raw_readl(addr);
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cx18_io_delay(cx);
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return ret;
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}
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static inline u16 cx18_raw_readw(struct cx18 *cx, const void __iomem *addr)
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u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr);
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static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
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{
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if (cx18_retry_mmio)
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return cx18_raw_readl_retry(cx, addr);
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return cx18_raw_readl_noretry(cx, addr);
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}
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static inline
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u16 cx18_raw_readw_noretry(struct cx18 *cx, const void __iomem *addr)
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{
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u16 ret = __raw_readw(addr);
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cx18_io_delay(cx);
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return ret;
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}
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u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr);
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static inline u16 cx18_raw_readw(struct cx18 *cx, const void __iomem *addr)
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{
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if (cx18_retry_mmio)
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return cx18_raw_readw_retry(cx, addr);
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return cx18_raw_readw_noretry(cx, addr);
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}
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/* Normal memory mapped IO */
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static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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static inline
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void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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writel(val, addr);
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cx18_io_delay(cx);
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}
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static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
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void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr);
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static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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if (cx18_retry_mmio)
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cx18_writel_retry(cx, val, addr);
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else
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cx18_writel_noretry(cx, val, addr);
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}
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static inline
|
||||
void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
|
||||
{
|
||||
writew(val, addr);
|
||||
cx18_io_delay(cx);
|
||||
}
|
||||
|
||||
static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
|
||||
void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr);
|
||||
|
||||
static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
|
||||
{
|
||||
if (cx18_retry_mmio)
|
||||
cx18_writew_retry(cx, val, addr);
|
||||
else
|
||||
cx18_writew_noretry(cx, val, addr);
|
||||
}
|
||||
|
||||
|
||||
static inline
|
||||
void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr)
|
||||
{
|
||||
writeb(val, addr);
|
||||
cx18_io_delay(cx);
|
||||
}
|
||||
|
||||
static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
|
||||
void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr);
|
||||
|
||||
static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
|
||||
{
|
||||
if (cx18_retry_mmio)
|
||||
cx18_writeb_retry(cx, val, addr);
|
||||
else
|
||||
cx18_writeb_noretry(cx, val, addr);
|
||||
}
|
||||
|
||||
|
||||
static inline u32 cx18_readl_noretry(struct cx18 *cx, const void __iomem *addr)
|
||||
{
|
||||
u32 ret = readl(addr);
|
||||
cx18_io_delay(cx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
|
||||
u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr);
|
||||
|
||||
static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
|
||||
{
|
||||
if (cx18_retry_mmio)
|
||||
return cx18_readl_retry(cx, addr);
|
||||
|
||||
return cx18_readl_noretry(cx, addr);
|
||||
}
|
||||
|
||||
|
||||
static inline u16 cx18_readw_noretry(struct cx18 *cx, const void __iomem *addr)
|
||||
{
|
||||
u16 ret = readw(addr);
|
||||
cx18_io_delay(cx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr);
|
||||
|
||||
static inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr)
|
||||
{
|
||||
if (cx18_retry_mmio)
|
||||
return cx18_readw_retry(cx, addr);
|
||||
|
||||
return cx18_readw_noretry(cx, addr);
|
||||
}
|
||||
|
||||
|
||||
static inline u8 cx18_readb_noretry(struct cx18 *cx, const void __iomem *addr)
|
||||
{
|
||||
u8 ret = readb(addr);
|
||||
cx18_io_delay(cx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr);
|
||||
|
||||
static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
|
||||
{
|
||||
if (cx18_retry_mmio)
|
||||
return cx18_readb_retry(cx, addr);
|
||||
|
||||
return cx18_readb_noretry(cx, addr);
|
||||
}
|
||||
|
||||
|
||||
static inline
|
||||
u32 cx18_write_sync_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
|
||||
{
|
||||
cx18_writel_noretry(cx, val, addr);
|
||||
return cx18_readl_noretry(cx, addr);
|
||||
}
|
||||
|
||||
static inline
|
||||
u32 cx18_write_sync_retry(struct cx18 *cx, u32 val, void __iomem *addr)
|
||||
{
|
||||
cx18_writel_retry(cx, val, addr);
|
||||
return cx18_readl_retry(cx, addr);
|
||||
}
|
||||
|
||||
static inline u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr)
|
||||
{
|
||||
cx18_writel(cx, val, addr);
|
||||
return cx18_readl(cx, addr);
|
||||
if (cx18_retry_mmio)
|
||||
return cx18_write_sync_retry(cx, val, addr);
|
||||
|
||||
return cx18_write_sync_noretry(cx, val, addr);
|
||||
}
|
||||
|
||||
|
||||
void cx18_memcpy_fromio(struct cx18 *cx, void *to,
|
||||
const void __iomem *from, unsigned int len);
|
||||
void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count);
|
||||
|
||||
|
||||
/* Access "register" region of CX23418 memory mapped I/O */
|
||||
static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg)
|
||||
{
|
||||
cx18_writel_noretry(cx, val, cx->reg_mem + reg);
|
||||
}
|
||||
|
||||
static inline void cx18_write_reg_retry(struct cx18 *cx, u32 val, u32 reg)
|
||||
{
|
||||
cx18_writel_retry(cx, val, cx->reg_mem + reg);
|
||||
}
|
||||
|
||||
static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
|
||||
{
|
||||
cx18_writel(cx, val, cx->reg_mem + reg);
|
||||
if (cx18_retry_mmio)
|
||||
cx18_write_reg_retry(cx, val, reg);
|
||||
else
|
||||
cx18_write_reg_noretry(cx, val, reg);
|
||||
}
|
||||
|
||||
|
||||
static inline u32 cx18_read_reg_noretry(struct cx18 *cx, u32 reg)
|
||||
{
|
||||
return cx18_readl_noretry(cx, cx->reg_mem + reg);
|
||||
}
|
||||
|
||||
static inline u32 cx18_read_reg_retry(struct cx18 *cx, u32 reg)
|
||||
{
|
||||
return cx18_readl_retry(cx, cx->reg_mem + reg);
|
||||
}
|
||||
|
||||
static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg)
|
||||
{
|
||||
return cx18_readl(cx, cx->reg_mem + reg);
|
||||
if (cx18_retry_mmio)
|
||||
return cx18_read_reg_retry(cx, reg);
|
||||
|
||||
return cx18_read_reg_noretry(cx, reg);
|
||||
}
|
||||
|
||||
|
||||
static inline u32 cx18_write_reg_sync_noretry(struct cx18 *cx, u32 val, u32 reg)
|
||||
{
|
||||
return cx18_write_sync_noretry(cx, val, cx->reg_mem + reg);
|
||||
}
|
||||
|
||||
static inline u32 cx18_write_reg_sync_retry(struct cx18 *cx, u32 val, u32 reg)
|
||||
{
|
||||
return cx18_write_sync_retry(cx, val, cx->reg_mem + reg);
|
||||
}
|
||||
|
||||
static inline u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg)
|
||||
{
|
||||
return cx18_write_sync(cx, val, cx->reg_mem + reg);
|
||||
if (cx18_retry_mmio)
|
||||
return cx18_write_reg_sync_retry(cx, val, reg);
|
||||
|
||||
return cx18_write_reg_sync_noretry(cx, val, reg);
|
||||
}
|
||||
|
||||
|
||||
/* Access "encoder memory" region of CX23418 memory mapped I/O */
|
||||
static inline void cx18_write_enc_noretry(struct cx18 *cx, u32 val, u32 addr)
|
||||
{
|
||||
cx18_writel_noretry(cx, val, cx->enc_mem + addr);
|
||||
}
|
||||
|
||||
static inline void cx18_write_enc_retry(struct cx18 *cx, u32 val, u32 addr)
|
||||
{
|
||||
cx18_writel_retry(cx, val, cx->enc_mem + addr);
|
||||
}
|
||||
|
||||
static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
|
||||
{
|
||||
cx18_writel(cx, val, cx->enc_mem + addr);
|
||||
if (cx18_retry_mmio)
|
||||
cx18_write_enc_retry(cx, val, addr);
|
||||
else
|
||||
cx18_write_enc_noretry(cx, val, addr);
|
||||
}
|
||||
|
||||
|
||||
static inline u32 cx18_read_enc_noretry(struct cx18 *cx, u32 addr)
|
||||
{
|
||||
return cx18_readl_noretry(cx, cx->enc_mem + addr);
|
||||
}
|
||||
|
||||
static inline u32 cx18_read_enc_retry(struct cx18 *cx, u32 addr)
|
||||
{
|
||||
return cx18_readl_retry(cx, cx->enc_mem + addr);
|
||||
}
|
||||
|
||||
static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr)
|
||||
{
|
||||
return cx18_readl(cx, cx->enc_mem + addr);
|
||||
if (cx18_retry_mmio)
|
||||
return cx18_read_enc_retry(cx, addr);
|
||||
|
||||
return cx18_read_enc_noretry(cx, addr);
|
||||
}
|
||||
|
||||
static inline u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
|
||||
static inline
|
||||
u32 cx18_write_enc_sync_noretry(struct cx18 *cx, u32 val, u32 addr)
|
||||
{
|
||||
return cx18_write_sync(cx, val, cx->enc_mem + addr);
|
||||
return cx18_write_sync_noretry(cx, val, cx->enc_mem + addr);
|
||||
}
|
||||
|
||||
static inline
|
||||
u32 cx18_write_enc_sync_retry(struct cx18 *cx, u32 val, u32 addr)
|
||||
{
|
||||
return cx18_write_sync_retry(cx, val, cx->enc_mem + addr);
|
||||
}
|
||||
|
||||
static inline
|
||||
u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
|
||||
{
|
||||
if (cx18_retry_mmio)
|
||||
return cx18_write_enc_sync_retry(cx, val, addr);
|
||||
|
||||
return cx18_write_enc_sync_noretry(cx, val, addr);
|
||||
}
|
||||
|
||||
void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);
|
||||
void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
|
||||
|
|
@ -134,7 +375,4 @@ void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
|
|||
void cx18_sw2_irq_disable(struct cx18 *cx, u32 val);
|
||||
void cx18_setup_page(struct cx18 *cx, u32 addr);
|
||||
|
||||
/* Tries to recover from the CX23418 responding improperly on the PCI bus */
|
||||
int cx18_pci_try_recover(struct cx18 *cx);
|
||||
|
||||
#endif /* CX18_IO_H */
|
||||
|
|
|
|||
|
|
@ -752,6 +752,7 @@ static int cx18_log_status(struct file *file, void *fh)
|
|||
CX18_INFO("Read MPEG/VBI: %lld/%lld bytes\n",
|
||||
(long long)cx->mpg_data_received,
|
||||
(long long)cx->vbi_data_inserted);
|
||||
cx18_log_statistics(cx);
|
||||
CX18_INFO("================== END STATUS CARD #%d ==================\n", cx->num);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue